feat(build): add COMPILER_ENABLE_RISCV_ZCMP option

Applicable for chips affected by interrupt issue:
  - ESP32C5
  - ESP32C61
  - ESP32H4

For all other chips that support the ZCMP extension without issues,
it will be enabled unconditionally.

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -239,10 +239,26 @@ config SOC_CPU_HAS_LOCKUP_RESET
     bool
     default y
 
+config SOC_CPU_HAS_ZC_EXTENSIONS
+    bool
+    default y
+
+config SOC_CPU_HAS_ZB_EXTENSIONS
+    bool
+    default y
+
 config SOC_CPU_ZCMP_WORKAROUND
     bool
     default y
 
+config SOC_CPU_ZCMP_PUSH_REVERSED
+    bool
+    default y
+
+config SOC_CPU_ZCMP_POPRET_ISSUE
+    bool
+    default y
+
 config SOC_DMA_CAN_ACCESS_FLASH
     bool
     default y

components/soc/esp32h4/include/soc/soc_caps.h

@@ -175,7 +175,12 @@
 #define SOC_HP_CPU_HAS_MULTIPLE_CORES   1   // Convenience boolean macro used to determine if a target has multiple cores.
 #define SOC_CPU_HAS_LOCKUP_RESET        1
 
+#define SOC_CPU_HAS_ZC_EXTENSIONS       1
+#define SOC_CPU_HAS_ZB_EXTENSIONS       1
+
 #define SOC_CPU_ZCMP_WORKAROUND         1
+#define SOC_CPU_ZCMP_PUSH_REVERSED      1
+#define SOC_CPU_ZCMP_POPRET_ISSUE       1
 
 /*-------------------------- DMA Common CAPS ----------------------------------------*/
 #define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */