feat(build): add COMPILER_ENABLE_RISCV_ZCMP option

Applicable for chips affected by interrupt issue:
  - ESP32C5
  - ESP32C61
  - ESP32H4

For all other chips that support the ZCMP extension without issues,
it will be enabled unconditionally.

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -487,6 +487,14 @@ config SOC_CPU_ZCMP_WORKAROUND
     bool
     default y
 
+config SOC_CPU_ZCMP_PUSH_REVERSED
+    bool
+    default y
+
+config SOC_CPU_ZCMP_POPRET_ISSUE
+    bool
+    default y
+
 config SOC_DS_SIGNATURE_MAX_BIT_LEN
     int
     default 3072

components/soc/esp32c5/include/soc/soc_caps.h

@@ -183,6 +183,8 @@
 #define SOC_CPU_HAS_LOCKUP_RESET        1
 
 #define SOC_CPU_ZCMP_WORKAROUND         1
+#define SOC_CPU_ZCMP_PUSH_REVERSED      1
+#define SOC_CPU_ZCMP_POPRET_ISSUE       1
 
 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
 /** The maximum length of a Digital Signature in bits. */