diff --git a/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h b/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h
index a57fbd83733..aee64445668 100644
--- a/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h
+++ b/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h
@@ -105,7 +105,7 @@ static inline void analog_cmpr_ll_set_clk_src(int unit_id, ana_cmpr_clk_src_t cl
     case ANA_CMPR_CLK_SRC_RC_FAST:
         HP_SYS_CLKRST.zero_det_ctrl0.reg_zero_det_clk_src_sel = 1;
         break;
-    case ANA_CMPR_CLK_SRC_PLL_F80M:
+    case ANA_CMPR_CLK_SRC_REF_F80M:
         HP_SYS_CLKRST.zero_det_ctrl0.reg_zero_det_clk_src_sel = 2;
         break;
     default:
diff --git a/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h b/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h
index f2c798d6520..24a2220ee7a 100644
--- a/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h
+++ b/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h
@@ -1086,7 +1086,7 @@ static inline void emac_ll_clock_enable_ptp(void *ext_regs, soc_periph_emac_ptp_
     case EMAC_PTP_CLK_SRC_XTAL:
         clk_src_val = 0;
         break;
-    case EMAC_PTP_CLK_SRC_PLL_F80M:
+    case EMAC_PTP_CLK_SRC_REF_F80M:
         clk_src_val = 1;
         break;
     default:
diff --git a/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h b/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h
index 49b1d2fa949..cf3b484bf9f 100644
--- a/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h
+++ b/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h
@@ -173,7 +173,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.rmt_ctrl0, reg_rmt_clk_div_numerator, divider_numerator);
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.rmt_ctrl0, reg_rmt_clk_div_denominator, divider_denominator);
     switch (src) {
-    case RMT_CLK_SRC_PLL_F80M:
+    case RMT_CLK_SRC_REF_F80M:
         HP_SYS_CLKRST.rmt_ctrl0.reg_rmt_clk_src_sel = 2;
         break;
     case RMT_CLK_SRC_RC_FAST:
diff --git a/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h b/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h
index 54b07254130..010417360b8 100644
--- a/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h
+++ b/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h
@@ -104,7 +104,7 @@ static inline void _timer_ll_set_clock_source(int group_id, uint32_t timer_num,
     case GPTIMER_CLK_SRC_XTAL:
         clk_id = 0;
         break;
-    case GPTIMER_CLK_SRC_PLL_F80M:
+    case GPTIMER_CLK_SRC_REF_F80M:
         clk_id = 2;
         break;
     case GPTIMER_CLK_SRC_RC_FAST:
diff --git a/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h b/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h
index 541f75a3d19..5c77f76551b 100644
--- a/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h
+++ b/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h
@@ -167,7 +167,7 @@ static inline void twai_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t
     case TWAI_CLK_SRC_XTAL:
         clk_sel = 0;
         break;
-    case TWAI_CLK_SRC_PLL_F80M:
+    case TWAI_CLK_SRC_REF_F80M:
         clk_sel = 2;
         break;
     default:
diff --git a/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h b/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h
index 381fb94f5d7..9a3ba9f486d 100644
--- a/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h
+++ b/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h
@@ -433,7 +433,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
     case UART_SCLK_RTC:
         sel_value = 1;
         break;
-    case UART_SCLK_PLL_F80M:
+    case UART_SCLK_REF_F80M:
         sel_value = 2;
         break;
     default:
@@ -484,7 +484,7 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
             *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
         case 2:
-            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
+            *source_clk = (soc_module_clk_t)UART_SCLK_REF_F80M;
             break;
         }
     } else {
diff --git a/components/hal/esp32s31/include/hal/etm_ll.h b/components/hal/esp32s31/include/hal/etm_ll.h
index a793e5bafbe..7d4376e95a6 100644
--- a/components/hal/esp32s31/include/hal/etm_ll.h
+++ b/components/hal/esp32s31/include/hal/etm_ll.h
@@ -74,7 +74,7 @@ static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_
     case ETM_CLK_SRC_RC_FAST:
         HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 1;
         break;
-    case ETM_CLK_SRC_PLL_F80M:
+    case ETM_CLK_SRC_REF_F80M:
         HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 2;
         break;
     default:
diff --git a/components/soc/esp32s31/include/soc/clk_tree_defs.h b/components/soc/esp32s31/include/soc/clk_tree_defs.h
index 4d13caf6b7d..4504a342eef 100644
--- a/components/soc/esp32s31/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32s31/include/soc/clk_tree_defs.h
@@ -147,7 +147,6 @@ typedef enum {
     SOC_MOD_CLK_PLL_F50M,                      /*!< PLL_F50M_CLK is from ref_50m (clock gating + configurable divider). Shares `ref_500m_sel` with PLL_F25M; frequency via esp_clk_tree_src_set_freq_hz (CPLL or MPLL upstream). */
     SOC_MOD_CLK_PLL_F60M,                      /*!< PLL_F60M_CLK is derived from BBPLL (clock gating + default divider 8), its default frequency is 60MHz */
     SOC_MOD_CLK_REF_F80M,                      /*!< REF_F80M_CLK from ref_80m (gate). Mux: BBPLL/6 (default) or XTALx2 80MHz (`reg_ref_80m_sel`). Frequency 80MHz either path. */
-    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from BBPLL (clock gating + default divider 6), its default frequency is 80MHz */
     SOC_MOD_CLK_PLL_F120M,                     /*!< PLL_F120M_CLK is derived from BBPLL (clock gating + default divider 4), its default frequency is 120MHz */
     SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from BBPLL (clock gating + default divider 3), its default frequency is 160MHz */
     SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from BBPLL (clock gating + default divider 2), its default frequency is 240MHz */
@@ -227,25 +226,25 @@ typedef enum {
  * }
  * @endcode
  */
-#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief Type of GPTimer clock source
  */
 typedef enum {
-    GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    GPTIMER_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */
     GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
     GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
 //////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
 
 typedef enum {
-    ETM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    ETM_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */
     ETM_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
     ETM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+    ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M as the default choice */
 } soc_periph_etm_clk_src_t;
 
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
@@ -253,16 +252,16 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of RMT
  */
-#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+#define SOC_RMT_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief Type of RMT clock source
  */
 typedef enum {
-    RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    RMT_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */
     RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
     RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M as the default choice */
 } soc_periph_rmt_clk_src_t;
 
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
@@ -270,16 +269,16 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of UART
  */
-#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+#define SOC_UART_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
 
 /**
  * @brief Type of UART clock source, reserved for the legacy UART driver
  */
 typedef enum {
-    UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock is PLL_F80M */
+    UART_SCLK_REF_F80M = SOC_MOD_CLK_REF_F80M,           /*!< UART source clock is REF_F80M */
     UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
     UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
-    UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_REF_F80M,           /*!< UART source clock default choice is REF_F80M */
 } soc_periph_uart_clk_src_legacy_t;
 
 /**
@@ -301,7 +300,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of LEDC
  */
-#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST}
 #define SOC_LEDC_CLK_STRS {"LEDC_USE_XTAL_CLK", "LEDC_USE_PLL_DIV_CLK", "LEDC_USE_RC_FAST_CLK"}
 
 /**
@@ -309,7 +308,7 @@ typedef enum {
  */
 typedef enum {
     LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
-    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
+    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_REF_F80M,    /*!< Select REF_F80M clock as the source clock */
     LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
     LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
 } soc_periph_ledc_clk_src_legacy_t;
@@ -417,14 +416,14 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of MWDT
  */
-#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
+#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST}
 
 /**
  * @brief MWDT clock source
  */
 typedef enum {
     MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL fixed 80 MHz as the source clock */
+    MWDT_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M,   /*!< Select PLL fixed 80 MHz as the source clock */
     MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RTC fast as the source clock */
     MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,        /*!< Select XTAL 40 MHz as the default clock choice */
 } soc_periph_mwdt_clk_src_t;
@@ -436,8 +435,8 @@ typedef enum {
  */
 typedef enum {
     SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
+    SDM_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the source clock */
+    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M clock as the default clock choice */
 } soc_periph_sdm_clk_src_t;
 
 //////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
@@ -448,8 +447,8 @@ typedef enum {
 
 typedef enum {
     GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
+    GLITCH_FILTER_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M clock as the default clock choice */
 } soc_periph_glitch_filter_clk_src_t;
 
 ////////////////////////////////////////////////ANA_CMPR////////////////////////////////////////////////////
@@ -457,7 +456,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of Analog Comparator
  */
-#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F80M}
+#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_REF_F80M}
 
 /**
  * @brief Type of Analog Comparator clock source
@@ -465,8 +464,8 @@ typedef enum {
 typedef enum {
     ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
     ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-    ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default clock choice */
+    ANA_CMPR_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */
+    ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M as the default clock choice */
 } soc_periph_ana_cmpr_clk_src_t;
 
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
@@ -474,15 +473,15 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of TWAI
  */
-#define SOC_TWAI_CLKS {(soc_periph_twai_clk_src_t)SOC_MOD_CLK_XTAL, (soc_periph_twai_clk_src_t)SOC_MOD_CLK_PLL_F80M}
+#define SOC_TWAI_CLKS {(soc_periph_twai_clk_src_t)SOC_MOD_CLK_XTAL, (soc_periph_twai_clk_src_t)SOC_MOD_CLK_REF_F80M}
 
 /**
  * @brief TWAI clock source
  */
 typedef enum {
     TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    TWAI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default clock choice */
+    TWAI_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */
+    TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M,  /*!< Select REF_F80M as the default clock choice */
 } soc_periph_twai_clk_src_t;
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
@@ -791,11 +790,11 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of EMAC PTP
  */
-#define SOC_EMAC_PTP_CLK {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M}
+#define SOC_EMAC_PTP_CLK {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M}
 
 typedef enum {
     EMAC_PTP_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
-    EMAC_PTP_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,
+    EMAC_PTP_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M,
     EMAC_PTP_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
 } soc_periph_emac_ptp_clk_src_t;