mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feature/esp32h2_eco5_ecc_v5.3' into 'release/v5.3'
feat(ecc): enable ECC constant time mode for ESP32-H2 ECO5 (v5.3) See merge request espressif/esp-idf!36585
This commit is contained in:
Jiang Jiang Jian
@@ -1239,6 +1239,10 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
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bool
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default y
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config SOC_ECC_CONSTANT_TIME_POINT_MUL
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bool
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default y
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config SOC_ECDSA_USES_MPI
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bool
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default y
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@@ -0,0 +1,13 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/efuse_struct.h"
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#define ESP_SOC_GET_CHIP_REV (EFUSE.rd_mac_sys_3.wafer_version_major * 100 + EFUSE.rd_mac_sys_3.wafer_version_minor)
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#define REG_COMPATIBLE_ADDR(rev, before_addr, after_addr) ((ESP_SOC_GET_CHIP_REV >= (rev)) ? (after_addr) : (before_addr))
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -7,208 +7,388 @@
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/chip_rev.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ECDSA_CONF_REG register
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* ECDSA configure register
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*/
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#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
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/** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0;
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* The work mode bits of ECDSA Accelerator. 0: Signature Verify mode. 1: Signature
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* Generate Mode.
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*/
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#define ECDSA_WORK_MODE (BIT(0))
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#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
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#define ECDSA_WORK_MODE_V 0x00000001U
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#define ECDSA_WORK_MODE_S 0
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/** ECDSA_ECC_CURVE : R/W; bitpos: [1]; default: 0;
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* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
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*/
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#define ECDSA_ECC_CURVE (BIT(1))
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#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
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#define ECDSA_ECC_CURVE_V 0x00000001U
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#define ECDSA_ECC_CURVE_S 1
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/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0;
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* The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
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* written by software.
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*/
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#define ECDSA_SOFTWARE_SET_K (BIT(2))
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#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
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#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_K_S 2
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/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0;
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* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
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* software.
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*/
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#define ECDSA_SOFTWARE_SET_Z (BIT(3))
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#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
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#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_Z_S 3
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/** ECDSA_CLK_REG register
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* ECDSA clock gate register
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*/
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#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
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/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
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* Write 1 to force on register clock gate.
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*/
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#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
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#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
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#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
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#define ECDSA_CLK_GATE_FORCE_ON_S 0
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/** ECDSA_INT_RAW_REG register
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* ECDSA interrupt raw register, valid in level.
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*/
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#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
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/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
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#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
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#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_RAW_S 0
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/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
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#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_RAW_S 1
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/** ECDSA_INT_ST_REG register
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* ECDSA interrupt status register.
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*/
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#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
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/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_ST (BIT(0))
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#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
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#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_ST_S 0
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/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
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#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ST_S 1
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/** ECDSA_INT_ENA_REG register
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* ECDSA interrupt enable register.
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*/
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#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
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/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
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#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
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#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_ENA_S 0
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/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
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#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ENA_S 1
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/** ECDSA_INT_CLR_REG register
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* ECDSA interrupt clear register.
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*/
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#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
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/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the ecdsa_calc_done_int interrupt
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*/
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#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
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#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
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#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
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#define ECDSA_CALC_DONE_INT_CLR_S 0
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/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
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#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
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#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_CLR_S 1
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/** ECDSA_START_REG register
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* ECDSA start register
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*/
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#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
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/** ECDSA_START : WT; bitpos: [0]; default: 0;
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* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
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* after configuration.
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*/
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#define ECDSA_START (BIT(0))
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#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
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#define ECDSA_START_V 0x00000001U
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#define ECDSA_START_S 0
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/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
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* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_LOAD_DONE (BIT(1))
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#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
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#define ECDSA_LOAD_DONE_V 0x00000001U
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#define ECDSA_LOAD_DONE_S 1
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/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
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* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_GET_DONE (BIT(2))
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#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
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#define ECDSA_GET_DONE_V 0x00000001U
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#define ECDSA_GET_DONE_S 2
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/** ECDSA_STATE_REG register
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* ECDSA status register
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*/
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#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
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/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
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* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
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* state.
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*/
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#define ECDSA_BUSY 0x00000003U
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#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
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#define ECDSA_BUSY_V 0x00000003U
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#define ECDSA_BUSY_S 0
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/** ECDSA_RESULT_REG register
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* ECDSA result register
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*/
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#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
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/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
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* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
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* done.
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*/
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#define ECDSA_OPERATION_RESULT (BIT(0))
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#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
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#define ECDSA_OPERATION_RESULT_V 0x00000001U
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#define ECDSA_OPERATION_RESULT_S 0
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/** Version register */
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/** ECDSA_DATE_REG register
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* Version control register
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* Version control
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* register
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*/
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#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
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/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 35684752;
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* ECDSA version control register
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/* ECDSA_DATE : R/W; bitpos: [28:0]; default: 35684752 (0x21FFB30) for rev 0.0;
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* ECDSA_DATE : R/W; bitpos: [28:0]; default: 37761312 (0x2403120) for rev 1.2;
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* ECDSA version control
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* register
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*/
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#define ECDSA_DATE 0x0FFFFFFFU
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#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
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#define ECDSA_DATE_V 0x0FFFFFFFU
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#define ECDSA_DATE_S 0
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/**
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* @brief Get the correct value of a field according to the register version
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* @note ESP32-H2 v1.2 updated the register ECDSA_DATE_REG to a new version,
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* At the same time the value of some registers was changed
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* This macro can help to get the correct value of a field according to the register version
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** @param old: the value of the field for the old version where DATE == 0x021FFB30 (rev 0.0)
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* @param new: the value of the field for the new version where DATE == 0x2403120 (rev 1.2)
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*/
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#define ECDSA_REG_GET_OFFSET(old, new) (REG_GET_FIELD(ECDSA_DATE_REG, ECDSA_DATE) >= 0x02403120 ? (new) : (old))
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/** Configuration registers */
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/** ECDSA_CONF_REG register
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* ECDSA configure
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* register
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*/
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#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
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/* ECDSA_WORK_MODE : R/W;
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* bitpos: [0]; default: 0; for DATE == 0x21FFB30 (rev 0.0)
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* bitpos: [1:0]; default: 0; for DATE == 0x2403120 (rev 1.2)
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* The work mode bits of ECDSA Accelerator.
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* 0: Signature Generate Mode.
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* 1: Signature Verify Mode.
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* 2: Export public key Mode. (only available for DATE == 0x2403120 (rev 1.2))
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* 3: Invalid mode. (only available for DATE == 0x2403120 (rev 1.2))
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*/
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#define ECDSA_WORK_MODE ECDSA_REG_GET_OFFSET(BIT(0), 0x00000003U)
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#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
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#define ECDSA_WORK_MODE_V ECDSA_REG_GET_OFFSET(0x00000001U, 0x00000003U)
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#define ECDSA_WORK_MODE_S 0
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/* ECDSA_ECC_CURVE : R/W;
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* bitpos: [1]; default: 0; for DATE == 0x21FFB30 (rev 0.0)
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* bitpos: [2]; default: 0; for DATE == 0x2403120 (rev 1.2)
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* The ecc curve select bit of ECDSA Accelerator.
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* 0: P-192. 1: P-256.
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*/
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#define ECDSA_ECC_CURVE ECDSA_REG_GET_OFFSET(BIT(1), BIT(2))
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#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
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#define ECDSA_ECC_CURVE_V 0x00000001U
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#define ECDSA_ECC_CURVE_S ECDSA_REG_GET_OFFSET(1, 2)
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/* ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0;
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* The source of k select bit. 0: k is automatically generated by TRNG. 1:
|
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* k is written by
|
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* software.
|
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*/
|
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#define ECDSA_SOFTWARE_SET_K ECDSA_REG_GET_OFFSET(BIT(2), BIT(3))
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#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
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#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_K_S ECDSA_REG_GET_OFFSET(2, 3)
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/* ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0;
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||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is
|
||||
* written by
|
||||
* software.
|
||||
*/
|
||||
#define ECDSA_SOFTWARE_SET_Z ECDSA_REG_GET_OFFSET(BIT(3), BIT(4))
|
||||
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
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||||
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
|
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#define ECDSA_SOFTWARE_SET_Z_S ECDSA_REG_GET_OFFSET(3, 4)
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|
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/* ECDSA_K_DETERMINISTIC : R/W; bitpos: [5]; default: 0;
|
||||
* The source of k select bit. 0: k is generated from TRNG. 1: k is
|
||||
* written by
|
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* software.
|
||||
*/
|
||||
#define ECDSA_DETERMINISTIC_K (BIT(5))
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#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
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||||
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
|
||||
#define ECDSA_DETERMINISTIC_K_S 5
|
||||
|
||||
|
||||
/** Clock and reset registers */
|
||||
|
||||
/** ECDSA_CLK_REG register
|
||||
* ECDSA clock gate
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
|
||||
/* ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock
|
||||
* gate.
|
||||
*/
|
||||
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
|
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#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
|
||||
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
|
||||
#define ECDSA_CLK_GATE_FORCE_ON_S 0
|
||||
|
||||
|
||||
/** Interrupt registers */
|
||||
|
||||
/** ECDSA_INT_RAW_REG register
|
||||
* ECDSA interrupt raw register, valid in
|
||||
* level.
|
||||
*/
|
||||
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
|
||||
|
||||
/* ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_prep_done_int
|
||||
* interrupt
|
||||
* This bit was named as ECDSA_CALC_DONE_INT_RAW in rev 0.0 and changed to ECDSA_PREP_DONE_INT_RAW in rev 1.2
|
||||
* functionality is the same
|
||||
*/
|
||||
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
|
||||
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_RAW_S 0
|
||||
|
||||
/* ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_proc_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
|
||||
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_RAW_S 1
|
||||
|
||||
/* ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_post_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
|
||||
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_RAW_S 2
|
||||
|
||||
/* ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW ECDSA_REG_GET_OFFSET(BIT(1), BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_S ECDSA_REG_GET_OFFSET(1, 3)
|
||||
|
||||
/** ECDSA_INT_ST_REG register
|
||||
* ECDSA interrupt status
|
||||
* register.
|
||||
*/
|
||||
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
|
||||
|
||||
/* ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_prep_done_int
|
||||
* interrupt
|
||||
* This bit was named as ECDSA_CALC_DONE_INT_ST in rev 0.0 and changed to ECDSA_PREP_DONE_INT_ST in rev 1.2
|
||||
* functionality is the same
|
||||
*/
|
||||
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
|
||||
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_ST_S 0
|
||||
|
||||
/* ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_proc_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
|
||||
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_ST_S 1
|
||||
|
||||
/* ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_post_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_ST (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
|
||||
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_ST_S 2
|
||||
|
||||
/* ECDSA_SHA_RELEASE_INT_ST : RO;
|
||||
* bitpos: [1] for DATE == 0x21FFB30 (rev 0.0) ; default: 0;
|
||||
* bitpos: [3] for DATE == 0x2403120 (rev 1.2) ; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int
|
||||
* interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ST ECDSA_REG_GET_OFFSET(BIT(1), BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_S ECDSA_REG_GET_OFFSET(1, 3)
|
||||
|
||||
/** ECDSA_INT_ENA_REG register
|
||||
* ECDSA interrupt enable
|
||||
* register.
|
||||
*/
|
||||
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
|
||||
|
||||
/* ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_prep_done_int
|
||||
* interrupt
|
||||
* This bit was named as ECDSA_CALC_DONE_INT_ENA in rev 0.0 and changed to ECDSA_PREP_DONE_INT_ENA in rev 1.2
|
||||
* functionality is the same
|
||||
*/
|
||||
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
|
||||
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_ENA_S 0
|
||||
|
||||
/* ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_proc_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
|
||||
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_ENA_S 1
|
||||
|
||||
/* ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_post_done_int
|
||||
* interrupt
|
||||
* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
|
||||
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_ENA_S 2
|
||||
|
||||
/* ECDSA_SHA_RELEASE_INT_ENA : R/W;
|
||||
* bitpos: [1] for DATE == 0x21FFB30 (rev 0.0); default: 0;
|
||||
* bitpos: [3] for DATE == 0x2403120 (rev 1.2); default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int
|
||||
* interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA (ECDSA_REG_GET_OFFSET(BIT(1), BIT(3)))
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_S (ECDSA_REG_GET_OFFSET(1, 3))
|
||||
|
||||
/** ECDSA_INT_CLR_REG register
|
||||
* ECDSA interrupt clear
|
||||
* register.
|
||||
*/
|
||||
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
|
||||
|
||||
|
||||
/* ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_prep_done_int interrupt
|
||||
* This bit was named as ECDSA_CALC_DONE_INT_CLR in rev 0.0 and changed to ECDSA_PREP_DONE_INT_CLR in rev 1.2
|
||||
* functionality is the same
|
||||
*/
|
||||
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
|
||||
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_CLR_S 0
|
||||
|
||||
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
|
||||
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_CLR_S 1
|
||||
|
||||
/* This bit is only available for DATE == 0x2403120 (rev 1.2)
|
||||
* ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
|
||||
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
|
||||
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_CLR_S 2
|
||||
|
||||
/* ECDSA_SHA_RELEASE_INT_CLR : WT;
|
||||
* bitpos: [1] for DATE == 0x21FFB30 (rev 0.0); default: 0;
|
||||
* bitpos: [3] for DATE == 0x2403120 (rev 1.2); default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int
|
||||
* interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR (ECDSA_REG_GET_OFFSET(BIT(1), BIT(3)))
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_S (ECDSA_REG_GET_OFFSET(1, 3))
|
||||
|
||||
/** ECDSA_START_REG register
|
||||
* ECDSA start
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
|
||||
/* ECDSA_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start calculation of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after
|
||||
* configuration.
|
||||
*/
|
||||
#define ECDSA_START (BIT(0))
|
||||
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
|
||||
#define ECDSA_START_V 0x00000001U
|
||||
#define ECDSA_START_S 0
|
||||
/* ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will
|
||||
* be self-cleared after
|
||||
* configuration.
|
||||
*/
|
||||
#define ECDSA_LOAD_DONE (BIT(1))
|
||||
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
|
||||
#define ECDSA_LOAD_DONE_V 0x00000001U
|
||||
#define ECDSA_LOAD_DONE_S 1
|
||||
/* ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after
|
||||
* configuration.
|
||||
*/
|
||||
#define ECDSA_GET_DONE (BIT(2))
|
||||
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
|
||||
#define ECDSA_GET_DONE_V 0x00000001U
|
||||
#define ECDSA_GET_DONE_S 2
|
||||
|
||||
/** Status registers */
|
||||
|
||||
/** ECDSA_STATE_REG register
|
||||
* ECDSA status
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
|
||||
/* ECDSA_BUSY : RO; bitpos: [2:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2:
|
||||
* GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
#define ECDSA_BUSY 0x00000003U
|
||||
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
|
||||
#define ECDSA_BUSY_V 0x00000003U
|
||||
#define ECDSA_BUSY_S 0
|
||||
|
||||
|
||||
/** Result registers */
|
||||
|
||||
/** ECDSA_RESULT_REG register
|
||||
* ECDSA result
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
|
||||
/* ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA
|
||||
* calculation is
|
||||
* done.
|
||||
*/
|
||||
#define ECDSA_OPERATION_RESULT (BIT(0))
|
||||
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
|
||||
#define ECDSA_OPERATION_RESULT_V 0x00000001U
|
||||
#define ECDSA_OPERATION_RESULT_S 0
|
||||
|
||||
|
||||
/** SHA register */
|
||||
|
||||
/** ECDSA_SHA_MODE_REG register
|
||||
* ECDSA control SHA register
|
||||
* ECDSA control SHA
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
|
||||
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
/* ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224.
|
||||
* 2: SHA-256. Others:
|
||||
* invalid.
|
||||
*/
|
||||
#define ECDSA_SHA_MODE 0x00000007U
|
||||
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
|
||||
@@ -216,11 +396,12 @@ extern "C" {
|
||||
#define ECDSA_SHA_MODE_S 0
|
||||
|
||||
/** ECDSA_SHA_START_REG register
|
||||
* ECDSA control SHA register
|
||||
* ECDSA control SHA
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
|
||||
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_START (BIT(0))
|
||||
@@ -229,12 +410,14 @@ extern "C" {
|
||||
#define ECDSA_SHA_START_S 0
|
||||
|
||||
/** ECDSA_SHA_CONTINUE_REG register
|
||||
* ECDSA control SHA register
|
||||
* ECDSA control SHA
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
|
||||
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
/* ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter calculation of SHA Calculator in ECDSA
|
||||
* Accelerator. This bit will be self-cleared after
|
||||
* configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE (BIT(0))
|
||||
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
|
||||
@@ -242,18 +425,21 @@ extern "C" {
|
||||
#define ECDSA_SHA_CONTINUE_S 0
|
||||
|
||||
/** ECDSA_SHA_BUSY_REG register
|
||||
* ECDSA status register
|
||||
* ECDSA status
|
||||
* register
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
|
||||
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
/* ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is
|
||||
* idle.
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY (BIT(0))
|
||||
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
|
||||
#define ECDSA_SHA_BUSY_V 0x00000001U
|
||||
#define ECDSA_SHA_BUSY_S 0
|
||||
|
||||
|
||||
/** ECDSA_MESSAGE_MEM register
|
||||
* The memory that stores message.
|
||||
*/
|
||||
@@ -263,31 +449,31 @@ extern "C" {
|
||||
/** ECDSA_R_MEM register
|
||||
* The memory that stores r.
|
||||
*/
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa00, 0x340))
|
||||
#define ECDSA_R_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_S_MEM register
|
||||
* The memory that stores s.
|
||||
*/
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa20, 0x360))
|
||||
#define ECDSA_S_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_Z_MEM register
|
||||
* The memory that stores software written z.
|
||||
*/
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa40, 0x380))
|
||||
#define ECDSA_Z_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_QAX_MEM register
|
||||
* The memory that stores x coordinates of QA or software written k.
|
||||
*/
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa60, 0x3a0))
|
||||
#define ECDSA_QAX_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_QAY_MEM register
|
||||
* The memory that stores y coordinates of QA.
|
||||
*/
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa80, 0x3c0))
|
||||
#define ECDSA_QAY_MEM_SIZE_BYTES 32
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -0,0 +1,321 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Data Memory */
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* ECDSA configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** work_mode : R/W; bitpos: [0]; default: 0;
|
||||
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
|
||||
* Generate Mode.
|
||||
*/
|
||||
uint32_t work_mode:1;
|
||||
/** ecc_curve : R/W; bitpos: [1]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
uint32_t ecc_curve:1;
|
||||
/** software_set_k : R/W; bitpos: [2]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
uint32_t software_set_k:1;
|
||||
/** software_set_z : R/W; bitpos: [3]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
uint32_t software_set_z:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_conf_reg_t;
|
||||
|
||||
/** Type of start register
|
||||
* ECDSA start register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
|
||||
* after configuration.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** load_done : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t load_done:1;
|
||||
/** get_done : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t get_done:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_start_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock and reset registers */
|
||||
/** Type of clk register
|
||||
* ECDSA clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_gate_force_on:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_raw:1;
|
||||
/** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_st:1;
|
||||
/** sha_release_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_ena:1;
|
||||
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_clr:1;
|
||||
/** sha_release_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of state register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy : RO; bitpos: [1:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
uint32_t busy:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of result register
|
||||
* ECDSA result register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** operation_result : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
uint32_t operation_result:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_result_reg_t;
|
||||
|
||||
|
||||
/** Group: SHA register */
|
||||
/** Type of sha_mode register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
*/
|
||||
uint32_t sha_mode:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_sha_mode_reg_t;
|
||||
|
||||
/** Type of sha_start register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_start:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_sha_start_reg_t;
|
||||
|
||||
/** Type of sha_continue register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_continue : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_continue:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_sha_continue_reg_t;
|
||||
|
||||
/** Type of sha_busy register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_busy : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
uint32_t sha_busy:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_sha_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 35684752;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
uint32_t ecdsa_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_rev_0_0_date_reg_t;
|
||||
|
||||
/**
|
||||
* ECDSA message register
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t message[8];
|
||||
} ecdsa_rev_0_0_message_reg_t;
|
||||
|
||||
/**
|
||||
* ECDSA memory register
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t r[8];
|
||||
volatile uint32_t s[8];
|
||||
volatile uint32_t z[8];
|
||||
volatile uint32_t qax[8];
|
||||
volatile uint32_t qay[8];
|
||||
} ecdsa_rev_0_0_mem_reg_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile ecdsa_rev_0_0_conf_reg_t conf;
|
||||
volatile ecdsa_rev_0_0_clk_reg_t clk;
|
||||
volatile ecdsa_rev_0_0_int_raw_reg_t int_raw;
|
||||
volatile ecdsa_rev_0_0_int_st_reg_t int_st;
|
||||
volatile ecdsa_rev_0_0_int_ena_reg_t int_ena;
|
||||
volatile ecdsa_rev_0_0_int_clr_reg_t int_clr;
|
||||
volatile ecdsa_rev_0_0_start_reg_t start;
|
||||
volatile ecdsa_rev_0_0_state_reg_t state;
|
||||
volatile ecdsa_rev_0_0_result_reg_t result;
|
||||
uint32_t reserved_028[53];
|
||||
volatile ecdsa_rev_0_0_date_reg_t date;
|
||||
uint32_t reserved_100[64];
|
||||
volatile ecdsa_rev_0_0_sha_mode_reg_t sha_mode;
|
||||
uint32_t reserved_204[3];
|
||||
volatile ecdsa_rev_0_0_sha_start_reg_t sha_start;
|
||||
volatile ecdsa_rev_0_0_sha_continue_reg_t sha_continue;
|
||||
volatile ecdsa_rev_0_0_sha_busy_reg_t sha_busy;
|
||||
uint32_t reserved_21c[25];
|
||||
volatile ecdsa_rev_0_0_message_reg_t message;
|
||||
uint32_t reserved_2a0[472];
|
||||
volatile ecdsa_rev_0_0_mem_reg_t mem;
|
||||
} ecdsa_dev_rev_0_0_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(ecdsa_dev_rev_0_0_t) == 0xaa0, "Invalid size of ecdsa_dev_rev_0_0_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,368 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Data Memory */
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* ECDSA configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** work_mode : R/W; bitpos: [1:0]; default: 0;
|
||||
* The work mode bits of ECDSA Accelerator.
|
||||
* 0: Signature Verify Mode.
|
||||
* 1: Signature Generate Mode.
|
||||
* 2: Export Public Key Mode.
|
||||
* 3: invalid.
|
||||
*/
|
||||
uint32_t work_mode:2;
|
||||
|
||||
/** ecc_curve : R/W; bitpos: [2]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
uint32_t ecc_curve:1;
|
||||
/** software_set_k : R/W; bitpos: [3]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
uint32_t software_set_k:1;
|
||||
|
||||
/** software_set_z : R/W; bitpos: [4]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
uint32_t software_set_z:1;
|
||||
|
||||
/** ecdsa_deterministic_k : R/W; bitpos: [5]; default: 0;
|
||||
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
|
||||
* deterministic derivation algorithm.
|
||||
*/
|
||||
|
||||
uint32_t ecdsa_deterministic_k:1;
|
||||
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_conf_reg_t;
|
||||
|
||||
/** Type of start register
|
||||
* ECDSA start register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
|
||||
* after configuration.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** load_done : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t load_done:1;
|
||||
/** get_done : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t get_done:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_start_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock and reset registers */
|
||||
/** Type of clk register
|
||||
* ECDSA clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_gate_force_on:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_raw:1;
|
||||
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_raw:1;
|
||||
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_raw:1;
|
||||
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_raw:1;
|
||||
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_st:1;
|
||||
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_st:1;
|
||||
/** post_done_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_st:1;
|
||||
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_st:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_ena:1;
|
||||
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_ena:1;
|
||||
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_ena:1;
|
||||
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_ena:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_clr:1;
|
||||
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_clr:1;
|
||||
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_clr:1;
|
||||
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_clr:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of state register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy : RO; bitpos: [1:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
uint32_t busy:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of result register
|
||||
* ECDSA result register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** operation_result : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
uint32_t operation_result:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_result_reg_t;
|
||||
|
||||
|
||||
/** Group: SHA register */
|
||||
/** Type of sha_mode register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
*/
|
||||
uint32_t sha_mode:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_mode_reg_t;
|
||||
|
||||
/** Type of sha_start register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_start:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_start_reg_t;
|
||||
|
||||
/** Type of sha_continue register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_continue : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_continue:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_continue_reg_t;
|
||||
|
||||
/** Type of sha_busy register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_busy : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
uint32_t sha_busy:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37761312;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
uint32_t ecdsa_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_date_reg_t;
|
||||
|
||||
/**
|
||||
* ECDSA message register
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t message[8];
|
||||
} ecdsa_message_reg_t;
|
||||
|
||||
/**
|
||||
* ECDSA memory register
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t r[8];
|
||||
volatile uint32_t s[8];
|
||||
volatile uint32_t z[8];
|
||||
volatile uint32_t qax[8];
|
||||
volatile uint32_t qay[8];
|
||||
} ecdsa_mem_reg_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile ecdsa_conf_reg_t conf;
|
||||
volatile ecdsa_clk_reg_t clk;
|
||||
volatile ecdsa_int_raw_reg_t int_raw;
|
||||
volatile ecdsa_int_st_reg_t int_st;
|
||||
volatile ecdsa_int_ena_reg_t int_ena;
|
||||
volatile ecdsa_int_clr_reg_t int_clr;
|
||||
volatile ecdsa_start_reg_t start;
|
||||
volatile ecdsa_state_reg_t state;
|
||||
volatile ecdsa_result_reg_t result;
|
||||
uint32_t reserved_028[53];
|
||||
volatile ecdsa_date_reg_t date;
|
||||
uint32_t reserved_100[64];
|
||||
volatile ecdsa_sha_mode_reg_t sha_mode;
|
||||
uint32_t reserved_204[3];
|
||||
volatile ecdsa_sha_start_reg_t sha_start;
|
||||
volatile ecdsa_sha_continue_reg_t sha_continue;
|
||||
volatile ecdsa_sha_busy_reg_t sha_busy;
|
||||
uint32_t reserved_21c[25];
|
||||
volatile ecdsa_message_reg_t message;
|
||||
uint32_t reserved_2a0[40];
|
||||
volatile ecdsa_mem_reg_t mem;
|
||||
uint32_t reserved_300[432];
|
||||
} ecdsa_dev_rev_1_2_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(ecdsa_dev_rev_1_2_t) == 0xaa0, "Invalid size of ecdsa_dev_rev_1_2_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -10,300 +10,43 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Data Memory */
|
||||
#include "soc/ecdsa_rev_0_0_struct.h"
|
||||
#include "soc/ecdsa_rev_1_2_struct.h"
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* ECDSA configure register
|
||||
/**
|
||||
* @brief Compatible ecdsa struct wrapper
|
||||
*
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** work_mode : R/W; bitpos: [0]; default: 0;
|
||||
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
|
||||
* Generate Mode.
|
||||
*/
|
||||
uint32_t work_mode:1;
|
||||
/** ecc_curve : R/W; bitpos: [1]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
uint32_t ecc_curve:1;
|
||||
/** software_set_k : R/W; bitpos: [2]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
uint32_t software_set_k:1;
|
||||
/** software_set_z : R/W; bitpos: [3]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
uint32_t software_set_z:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_conf_reg_t;
|
||||
|
||||
/** Type of start register
|
||||
* ECDSA start register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
|
||||
* after configuration.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** load_done : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t load_done:1;
|
||||
/** get_done : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t get_done:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_start_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock and reset registers */
|
||||
/** Type of clk register
|
||||
* ECDSA clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_gate_force_on:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_raw:1;
|
||||
/** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_st:1;
|
||||
/** sha_release_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_ena:1;
|
||||
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_clr:1;
|
||||
/** sha_release_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of state register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy : RO; bitpos: [1:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
uint32_t busy:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of result register
|
||||
* ECDSA result register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** operation_result : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
uint32_t operation_result:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_result_reg_t;
|
||||
|
||||
|
||||
/** Group: SHA register */
|
||||
/** Type of sha_mode register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
*/
|
||||
uint32_t sha_mode:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_mode_reg_t;
|
||||
|
||||
/** Type of sha_start register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_start:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_start_reg_t;
|
||||
|
||||
/** Type of sha_continue register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_continue : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_continue:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_continue_reg_t;
|
||||
|
||||
/** Type of sha_busy register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_busy : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
uint32_t sha_busy:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 35684752;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile ecdsa_conf_reg_t conf;
|
||||
volatile ecdsa_clk_reg_t clk;
|
||||
volatile ecdsa_int_raw_reg_t int_raw;
|
||||
volatile ecdsa_int_st_reg_t int_st;
|
||||
volatile ecdsa_int_ena_reg_t int_ena;
|
||||
volatile ecdsa_int_clr_reg_t int_clr;
|
||||
volatile ecdsa_start_reg_t start;
|
||||
volatile ecdsa_state_reg_t state;
|
||||
volatile ecdsa_result_reg_t result;
|
||||
uint32_t reserved_028[53];
|
||||
volatile ecdsa_date_reg_t date;
|
||||
uint32_t reserved_100[64];
|
||||
volatile ecdsa_sha_mode_reg_t sha_mode;
|
||||
uint32_t reserved_204[3];
|
||||
volatile ecdsa_sha_start_reg_t sha_start;
|
||||
volatile ecdsa_sha_continue_reg_t sha_continue;
|
||||
volatile ecdsa_sha_busy_reg_t sha_busy;
|
||||
uint32_t reserved_21c[25];
|
||||
volatile uint32_t message[8];
|
||||
uint32_t reserved_2a0[472];
|
||||
volatile uint32_t r[8];
|
||||
volatile uint32_t s[8];
|
||||
volatile uint32_t z[8];
|
||||
volatile uint32_t qax[8];
|
||||
volatile uint32_t qay[8];
|
||||
volatile ecdsa_dev_rev_0_0_t rev_0_0;
|
||||
volatile ecdsa_dev_rev_1_2_t rev_1_2;
|
||||
} ecdsa_dev_t;
|
||||
|
||||
extern ecdsa_dev_t ECDSA;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
|
||||
#endif
|
||||
/* Note: For ECDSA register on ESP32-H2, you need to use the ECDSA struct through
|
||||
* ECDSA_REG_GET and ECDSA_REG_SET to access the ECDSA peripheral register and its fields respectively.
|
||||
* For e.g., ECDSA_REG_SET(ECDSA.clk.clk_gate_force_on, enable) is used to set the register value.
|
||||
* The ECDSA struct should not be referenced directly.
|
||||
*/
|
||||
|
||||
/** The ECDSA date version of chip revision 1.2*/
|
||||
#define ECDSA_REV1_2_DATE (0x2403120)
|
||||
|
||||
/**
|
||||
* @brief Set the register value compatibly
|
||||
* @param reg The register to set
|
||||
* @param val The value to set
|
||||
*/
|
||||
#define ECDSA_REG_SET(reg, val) (ECDSA.rev_1_2.date.ecdsa_date >= ECDSA_REV1_2_DATE ? \
|
||||
(ECDSA.rev_1_2.reg = (val)) : (ECDSA.rev_0_0.reg = (val)))
|
||||
|
||||
/**
|
||||
* @brief Get the register value compatibly
|
||||
* @param reg The register to get
|
||||
*/
|
||||
#define ECDSA_REG_GET(reg) (ECDSA.rev_1_2.date.ecdsa_date >= ECDSA_REV1_2_DATE ? \
|
||||
(ECDSA.rev_1_2.reg) : (ECDSA.rev_0_0.reg))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -502,9 +502,11 @@
|
||||
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
|
||||
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
|
||||
|
||||
/*--------------------------- ECC CAPS ---------------------------------------*/
|
||||
#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
|
||||
|
||||
/*------------------------- ECDSA CAPS -------------------------*/
|
||||
#define SOC_ECDSA_USES_MPI (1)
|
||||
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-H2 has 2 UARTs
|
||||
#define SOC_UART_NUM (2)
|
||||
|
||||
@@ -40,7 +40,7 @@ PROVIDE ( RSA = 0x6008A000 );
|
||||
PROVIDE ( ECC = 0x6008B000 );
|
||||
PROVIDE ( DS = 0x6008C000 );
|
||||
PROVIDE ( HMAC = 0x6008D000 );
|
||||
|
||||
PROVIDE ( ECDSA = 0x6008E000 );
|
||||
PROVIDE ( IO_MUX = 0x60090000 );
|
||||
PROVIDE ( GPIO = 0x60091000 );
|
||||
PROVIDE ( GPIO_EXT = 0x60091f00 );
|
||||
|
||||
Reference in New Issue
Block a user