Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep

Browse Source
This commit is contained in:
wuzhenghui
2025-11-11 21:58:51 +08:00
parent 5e03aa8878
commit 5eff18eec2
15 changed files with 207 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/ld/esp32p4/memory.ld.in
+12 -3
View File
@@ -32,6 +32,12 @@
#define SRAM_HIGH_END SRAM_HIGH_START + SRAM_HIGH_SIZE
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
#define MSPI_WORKAROUND_SIZE CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
#else
#define MSPI_WORKAROUND_SIZE 0x0
#endif
#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 10)
#define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack
@@ -90,14 +96,17 @@ MEMORY
/* (See irom_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Used to store the deep sleep workaround code of P4 rev3.0. The reset vector will be set here before the chip enters sleep. */
rev3_mspi_workaround_seg(RWX) : org = 0x50108000, len = MSPI_WORKAROUND_SIZE
/**
* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
*/
#if CONFIG_ULP_COPROC_ENABLED
lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM,
lp_ram_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x8000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM - LP_ROM_DRAM_SIZE
#else
lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM
lp_ram_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM - MSPI_WORKAROUND_SIZE
#endif // CONFIG_ULP_COPROC_ENABLED
/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
@@ -108,7 +117,7 @@ MEMORY
The aim of this is to keep data that will not be moved around and have a fixed address.
This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data
*/
lp_reserved_seg(RW) : org = 0x50108000, len = RESERVE_RTC_MEM
lp_reserved_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE, len = RESERVE_RTC_MEM
/* PSRAM seg */
extern_ram_seg(RWX) : org = 0x48000000, len = IDROM_SEG_SIZE
components/esp_system/ld/esp32p4/sections.rev3.ld.in
+9
View File
@@ -115,6 +115,15 @@ SECTIONS
ALIGNED_SYMBOL(4, _rtc_force_slow_end)
} > lp_ram_seg
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
.rtc.p4_rev3_mspi_workaround :
{
ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_start)
KEEP (*(.p4_rev3_mspi_workaround.rtc_text .p4_rev3_mspi_workaround.rtc_text.*))
ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_end)
} > rev3_mspi_workaround_seg
#endif
/**
* This section holds RTC data that should have fixed addresses.
* The data are not initialized at power-up and are retained during deep