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refactor(hal): Created esp_hal_security for security code

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This commit is contained in:
Aditya Patwardhan
2026-01-21 09:59:46 +05:30
parent 469ead652b
commit 5ee7af3afd
220 changed files with 4098 additions and 3766 deletions
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components/esp_hal_security/esp32c5/include/esp_hal_security/aes_ll.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include "soc/aes_reg.h"
#include "soc/pcr_struct.h"
#include "esp_hal_security/aes_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief State of AES accelerator, busy, idle or done
*
*/
typedef enum {
ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
ESP_AES_STATE_BUSY, /* Transform in progress */
ESP_AES_STATE_DONE, /* Transform completed */
} esp_aes_state_t;
/**
* @brief Enable the bus clock for AES peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void aes_ll_enable_bus_clock(bool enable)
{
PCR.aes_conf.aes_clk_en = enable;
}
/**
* @brief Reset the AES peripheral module
*/
static inline void aes_ll_reset_register(void)
{
PCR.aes_conf.aes_rst_en = 1;
PCR.aes_conf.aes_rst_en = 0;
// Clear reset on digital signature also, otherwise AES is held in reset
PCR.ds_conf.ds_rst_en = 0;
}
/**
* @brief Write the encryption/decryption key to hardware
*
* @param key Key to be written to the AES hardware
* @param key_word_len Number of words in the key
*
* @return Number of bytes written to hardware, used for fault injection check
*/
static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len)
{
/* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
volatile uint8_t key_in_hardware = 0;
/* Memcpy to avoid potential unaligned access */
uint32_t key_word;
for (int i = 0; i < key_word_len; i++) {
memcpy(&key_word, key + 4 * i, 4);
REG_WRITE(AES_KEY_0_REG + i * 4, key_word);
key_in_hardware += 4;
}
return key_in_hardware;
}
/**
* @brief Sets the mode
*
* @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0
* @param key_bytes Number of bytes in the key
*/
static inline void aes_ll_set_mode(int mode, uint8_t key_bytes)
{
const uint32_t MODE_DECRYPT_BIT = 4;
unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
/* See TRM for the mapping between keylength and mode bit */
REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
}
/**
* @brief Writes message block to AES hardware
*
* @param input Block to be written
*/
static inline void aes_ll_write_block(const void *input)
{
uint32_t input_word;
for (int i = 0; i < AES_BLOCK_WORDS; i++) {
memcpy(&input_word, (uint8_t*)input + 4 * i, 4);
REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word);
}
}
/**
* @brief Read the AES block
*
* @param output the output of the transform, length = AES_BLOCK_BYTES
*/
static inline void aes_ll_read_block(void *output)
{
uint32_t output_word;
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
/* Memcpy to avoid potential unaligned access */
memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
}
}
/**
* @brief Starts block transform
*
*/
static inline void aes_ll_start_transform(void)
{
REG_WRITE(AES_TRIGGER_REG, 1);
}
/**
* @brief Read state of AES accelerator
*
* @return esp_aes_state_t
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}
/**
* @brief Set mode of operation
*
* @note Only used for DMA transforms
*
* @param mode Mode of operation to set (e.g., ECB, CBC, CTR, etc.)
*/
static inline void aes_ll_set_block_mode(esp_aes_mode_t mode)
{
REG_WRITE(AES_BLOCK_MODE_REG, mode);
}
/**
* @brief Set AES-CTR counter to INC32
*
* @note Only affects AES-CTR mode
*
*/
static inline void aes_ll_set_inc(void)
{
REG_WRITE(AES_INC_SEL_REG, 0);
}
/**
* @brief Release the DMA
*
*/
static inline void aes_ll_dma_exit(void)
{
REG_WRITE(AES_DMA_EXIT_REG, 0);
}
/**
* @brief Sets the number of blocks to be transformed
*
* @note Only used for DMA transforms
*
* @param num_blocks Number of blocks to transform
*/
static inline void aes_ll_set_num_blocks(size_t num_blocks)
{
REG_WRITE(AES_BLOCK_NUM_REG, num_blocks);
}
/*
* Write IV to hardware iv registers
*/
static inline void aes_ll_set_iv(const uint8_t *iv)
{
uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
uint32_t iv_word;
for (int i = 0; i < IV_WORDS; i++) {
/* Memcpy to avoid potential unaligned access */
memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
REG_WRITE(&reg_addr_buf[i], iv_word);
}
}
/*
* Read IV from hardware iv registers
*/
static inline void aes_ll_read_iv(uint8_t *iv)
{
uint32_t iv_word;
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < IV_WORDS; i++) {
iv_word = REG_READ(AES_IV_MEM + (i * REG_WIDTH));
/* Memcpy to avoid potential unaligned access */
memcpy(iv + i * 4, &iv_word, sizeof(iv_word));
}
}
/**
* @brief Enable or disable DMA mode
*
* @param enable true to enable, false to disable.
*/
static inline void aes_ll_dma_enable(bool enable)
{
REG_WRITE(AES_DMA_ENABLE_REG, enable);
}
/**
* @brief Enable or disable transform completed interrupt
*
* @param enable true to enable, false to disable.
*/
static inline void aes_ll_interrupt_enable(bool enable)
{
REG_WRITE(AES_INT_ENA_REG, enable);
}
/**
* @brief Clears the interrupt
*
*/
static inline void aes_ll_interrupt_clear(void)
{
REG_WRITE(AES_INT_CLEAR_REG, 1);
}
/**
* @brief Enable the pseudo-round function during AES operations
*
* @param enable true to enable, false to disable
* @param base basic number of pseudo rounds, zero if disable
* @param increment increment number of pseudo rounds, zero if disable
* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
*/
static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
{
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable);
if (enable) {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt);
} else {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0);
}
}
/**
* @brief Check if the pseudo round function is supported
*/
static inline bool aes_ll_is_pseudo_rounds_function_supported(void)
{
return true;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/apm_ll.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/apm_defs.h"
#include "soc/tee_reg.h"
#include "soc/lp_tee_reg.h"
#include "soc/hp_apm_reg.h"
#include "soc/hp_apm_struct.h"
#include "soc/lp_apm0_reg.h"
#include "soc/lp_apm0_struct.h"
#include "soc/lp_apm_reg.h"
#include "soc/lp_apm_struct.h"
#include "soc/cpu_apm_reg.h"
#include "soc/cpu_apm_struct.h"
#include "soc/pcr_reg.h"
#include "soc/interrupts.h"
#include "esp_hal_security/apm_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Helper macros for getting APM ctrl region pms attributes field mask */
#define APM_REGION_PMS_SHIFT(mode) (4U * ((mode) - 1))
#define APM_REGION_PMS_MASK(mode) (0x07U << APM_REGION_PMS_SHIFT(mode))
#define APM_REGION_PMS_FIELD(mode, pms) ((pms) << APM_REGION_PMS_SHIFT(mode))
/* Helper macros for getting TEE ctrl periph pms attributes field mask */
#define APM_PERI_PMS_MASK(mode) ((1U << (mode)) | (1U << ((mode) ^ 4U)))
#define APM_PERI_PMS_R_FIELD(mode, pms) ((((pms) & APM_PERM_R) >> 2U) << (mode))
#define APM_PERI_PMS_W_FIELD(mode, pms) ((((pms) & APM_PERM_W) >> 1U) << ((mode) ^ 4U))
/**
* @brief Set security mode for a specific master in HP-TEE
*
* @param id Master ID
* @param mode Security mode to set
*/
static inline void apm_ll_hp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode)
{
REG_WRITE(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, mode);
}
/**
* @brief Lock master security mode for HP-TEE
*
* @param id Master ID
*/
static inline void apm_ll_hp_tee_lock_master_sec_mode(apm_master_id_t id)
{
REG_SET_BIT(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, APM_TEE_MODE_LOCK_BIT);
}
/**
* @brief Set access permissions for a specific peripheral in HP-TEE
*
* @param periph Peripheral ID
* @param mode Security mode
* @param pms Access permissions
*/
static inline void apm_ll_hp_tee_set_peri_access(apm_tee_hp_periph_t periph, apm_security_mode_t mode, apm_perm_t pms)
{
uint32_t reg = TEE_UART0_CTRL_REG + APM_TEE_PERI_CTRL_OFFSET * periph;
uint32_t val = REG_READ(reg);
val &= ~APM_PERI_PMS_MASK(mode);
val |= APM_PERI_PMS_R_FIELD(mode, pms);
val |= APM_PERI_PMS_W_FIELD(mode, pms);
REG_WRITE(reg, val);
}
/**
* @brief Enable or disable error response from HP-TEE when access is blocked.
*
* @param enable true to enable error response, false to disable.
*/
static inline void apm_ll_hp_tee_enable_bus_err_resp(bool enable)
{
if (enable) {
REG_SET_BIT(TEE_BUS_ERR_CONF_REG, TEE_BUS_ERR_RESP_EN);
} else {
REG_CLR_BIT(TEE_BUS_ERR_CONF_REG, TEE_BUS_ERR_RESP_EN);
}
}
/**
* @brief Enable/disable clock gating for HP-TEE
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_tee_enable_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
} else {
REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
}
}
/**
* @brief Set security mode for a specific master in LP-TEE
*
* @param id Master ID (unused)
* @param mode Security mode to set
*/
static inline void apm_ll_lp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode)
{
(void)id;
REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, mode);
}
/**
* @brief Lock master security mode for LP-TEE
*
* @param id Master ID (unused)
*/
static inline void apm_ll_lp_tee_lock_master_sec_mode(apm_master_id_t id)
{
(void)id;
REG_SET_BIT(LP_TEE_M0_MODE_CTRL_REG, LP_TEE_M0_LOCK);
}
/**
* @brief Set access permissions for a specific peripheral in LP-TEE
*
* @param periph Peripheral ID
* @param mode Security mode
* @param pms Access permissions
*/
static inline void apm_ll_lp_tee_set_peri_access(apm_tee_lp_periph_t periph, apm_security_mode_t mode, apm_perm_t pms)
{
uint32_t reg = LP_TEE_EFUSE_CTRL_REG + APM_TEE_PERI_CTRL_OFFSET * periph;
uint32_t val = REG_READ(reg);
val &= ~APM_PERI_PMS_MASK(mode);
val |= APM_PERI_PMS_R_FIELD(mode, pms);
val |= APM_PERI_PMS_W_FIELD(mode, pms);
REG_WRITE(reg, val);
}
/**
* @brief Enable or disable error response from LP-TEE when access is blocked.
*
* @param enable true to enable error response, false to disable.
*/
static inline void apm_ll_lp_tee_enable_bus_err_resp(bool enable)
{
if (enable) {
REG_SET_BIT(LP_TEE_BUS_ERR_CONF_REG, LP_TEE_BUS_ERR_RESP_EN);
} else {
REG_CLR_BIT(LP_TEE_BUS_ERR_CONF_REG, LP_TEE_BUS_ERR_RESP_EN);
}
}
/**
* @brief Enable/disable clock gating for LP-TEE
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_tee_enable_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN);
} else {
REG_SET_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN);
}
}
/**
* @brief Enable/disable forced HP memory access for LP-TEE
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_tee_enable_force_hp_mem_access(bool enable)
{
if (enable) {
REG_SET_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN);
} else {
REG_CLR_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN);
}
}
/**
* @brief Enable/disable controller filter for specific path in HP-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(path));
} else {
REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(path));
}
}
/**
* @brief Enable/disable all controller filters in HP-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_apm_enable_ctrl_filter_all(bool enable)
{
REG_WRITE(HP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
}
/**
* @brief Enable/disable region filter in HP-APM
*
* @param regn_num Region number
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_apm_enable_region_filter(uint32_t regn_num, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
} else {
REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
}
}
/**
* @brief Set region start address in HP-APM
*
* @param regn_num Region number
* @param addr Start address
*/
static inline void apm_ll_hp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(HP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set region end address in HP-APM
*
* @param regn_num Region number
* @param addr End address
*/
static inline void apm_ll_hp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(HP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set security mode region attributes in HP-APM
*
* @param regn_num Region number
* @param mode Security mode
* @param regn_pms Region PMS attributes
*/
static inline void apm_ll_hp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
{
uint32_t reg = HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
uint32_t val = REG_READ(reg);
val &= ~APM_REGION_PMS_MASK(mode);
val |= APM_REGION_PMS_FIELD(mode, regn_pms);
REG_WRITE(reg, val);
}
/**
* @brief Lock security mode region attributes in HP-APM
*
* @param regn_num Region number
*/
static inline void apm_ll_hp_apm_lock_sec_mode_region_attr(uint32_t regn_num)
{
REG_SET_BIT(HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
}
/**
* @brief Get exception data (regn, master, security mode) from HP-APM
*
* @param path Access path
* @return Exception data
*/
static inline uint32_t apm_ll_hp_apm_get_excp_data(apm_ctrl_access_path_t path)
{
return REG_READ(HP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception status from HP-APM
*
* @param path Access path
* @return Exception type
*/
static inline uint32_t apm_ll_hp_apm_get_excp_type(apm_ctrl_access_path_t path)
{
return REG_READ(HP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception address from HP-APM
*
* @param path Access path
* @return Exception address
*/
static inline uint32_t apm_ll_hp_apm_get_excp_addr(apm_ctrl_access_path_t path)
{
return REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception information from HP-APM
*
* @param path Access path
* @param info Pointer to store exception information
*/
static inline void apm_ll_hp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
{
hp_apm_m0_exception_info0_reg_t reg;
reg.val = apm_ll_hp_apm_get_excp_data(path);
info->regn = reg.m0_exception_region;
info->mode = reg.m0_exception_mode;
info->id = reg.m0_exception_id;
info->type = apm_ll_hp_apm_get_excp_type(path);
info->addr = apm_ll_hp_apm_get_excp_addr(path);
}
/**
* @brief Clear controller exception status in HP-APM
*
* @param path Access path
*/
static inline void apm_ll_hp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
{
REG_SET_BIT(HP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT);
}
/**
* @brief Enable/disable controller interrupt in HP-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_INT_EN_REG, BIT(path));
} else {
REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(path));
}
}
/**
* @brief Get controller interrupt source number from HP-APM
*
* @param path Access path
* @return Interrupt source number
*/
static inline int apm_ll_hp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
{
return ETS_HP_APM_M0_INTR_SOURCE + path;
}
/**
* @brief Enable/disable controller clock gating in HP-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_hp_apm_enable_ctrl_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
} else {
REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
}
}
/**
* @brief Enable/disable controller filter for specific path in LP-APM0
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm0_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path));
} else {
REG_CLR_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path));
}
}
/**
* @brief Enable/disable all controller filters in LP-APM0
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm0_enable_ctrl_filter_all(bool enable)
{
REG_WRITE(LP_APM0_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
}
/**
* @brief Enable/disable region filter in LP-APM0
*
* @param regn_num Region number
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm0_enable_region_filter(uint32_t regn_num, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num));
} else {
REG_CLR_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num));
}
}
/**
* @brief Set region start address in LP-APM0
*
* @param regn_num Region number
* @param addr Start address
*/
static inline void apm_ll_lp_apm0_set_region_start_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(LP_APM0_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set region end address in LP-APM0
*
* @param regn_num Region number
* @param addr End address
*/
static inline void apm_ll_lp_apm0_set_region_end_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(LP_APM0_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set security mode region attributes in LP-APM0
*
* @param regn_num Region number
* @param mode Security mode
* @param regn_pms Region PMS attributes
*/
static inline void apm_ll_lp_apm0_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
{
uint32_t reg = LP_APM0_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
uint32_t val = REG_READ(reg);
val &= ~APM_REGION_PMS_MASK(mode);
val |= APM_REGION_PMS_FIELD(mode, regn_pms);
REG_WRITE(reg, val);
}
/**
* @brief Lock security mode region attributes in LP-APM0
*
* @param regn_num Region number
*/
static inline void apm_ll_lp_apm0_lock_sec_mode_region_attr(uint32_t regn_num)
{
REG_SET_BIT(LP_APM0_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
}
/**
* @brief Get exception data (regn, master, security mode) from LP-APM0
*
* @param path Access path
* @return Exception data
*/
static inline uint32_t apm_ll_lp_apm0_get_excp_data(apm_ctrl_access_path_t path)
{
(void)path;
return REG_READ(LP_APM0_M0_EXCEPTION_INFO0_REG);
}
/**
* @brief Get exception status from LP-APM0
*
* @param path Access path
* @return Exception type
*/
static inline uint32_t apm_ll_lp_apm0_get_excp_type(apm_ctrl_access_path_t path)
{
(void)path;
return REG_READ(LP_APM0_M0_STATUS_REG);
}
/**
* @brief Get exception address from LP-APM0
*
* @param path Access path
* @return Exception address
*/
static inline uint32_t apm_ll_lp_apm0_get_excp_addr(apm_ctrl_access_path_t path)
{
(void)path;
return REG_READ(LP_APM0_M0_EXCEPTION_INFO1_REG);
}
/**
* @brief Get exception information from LP-APM0
*
* @param path Access path
* @param info Pointer to store exception information
*/
static inline void apm_ll_lp_apm0_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
{
lp_apm0_m0_exception_info0_reg_t reg;
reg.val = apm_ll_lp_apm0_get_excp_data(path);
info->regn = reg.m0_exception_region;
info->mode = reg.m0_exception_mode;
info->id = reg.m0_exception_id;
info->type = apm_ll_lp_apm0_get_excp_type(path);
info->addr = apm_ll_lp_apm0_get_excp_addr(path);
}
/**
* @brief Clear controller exception status in LP-APM0
*
* @param path Access path
*/
static inline void apm_ll_lp_apm0_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
{
(void)path;
REG_SET_BIT(LP_APM0_M0_STATUS_CLR_REG, APM_EXCP_STATUS_CLR_BIT);
}
/**
* @brief Enable/disable controller interrupt in LP-APM0
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm0_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM0_INT_EN_REG, BIT(path));
} else {
REG_CLR_BIT(LP_APM0_INT_EN_REG, BIT(path));
}
}
/**
* @brief Get controller interrupt source number from LP-APM0
*
* @param path Access path
* @return Interrupt source number
*/
static inline int apm_ll_lp_apm0_get_ctrl_intr_src(apm_ctrl_access_path_t path)
{
(void)path;
return ETS_LP_APM0_INTR_SOURCE;
}
/**
* @brief Enable/disable controller clock gating in LP-APM0
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm0_enable_ctrl_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN);
} else {
REG_SET_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN);
}
}
/**
* @brief Enable/disable controller filter for specific path in LP-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM_FUNC_CTRL_REG, BIT(path));
} else {
REG_CLR_BIT(LP_APM_FUNC_CTRL_REG, BIT(path));
}
}
/**
* @brief Enable/disable all controller filters in LP-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm_enable_ctrl_filter_all(bool enable)
{
REG_WRITE(LP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
}
/**
* @brief Enable/disable region filter in LP-APM
*
* @param regn_num Region number
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm_enable_region_filter(uint32_t regn_num, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
} else {
REG_CLR_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
}
}
/**
* @brief Set region start address in LP-APM
*
* @param regn_num Region number
* @param addr Start address
*/
static inline void apm_ll_lp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(LP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set region end address in LP-APM
*
* @param regn_num Region number
* @param addr End address
*/
static inline void apm_ll_lp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(LP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set security mode region attributes in LP-APM
*
* @param regn_num Region number
* @param mode Security mode
* @param regn_pms Region PMS attributes
*/
static inline void apm_ll_lp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
{
uint32_t reg = LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
uint32_t val = REG_READ(reg);
val &= ~APM_REGION_PMS_MASK(mode);
val |= APM_REGION_PMS_FIELD(mode, regn_pms);
REG_WRITE(reg, val);
}
/**
* @brief Lock security mode region attributes in LP-APM
*
* @param regn_num Region number
*/
static inline void apm_ll_lp_apm_lock_sec_mode_region_attr(uint32_t regn_num)
{
REG_SET_BIT(LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
}
/**
* @brief Get exception data (regn, master, security mode) from LP-APM
*
* @param path Access path
* @return Exception data
*/
static inline uint32_t apm_ll_lp_apm_get_excp_data(apm_ctrl_access_path_t path)
{
return REG_READ(LP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception status from LP-APM
*
* @param path Access path
* @return Exception type
*/
static inline uint32_t apm_ll_lp_apm_get_excp_type(apm_ctrl_access_path_t path)
{
return REG_READ(LP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception address from LP-APM
*
* @param path Access path
* @return Exception address
*/
static inline uint32_t apm_ll_lp_apm_get_excp_addr(apm_ctrl_access_path_t path)
{
return REG_READ(LP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception information from LP-APM
*
* @param path Access path
* @param info Pointer to store exception information
*/
static inline void apm_ll_lp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
{
lp_apm_m0_exception_info0_reg_t reg;
reg.val = apm_ll_lp_apm_get_excp_data(path);
info->regn = reg.m0_exception_region;
info->mode = reg.m0_exception_mode;
info->id = reg.m0_exception_id;
info->type = apm_ll_lp_apm_get_excp_type(path);
info->addr = apm_ll_lp_apm_get_excp_addr(path);
}
/**
* @brief Clear controller exception status in LP-APM
*
* @param path Access path
*/
static inline void apm_ll_lp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
{
REG_SET_BIT(LP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT);
}
/**
* @brief Enable/disable controller interrupt in LP-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(LP_APM_INT_EN_REG, BIT(path));
} else {
REG_CLR_BIT(LP_APM_INT_EN_REG, BIT(path));
}
}
/**
* @brief Enable/disable controller clock gating in LP-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_lp_apm_enable_ctrl_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN);
} else {
REG_SET_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN);
}
}
/**
* @brief Get controller interrupt source number from LP-APM
*
* @param path Access path
* @return Interrupt source number
*/
static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
{
return ETS_LP_APM_M0_INTR_SOURCE + path;
}
/**
* @brief Enable/disable controller filter for specific path in CPU-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_cpu_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
} else {
REG_CLR_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
}
}
/**
* @brief Enable/disable all controller filters in CPU-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_cpu_apm_enable_ctrl_filter_all(bool enable)
{
REG_WRITE(CPU_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
}
/**
* @brief Enable/disable region filter in CPU-APM
*
* @param regn_num Region number
* @param enable True to enable, false to disable
*/
static inline void apm_ll_cpu_apm_enable_region_filter(uint32_t regn_num, bool enable)
{
if (enable) {
REG_SET_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
} else {
REG_CLR_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
}
}
/**
* @brief Set region start address in CPU-APM
*
* @param regn_num Region number
* @param addr Start address
*/
static inline void apm_ll_cpu_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(CPU_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set region end address in CPU-APM
*
* @param regn_num Region number
* @param addr End address
*/
static inline void apm_ll_cpu_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(CPU_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
}
/**
* @brief Set security mode region attributes in CPU-APM
*
* @param regn_num Region number
* @param mode Security mode
* @param regn_pms Region PMS attributes
*/
static inline void apm_ll_cpu_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
{
uint32_t reg = CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
uint32_t val = REG_READ(reg);
val &= ~APM_REGION_PMS_MASK(mode);
val |= APM_REGION_PMS_FIELD(mode, regn_pms);
REG_WRITE(reg, val);
}
/**
* @brief Lock security mode region attributes in CPU-APM
*
* @param regn_num Region number
*/
static inline void apm_ll_cpu_apm_lock_sec_mode_region_attr(uint32_t regn_num)
{
REG_SET_BIT(CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
}
/**
* @brief Get exception data (regn, master, security mode) from CPU-APM
*
* @param path Access path
* @return Exception data
*/
static inline uint32_t apm_ll_cpu_apm_get_excp_data(apm_ctrl_access_path_t path)
{
return REG_READ(CPU_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception status from CPU-APM
*
* @param path Access path
* @return Exception type
*/
static inline uint32_t apm_ll_cpu_apm_get_excp_type(apm_ctrl_access_path_t path)
{
return REG_READ(CPU_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception address from CPU-APM
*
* @param path Access path
* @return Exception address
*/
static inline uint32_t apm_ll_cpu_apm_get_excp_addr(apm_ctrl_access_path_t path)
{
return REG_READ(CPU_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path);
}
/**
* @brief Get exception information from CPU-APM
*
* @param path Access path
* @param info Pointer to store exception information
*/
static inline void apm_ll_cpu_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
{
cpu_apm_m0_exception_info0_reg_t reg;
reg.val = apm_ll_cpu_apm_get_excp_data(path);
info->regn = reg.m0_exception_region;
info->mode = reg.m0_exception_mode;
info->id = reg.m0_exception_id;
info->type = apm_ll_cpu_apm_get_excp_type(path);
info->addr = apm_ll_cpu_apm_get_excp_addr(path);
}
/**
* @brief Clear controller exception status in CPU-APM
*
* @param path Access path
*/
static inline void apm_ll_cpu_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
{
REG_SET_BIT(CPU_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT);
}
/**
* @brief Enable/disable controller interrupt in CPU-APM
*
* @param path Access path
* @param enable True to enable, false to disable
*/
static inline void apm_ll_cpu_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
{
if (enable) {
REG_SET_BIT(CPU_APM_INT_EN_REG, BIT(path));
} else {
REG_CLR_BIT(CPU_APM_INT_EN_REG, BIT(path));
}
}
/**
* @brief Enable/disable controller clock gating in CPU-APM
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_cpu_apm_enable_ctrl_clk_gating(bool enable)
{
if (enable) {
REG_CLR_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
} else {
REG_SET_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
}
}
/**
* @brief Get controller interrupt source number from CPU-APM
*
* @param path Access path
* @return Interrupt source number
*/
static inline int apm_ll_cpu_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
{
return ETS_CPU_APM_M0_INTR_SOURCE + path;
}
/**
* @brief Enable/disable APM reset event bypass
*
* @param enable True to enable, false to disable
*/
static inline void apm_ll_enable_reset_event_bypass(bool enable)
{
if (enable) {
REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
} else {
REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
}
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/ds_ll.h
+202
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use it in application code.
******************************************************************************/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "soc/hwcrypto_reg.h"
#include "soc/soc_caps.h"
#include "soc/pcr_struct.h"
#include "esp_hal_security/ds_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for Digital Signature peripheral module
*
* @param true to enable the module, false to disable the module
*/
static inline void ds_ll_enable_bus_clock(bool enable)
{
PCR.ds_conf.ds_clk_en = enable;
}
/**
* @brief Reset the Digital Signature peripheral module
*/
static inline void ds_ll_reset_register(void)
{
PCR.ds_conf.ds_rst_en = 1;
PCR.ds_conf.ds_rst_en = 0;
}
static inline void ds_ll_start(void)
{
REG_WRITE(DS_SET_START_REG, 1);
}
/**
* @brief Wait until DS peripheral has finished any outstanding operation.
*/
static inline bool ds_ll_busy(void)
{
return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false;
}
/**
* @brief Busy wait until the hardware is ready.
*/
static inline void ds_ll_wait_busy(void)
{
while (ds_ll_busy());
}
/**
* @brief In case of a key error, check what caused it.
*/
static inline ds_key_check_t ds_ll_key_error_source(void)
{
uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG);
if (key_error == 0) {
return DS_NO_KEY_INPUT;
} else {
return DS_OTHER_WRONG;
}
}
/**
* @brief Set the DS key source.
*/
static inline void ds_ll_set_key_source(ds_key_source_t key_source)
{
REG_WRITE(DS_KEY_SOURCE_REG, key_source);
}
/**
* @brief Write the initialization vector to the corresponding register field.
*/
static inline void ds_ll_configure_iv(const uint32_t *iv)
{
for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
}
}
/**
* @brief Write the message which should be signed.
*
* @param msg Pointer to the message.
* @param size Length of msg in bytes. It is the RSA signature length in bytes.
*/
static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
{
memcpy((uint8_t*) DS_X_MEM, msg, size);
// Fence ensures all memory operations are completed before proceeding further
asm volatile("fence");
}
/**
* @brief Write the encrypted private key parameters.
*/
static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_params)
{
/* Note: as the internal peripheral still has RSA 4096 structure,
but C is encrypted based on the actual max RSA length (ETS_DS_MAX_BITS), need to fragment it
when copying to hardware...
(note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
*/
typedef struct {
uint32_t addr;
size_t len;
} frag_t;
const frag_t frags[] = {
{DS_Y_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_M_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
};
const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
const uint8_t *from = encrypted_key_params;
for (int i = 0; i < NUM_FRAGS; i++) {
memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
// Fence ensures all memory operations are completed before proceeding further
asm volatile("fence");
from += frags[i].len;
}
}
/**
* @brief Begin signing procedure.
*/
static inline void ds_ll_start_sign(void)
{
REG_WRITE(DS_SET_CONTINUE_REG, 1);
}
/**
* @brief check the calculated signature.
*
* @return
* - DS_SIGNATURE_OK if no issue is detected with the signature.
* - DS_SIGNATURE_PADDING_FAIL if the padding of the private key parameters is wrong.
* - DS_SIGNATURE_MD_FAIL if the message digest check failed. This means that the message digest calculated using
* the private key parameters fails, i.e., the integrity of the private key parameters is not protected.
* - DS_SIGNATURE_PADDING_AND_MD_FAIL if both padding and message digest check fail.
*/
static inline ds_signature_check_t ds_ll_check_signature(void)
{
uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
switch (result) {
case 0:
return DS_SIGNATURE_OK;
case 1:
return DS_SIGNATURE_MD_FAIL;
case 2:
return DS_SIGNATURE_PADDING_FAIL;
default:
return DS_SIGNATURE_PADDING_AND_MD_FAIL;
}
}
/**
* @brief Read the signature from the hardware.
*
* @param result The signature result.
* @param size Length of signature result in bytes. It is the RSA signature length in bytes.
*/
static inline void ds_ll_read_result(uint8_t *result, size_t size)
{
memcpy(result, (uint8_t*) DS_Z_MEM, size);
// Fence ensures all memory operations are completed before proceeding further
asm volatile("fence");
}
/**
* @brief Exit the signature operation.
*
* @note This does not deactivate the module. Corresponding clock/reset bits have to be triggered for deactivation.
*/
static inline void ds_ll_finish(void)
{
REG_WRITE(DS_SET_FINISH_REG, 1);
ds_ll_wait_busy();
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/ecc_ll.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include "hal/assert.h"
#include "esp_hal_security/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
ECC_PARAM_QX,
ECC_PARAM_QY,
ECC_PARAM_QZ,
} ecc_ll_param_t;
/**
* @brief Enable the bus clock for ECC peripheral module
*
* @param true to enable the module, false to disable the module
*/
static inline void ecc_ll_enable_bus_clock(bool enable)
{
PCR.ecc_conf.ecc_clk_en = enable;
}
/**
* @brief Reset the ECC peripheral module
*/
static inline void ecc_ll_reset_register(void)
{
PCR.ecc_conf.ecc_rst_en = 1;
PCR.ecc_conf.ecc_rst_en = 0;
// Clear reset on ECDSA, otherwise ECC is held in reset
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
static inline void ecc_ll_power_up(void)
{
/* Power up the ECC peripheral (default state is power-down) */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
}
static inline void ecc_ll_power_down(void)
{
/* Power down the ECC peripheral */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
}
static inline void ecc_ll_disable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
}
static inline void ecc_ll_clear_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
}
static inline void ecc_ll_set_mode(ecc_mode_t mode)
{
switch (mode) {
case ECC_MODE_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
break;
case ECC_MODE_VERIFY:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
break;
case ECC_MODE_VERIFY_THEN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
break;
case ECC_MODE_JACOBIAN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
break;
case ECC_MODE_POINT_ADD:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
break;
case ECC_MODE_JACOBIAN_POINT_VERIFY:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
break;
case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
break;
case ECC_MODE_MOD_ADD:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
break;
case ECC_MODE_MOD_SUB:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
break;
case ECC_MODE_MOD_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
break;
case ECC_MODE_INVERSE_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
break;
}
}
static inline void ecc_ll_set_curve(ecc_curve_t curve)
{
switch (curve) {
case ECC_CURVE_SECP192R1:
case ECC_CURVE_SECP256R1:
case ECC_CURVE_SECP384R1:
case ECC_CURVE_SM2:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
{
switch (base) {
case ECC_MOD_N:
REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
break;
case ECC_MOD_P:
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
static inline bool ecc_ll_is_p384_curve_operations_supported(void)
{
return true;
}
static inline void ecc_ll_enable_constant_time_point_mul(bool enable)
{
if (enable) {
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
} else {
REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
}
}
static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
{
uint32_t reg;
uint32_t word;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_MEM;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_MEM;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
case ECC_PARAM_QY:
reg = ECC_MULT_QY_MEM;
break;
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
for (int i = 0; i < len; i += 4) {
memcpy(&word, buf + i, 4);
REG_WRITE(reg + i, word);
}
}
static inline void ecc_ll_start_calc(void)
{
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
}
static inline int ecc_ll_is_calc_finished(void)
{
return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
}
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
}
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
{
uint32_t reg;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_MEM;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_MEM;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
case ECC_PARAM_QY:
reg = ECC_MULT_QY_MEM;
break;
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
memcpy(buf, (void *)reg, len);
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/ecdsa_ll.h
+459
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include "hal/assert.h"
#include "soc/ecdsa_reg.h"
#include "soc/pcr_struct.h"
#include "soc/efuse_periph.h"
#include "esp_hal_security/ecdsa_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Memory blocks of ECDSA parameters
*/
typedef enum {
ECDSA_PARAM_R,
ECDSA_PARAM_S,
ECDSA_PARAM_Z,
ECDSA_PARAM_QAX,
ECDSA_PARAM_QAY
} ecdsa_ll_param_t;
/**
* @brief Interrupt types in ECDSA
*/
typedef enum {
ECDSA_INT_CALC_DONE,
ECDSA_INT_SHA_RELEASE,
} ecdsa_ll_intr_type_t;
/**
* @brief Stages of ECDSA operation
*/
typedef enum {
ECDSA_STAGE_START_CALC,
ECDSA_STAGE_LOAD_DONE,
ECDSA_STAGE_GET_DONE
} ecdsa_ll_stage_t;
/**
* @brief States of ECDSA peripheral
*/
typedef enum {
ECDSA_STATE_IDLE,
ECDSA_STATE_LOAD,
ECDSA_STATE_GET,
ECDSA_STATE_BUSY
} ecdsa_ll_state_t;
/**
* @brief Types of SHA
*/
typedef enum {
ECDSA_SHA_224,
ECDSA_SHA_256
} ecdsa_ll_sha_type_t;
/**
* @brief Operation modes of SHA
*/
typedef enum {
ECDSA_MODE_SHA_START,
ECDSA_MODE_SHA_CONTINUE
} ecdsa_ll_sha_mode_t;
/**
* @brief Get the state of ECDSA peripheral
*
* @return State of ECDSA
*/
static inline uint32_t ecdsa_ll_get_state(void)
{
return REG_GET_FIELD(ECDSA_STATE_REG, ECDSA_BUSY);
}
/**
* @brief Enable the bus clock for ECDSA peripheral module
*
* @param true to enable the module, false to disable the module
*/
static inline void ecdsa_ll_enable_bus_clock(bool enable)
{
PCR.ecdsa_conf.ecdsa_clk_en = enable;
}
/**
* @brief Reset the ECDSA peripheral module
*/
static inline void ecdsa_ll_reset_register(void)
{
PCR.ecdsa_conf.ecdsa_rst_en = 1;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
while (ecdsa_ll_get_state() != ECDSA_STATE_IDLE) {
;
}
}
/**
* @brief Enable interrupt of a given type
*
* @param type Interrupt type
*/
static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
break;
default:
HAL_ASSERT(false && "Unsupported interrupt type");
break;
}
}
/**
* @brief Disable interrupt of a given type
*
* @param type Interrupt type
*/
static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
break;
default:
HAL_ASSERT(false && "Unsupported interrupt type");
break;
}
}
/**
* @brief Clear interrupt of a given type
*
* @param type Interrupt type
*/
static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
break;
default:
HAL_ASSERT(false && "Unsupported interrupt type");
break;
}
}
/**
* @brief Set working mode of ECDSA
*
* @param mode Mode of operation
*/
static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
{
switch (mode) {
case ECDSA_MODE_SIGN_VERIFY:
REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
break;
case ECDSA_MODE_SIGN_GEN:
REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
break;
case ECDSA_MODE_EXPORT_PUBKEY:
REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
break;
}
}
/**
* @brief Set curve for ECDSA operation
*
* @param curve ECDSA curve
*/
static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
{
switch (curve) {
case ECDSA_CURVE_SECP192R1:
case ECDSA_CURVE_SECP256R1:
case ECDSA_CURVE_SECP384R1:
case ECDSA_CURVE_SM2:
REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
/**
* @brief Set the source of `Z` (SHA message)
*
* @param mode Mode of SHA generation
*/
static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
{
switch (mode) {
case ECDSA_Z_USE_SHA_PERI:
REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
break;
case ECDSA_Z_USER_PROVIDED:
REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
break;
}
}
/**
* @brief Set the signature generation type of ECDSA operation
*
* @param type Type of the ECDSA signature
*/
static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
{
switch (type) {
case ECDSA_K_TYPE_TRNG:
REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
break;
#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
case ECDSA_K_TYPE_DETERMINISITIC:
REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
break;
#endif
default:
HAL_ASSERT(false && "Unsupported K type");
break;
}
}
/**
* @brief Set the stage of ECDSA operation
*
* @param stage Stage of operation
*/
static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
{
switch (stage) {
case ECDSA_STAGE_START_CALC:
REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
break;
case ECDSA_STAGE_LOAD_DONE:
REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
break;
case ECDSA_STAGE_GET_DONE:
REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
break;
default:
HAL_ASSERT(false && "Unsupported state");
break;
}
}
/**
* @brief Set the SHA type
*
* @param type Type of SHA
*/
static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
{
switch (type) {
case ECDSA_SHA_224:
REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
break;
case ECDSA_SHA_256:
REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
break;
default:
HAL_ASSERT(false && "Unsupported type");
break;
}
}
/**
* @brief Set the SHA operation mode
*
* @param mode Mode of SHA operation
*/
static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
{
switch (mode) {
case ECDSA_MODE_SHA_START:
REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
break;
case ECDSA_MODE_SHA_CONTINUE:
REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
break;
default:
HAL_ASSERT(false && "Unsupported type");
break;
}
}
/**
* @brief Check if SHA is busy
*
* @return - true, if SHA is busy
* - false, if SHA is IDLE
*/
static inline bool ecdsa_ll_sha_is_busy(void)
{
return REG_GET_BIT(ECDSA_SHA_BUSY_REG, ECDSA_SHA_BUSY);
}
/**
* @brief Write the ECDSA parameter
*
* @param param Parameter to be written
* @param buf Buffer containing data
* @param len Length of buffer
*/
static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *buf, uint16_t len)
{
uint32_t reg;
uint32_t word;
switch (param) {
case ECDSA_PARAM_R:
reg = ECDSA_R_MEM;
break;
case ECDSA_PARAM_S:
reg = ECDSA_S_MEM;
break;
case ECDSA_PARAM_Z:
reg = ECDSA_Z_MEM;
break;
case ECDSA_PARAM_QAX:
reg = ECDSA_QAX_MEM;
break;
case ECDSA_PARAM_QAY:
reg = ECDSA_QAY_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
for (int i = 0; i < len; i += 4) {
memcpy(&word, buf + i, 4);
REG_WRITE(reg + i, word);
}
}
/**
* @brief Read the ECDSA parameter
*
* @param param Parameter to be read
* @param buf Buffer where the data will be written
* @param len Length of buffer
*/
static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uint16_t len)
{
uint32_t reg;
switch (param) {
case ECDSA_PARAM_R:
reg = ECDSA_R_MEM;
break;
case ECDSA_PARAM_S:
reg = ECDSA_S_MEM;
break;
case ECDSA_PARAM_Z:
reg = ECDSA_Z_MEM;
break;
case ECDSA_PARAM_QAX:
reg = ECDSA_QAX_MEM;
break;
case ECDSA_PARAM_QAY:
reg = ECDSA_QAY_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
memcpy(buf, (void *)reg, len);
}
/**
* @brief Check if the ECDSA operation is successful
*
* @return - 1, if ECDSA operation succeeds
* - 0, otherwise
*/
static inline int ecdsa_ll_get_operation_result(void)
{
return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_OPERATION_RESULT);
}
/**
* @brief Check if the ECDSA deterministic mode is supported
*/
static inline bool ecdsa_ll_is_deterministic_mode_supported(void)
{
return true;
}
/**
* @brief Set the ECDSA key block in eFuse
*
* @param curve ECDSA curve type
* @param efuse_blk eFuse block number
*/
__attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
{
uint8_t efuse_blk_low = 0;
uint8_t efuse_blk_high = 0;
switch (curve) {
case ECDSA_CURVE_SECP192R1:
EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
break;
case ECDSA_CURVE_SECP256R1:
EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
break;
case ECDSA_CURVE_SECP384R1:
// ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
// where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
break;
default:
HAL_ASSERT(false && "Unsupported curve");
break;
}
}
/**
* @brief Check if the ECDSA peripheral is supported on this chip revision
* For ESP32-C5, ECDSA is always supported
*/
static inline bool ecdsa_ll_is_supported(void)
{
return true;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/hmac_ll.h
+212
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@@ -0,0 +1,212 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use it in application code.
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
#pragma once
#include <string.h>
#include <stdbool.h>
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/pcr_struct.h"
#include "esp_hal_security/hmac_types.h"
#define SHA256_BLOCK_SZ 64
#define SHA256_DIGEST_SZ 32
#define EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG 6
#define EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE 7
#define EFUSE_KEY_PURPOSE_HMAC_UP 8
#define EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL 5
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for HMAC peripheral module
*
* @param true to enable the module, false to disable the module
*/
static inline void hmac_ll_enable_bus_clock(bool enable)
{
PCR.hmac_conf.hmac_clk_en = enable;
}
/**
* @brief Reset the HMAC peripheral module
*/
static inline void hmac_ll_reset_register(void)
{
PCR.hmac_conf.hmac_rst_en = 1;
PCR.hmac_conf.hmac_rst_en = 0;
}
/**
* Makes the peripheral ready for use, after enabling it.
*/
static inline void hmac_ll_start(void)
{
REG_WRITE(HMAC_SET_START_REG, 1);
}
/**
* @brief Determine where the HMAC output should go.
*
* The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver
* the output directly to another peripheral instead, e.g. the Digital Signature peripheral.
*/
static inline void hmac_ll_config_output(hmac_hal_output_t config)
{
switch (config) {
case HMAC_OUTPUT_USER:
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
break;
case HMAC_OUTPUT_DS:
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE);
break;
case HMAC_OUTPUT_JTAG_ENABLE:
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG);
break;
case HMAC_OUTPUT_ALL:
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL);
break;
default:
; // do nothing, error will be indicated by hmac_hal_config_error()
}
}
/**
* @brief Selects which hardware key should be used.
*/
static inline void hmac_ll_config_hw_key_id(uint32_t key_id)
{
REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id);
}
/**
* @brief Apply and check configuration.
*
* Afterwards, the configuration can be checked for errors with hmac_hal_config_error().
*/
static inline void hmac_ll_config_finish(void)
{
REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1);
}
/**
*
* @brief Query HMAC error state after configuration actions.
*
* @return
* - 1 or greater on error
* - 0 on success
*/
static inline uint32_t hmac_ll_config_error(void)
{
return REG_READ(HMAC_QUERY_ERROR_REG);
}
/**
* Wait until the HAL is ready for the next interaction.
*/
static inline void hmac_ll_wait_idle(void)
{
uint32_t query;
do {
query = REG_READ(HMAC_QUERY_BUSY_REG);
} while (query != 0);
}
/**
* @brief Write a message block of 512 bits to the HMAC peripheral.
*/
static inline void hmac_ll_write_block_512(const uint32_t *block)
{
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < SHA256_BLOCK_SZ / REG_WIDTH; i++) {
REG_WRITE(HMAC_WR_MESSAGE_MEM + (i * REG_WIDTH), block[i]);
}
REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1);
}
/**
* @brief Read the 256 bit HMAC.
*/
static inline void hmac_ll_read_result_256(uint32_t *result)
{
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < SHA256_DIGEST_SZ / REG_WIDTH; i++) {
result[i] = REG_READ(HMAC_RD_RESULT_MEM + (i * REG_WIDTH));
}
}
/**
* @brief Clean the HMAC result provided to other hardware.
*/
static inline void hmac_ll_clean(void)
{
REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1);
REG_WRITE(HMAC_SET_INVALIDATE_JTAG_REG, 1);
}
/**
* @brief Signals that the following block will be the padded last block.
*/
static inline void hmac_ll_msg_padding(void)
{
REG_WRITE(HMAC_SET_MESSAGE_PAD_REG, 1);
}
/**
* @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware.
*
* Only applies if the message length is a multiple of 512 bits.
* See the chip TRM HMAC chapter for more details.
*/
static inline void hmac_ll_msg_end(void)
{
REG_WRITE(HMAC_SET_MESSAGE_END_REG, 1);
}
/**
* @brief The message including padding fits into one block, so no further action needs to be taken.
*
* This is called after the one-block-message has been written.
*/
static inline void hmac_ll_msg_one_block(void)
{
REG_WRITE(HMAC_ONE_BLOCK_REG, 1);
}
/**
* @brief Indicate that more blocks will be written after the last block.
*/
static inline void hmac_ll_msg_continue(void)
{
REG_WRITE(HMAC_SET_MESSAGE_ING_REG, 1);
}
/**
* @brief Clear the HMAC result.
*
* Use this after reading the HMAC result or if aborting after any of the other steps above.
*/
static inline void hmac_ll_calc_finish(void)
{
REG_WRITE(HMAC_SET_RESULT_FINISH_REG, 2);
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/huk_ll.h
+141
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use it in application code.
******************************************************************************/
#pragma once
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "esp_hal_security/huk_types.h"
#include "soc/huk_reg.h"
#include "soc/soc_caps.h"
#include "soc/lp_aon_reg.h"
#include "esp_rom_sys.h" // HUK memory recharge workaround
#ifdef __cplusplus
extern "C" {
#endif
static inline void huk_ll_power_up(void)
{
/* huk force_pd MUST be cleared!!! */
REG_CLR_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PD);
/* huk force_pu MUST be set!!! */
REG_SET_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PU);
}
/* @brief Configure the HUK mode */
static inline void huk_ll_configure_mode(const esp_huk_mode_t huk_mode)
{
REG_SET_FIELD(HUK_CONF_REG, HUK_MODE, huk_mode);
}
static inline void huk_ll_write_info(const uint8_t *buffer, const size_t size)
{
memcpy((uint8_t *)HUK_INFO_MEM, buffer, size);
}
static inline void huk_ll_read_info(uint8_t *buffer, const size_t size)
{
memcpy(buffer, (uint8_t *)HUK_INFO_MEM, size);
}
/* @brief Start the HUK at IDLE state */
static inline void huk_ll_start(void)
{
REG_SET_FIELD(HUK_START_REG, HUK_START, 1);
}
/* @brief Continue HUK operation at LOAD/GAIN state */
static inline void huk_ll_continue(void)
{
REG_SET_FIELD(HUK_START_REG, HUK_CONTINUE, 1);
}
/* @bried Enable or Disable the HUK interrupts */
static inline void huk_ll_configure_interrupt(const esp_huk_interrupt_type_t intr, const bool en)
{
switch (intr) {
case ESP_HUK_INT_PREP_DONE:
REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en);
case ESP_HUK_INT_PROC_DONE:
REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en);
case ESP_HUK_INT_POST_DONE:
REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en);
default:
return;
}
}
/* @bried Clear the HUK interrupts */
static inline void huk_ll_clear_int(const esp_huk_interrupt_type_t intr)
{
switch (intr) {
case ESP_HUK_INT_PREP_DONE:
REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1);
case ESP_HUK_INT_PROC_DONE:
REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1);
case ESP_HUK_INT_POST_DONE:
REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1);
default:
return;
}
}
/**
* @brief Read state of Hardware Unique Key Generator
*
* @return esp_huk_state_t
*/
static inline esp_huk_state_t huk_ll_get_state(void)
{
return (esp_huk_state_t) REG_GET_FIELD(HUK_STATE_REG, HUK_STATE);
}
/**
* @brief Get the HUK generation status
*/
static inline esp_huk_gen_status_t huk_ll_get_gen_status(void)
{
return (esp_huk_gen_status_t) REG_GET_FIELD(HUK_STATUS_REG, HUK_STATUS);
}
static inline void __attribute__((always_inline)) huk_ll_recharge_huk_memory(void)
{
REG_CLR_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PD);
REG_CLR_BIT(LP_AON_PUF_MEM_SW_REG, LP_AON_PUF_MEM_SW);
REG_SET_BIT(LP_AON_PUF_MEM_DISCHARGE_REG, LP_AON_PUF_MEM_DISCHARGE);
esp_rom_delay_us(100000);
REG_CLR_BIT(LP_AON_PUF_MEM_DISCHARGE_REG, LP_AON_PUF_MEM_DISCHARGE);
REG_SET_BIT(LP_AON_PUF_MEM_SW_REG, LP_AON_PUF_MEM_SW);
esp_rom_delay_us(100000);
}
/**
* @brief Read the HUK date information
*/
static inline uint32_t huk_ll_get_date_info(void)
{
// Only the least significant 28 bits have desired information
return (uint32_t)(0x0FFFFFFF & REG_READ(HUK_DATE_REG));
}
#ifdef __cplusplus
}
#endif
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/key_mgr_ll.h
+493
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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use it in application code.
******************************************************************************/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hal/assert.h"
#include "esp_hal_security/key_mgr_types.h"
#include "soc/keymng_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Read state of Key Manager
*
* @return esp_key_mgr_state_t
*/
static inline esp_key_mgr_state_t key_mgr_ll_get_state(void)
{
return (esp_key_mgr_state_t) REG_GET_FIELD(KEYMNG_STATE_REG, KEYMNG_STATE);
}
static inline void key_mgr_ll_power_up(void)
{
/* Power up the Key Manager peripheral (default state is power-down) */
REG_CLR_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PD);
REG_SET_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PU);
}
#define key_mgr_ll_enable_bus_clock(...) do { \
_key_mgr_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
static inline void key_mgr_ll_power_down(void)
{
/* Power down the Key Manager peripheral */
REG_CLR_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PU);
REG_SET_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PD);
}
/**
* @brief Enable the bus clock for Key Manager peripheral
*
* @param true to enable, false to disable
*/
static inline void _key_mgr_ll_enable_bus_clock(bool enable)
{
// Enable key manager clock
PCR.km_conf.km_clk_en = enable;
}
/**
* @brief Enable the peripheral clock for Key Manager
*
* @param true to enable, false to disable
*/
static inline void _key_mgr_ll_enable_peripheral_clock(bool enable)
{
; /* Nothing to do here, Kept for compatibility with other SoC */
}
#define key_mgr_ll_enable_peripheral_clock(...) do { \
_key_mgr_ll_enable_peripheral_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Reset the Key Manager peripheral
*
*/
static inline void _key_mgr_ll_reset_register(void)
{
PCR.km_conf.km_rst_en = 1;
PCR.km_conf.km_rst_en = 0;
// Wait for key manager to be ready
while (!PCR.km_conf.km_ready) {
};
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
};
}
#define key_mgr_ll_reset_register(...) do { \
_key_mgr_ll_reset_register(__VA_ARGS__); \
} while(0)
/* @brief Start the key manager at IDLE state */
static inline void key_mgr_ll_start(void)
{
REG_SET_BIT(KEYMNG_START_REG, KEYMNG_START);
}
/* @brief Continue key manager operation at LOAD/GAIN state */
static inline void key_mgr_ll_continue(void)
{
REG_SET_BIT(KEYMNG_START_REG, KEYMNG_CONTINUE);
}
/* @brief Enable or Disable the KEY_MGR interrupts */
static inline void key_mgr_ll_configure_interrupt(const esp_key_mgr_interrupt_type_t intr, bool en)
{
switch (intr) {
case ESP_KEY_MGR_INT_PREP_DONE:
REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
break;
case ESP_KEY_MGR_INT_PROC_DONE:
REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
break;
case ESP_KEY_MGR_INT_POST_DONE:
REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
break;
default:
return;
}
}
/* @brief Clear the KEY_MGR interrupts */
static inline void key_mgr_ll_clear_int(const esp_key_mgr_interrupt_type_t intr)
{
switch (intr) {
case ESP_KEY_MGR_INT_PREP_DONE:
REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
break;
case ESP_KEY_MGR_INT_PROC_DONE:
REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
break;
case ESP_KEY_MGR_INT_POST_DONE:
REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
break;
default:
return;
}
}
/**
* @brief Set the key manager to use the software provided init key
*/
static inline void key_mgr_ll_use_sw_init_key(void)
{
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_SW_INIT_KEY);
}
/**
* @brief Configure the key manager key usage policy for a particular key type
*
*/
static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
}
break;
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
}
break;
case ESP_KEY_MGR_HMAC_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
}
break;
case ESP_KEY_MGR_DS_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
}
break;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
}
break;
default:
HAL_ASSERT(false && "Unsupported key type");
return;
}
}
static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
default:
HAL_ASSERT(false && "Unsupported key type");
return ESP_KEY_MGR_USAGE_INVALID;
}
}
/**
* @brief Set the lock for the use_sw_init_key_reg
* After this lock has been set,
* The Key manager configuration about the use of software init key cannot be changed
*/
static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
{
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_SW_INIT_KEY_LOCK);
}
/**
* @brief Set the lock for the use_sw_init_key_reg
* After this lock has been set,
* The Key manager configuration about whether to use a particular key from efuse or key manager cannot be changed.
*/
static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
break;
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
break;
case ESP_KEY_MGR_HMAC_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
break;
case ESP_KEY_MGR_DS_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
break;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
break;
default:
HAL_ASSERT(false && "Unsupported key type");
return;
}
}
/* @brief Configure the key purpose to be used by the Key Manager for key generator operation */
static inline void key_mgr_ll_set_key_purpose(const esp_key_mgr_key_purpose_t key_purpose)
{
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, key_purpose);
}
/**
* @brief Configure the mode which is used by the Key Manager for the generator key deployment process
*/
static inline void key_mgr_ll_set_key_generator_mode(const esp_key_mgr_key_generator_mode_t mode)
{
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KGEN_MODE, mode);
}
/**
* @brief Read the key manager process result
* @return 1 for Success
* 0 for failure
*/
static inline bool key_mgr_ll_is_result_success(void)
{
return REG_GET_FIELD(KEYMNG_RESULT_REG, KEYMNG_PROC_RESULT);
}
/**
* @brief Check if the deployed key is valid or not
* @return 1 for Success
* 0 for failure
*/
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
switch (key_len) {
case ESP_KEY_MGR_ECDSA_LEN_192:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_LEN_384:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
case ESP_KEY_MGR_HMAC_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
case ESP_KEY_MGR_DS_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
default:
HAL_ASSERT(false && "Unsupported mode");
return 0;
}
}
/*
* @brief Write the SW init key in the key manager registers
*
* @input
* sw_init_key_buf Init key buffer, this should be a readable buffer of data_len size which should contain the sw init key. The buffer must be 32 bit aligned
* data_len Length of the init key buffer
*/
static inline void key_mgr_ll_write_sw_init_key(const uint8_t *sw_init_key_buf, const size_t data_len)
{
memcpy((uint8_t *)KEYMNG_SW_INIT_KEY_MEM, sw_init_key_buf, data_len);
}
/*
* @brief Write the Assist info in the key manager registers
*
* @input
* assist_info_buf Assist info buffer, this should be a readable buffer of data_len size which should contain the assist info. The buffer must be 32 bit aligned
* data_len Length of the assist info buffer
*/
static inline void key_mgr_ll_write_assist_info(const uint8_t *assist_info_buf, const size_t data_len)
{
memcpy((uint8_t *)KEYMNG_ASSIST_INFO_MEM, assist_info_buf, data_len);
}
/*
* @brief Read the Assist info from the key manager registers
*
* @input
* assist_info_buf Assist info buffer, this should be a writable buffer of size KEY_MGR_ASSIST_INFO_LEN. The buffer must be 32 bit aligned
*/
static inline void key_mgr_ll_read_assist_info(uint8_t *assist_info_buf)
{
memcpy(assist_info_buf, (uint8_t *)KEYMNG_ASSIST_INFO_MEM, KEY_MGR_ASSIST_INFO_LEN);
}
/*
* @brief Write the Public info in the key manager registers
* @input
* public_info_buf Public info buffer, this should be a readable buffer of data_len size which should contain the public info. The buffer must be 32 bit aligned
* data_len Length of the public info buffer
*/
static inline void key_mgr_ll_write_public_info(const uint8_t *public_info_buf, const size_t data_len)
{
memcpy((uint8_t *)KEYMNG_PUBLIC_INFO_MEM, public_info_buf, data_len);
}
/*
* @brief Read the Public info in the key manager registers
* @input
* public_info_buf Public info buffer, this should be a writable buffer of read_len, The buffer must be 32 bit aligned
* read_len Length of the public info buffer
*/
static inline void key_mgr_ll_read_public_info(uint8_t *public_info_buf, const size_t read_len)
{
memcpy(public_info_buf, (uint8_t *)KEYMNG_PUBLIC_INFO_MEM, read_len);
}
static inline bool key_mgr_ll_is_huk_valid(void)
{
return REG_GET_FIELD(KEYMNG_HUK_VLD_REG, KEYMNG_HUK_VALID);
}
/* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
uint32_t key_len_bit_mask;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
key_len_bit_mask = KEYMNG_FLASH_KEY_LEN;
} else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_len_bit_mask = KEYMNG_PSRAM_KEY_LEN;
} else {
HAL_ASSERT(false && "Unsupported key type");
return;
}
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
break;
case ESP_KEY_MGR_XTS_AES_LEN_256:
REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
break;
default:
HAL_ASSERT(false && "Unsupported key length");
return;
}
}
/* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline esp_key_mgr_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
{
uint32_t key_len_bit = 0;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
key_len_bit = REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
} else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_len_bit = REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
} else {
HAL_ASSERT(false && "Unsupported key type");
return (esp_key_mgr_key_len_t) key_len_bit;
}
switch (key_len_bit) {
case 0:
return ESP_KEY_MGR_XTS_AES_LEN_128;
case 1:
return ESP_KEY_MGR_XTS_AES_LEN_256;
default:
HAL_ASSERT(false && "Unsupported key length");
return (esp_key_mgr_key_len_t) key_len_bit;
}
}
/**
* @brief Read the Key Manager date information
*/
static inline uint32_t key_mgr_ll_get_date_info(void)
{
// Only the least significant 28 bits have desired information
return (uint32_t)(0x0FFFFFFF & REG_READ(KEYMNG_DATE_REG));
}
static inline bool key_mgr_ll_is_supported(void)
{
return true;
}
static inline bool key_mgr_ll_flash_encryption_supported(void)
{
if (!key_mgr_ll_is_supported() || efuse_hal_chip_revision() <= 100) {
return false;
}
return true;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/mpi_ll.h
+184
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/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "esp_hal_security/mpi_types.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/rsa_reg.h"
#include "soc/mpi_periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for MPI peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void mpi_ll_enable_bus_clock(bool enable)
{
PCR.rsa_conf.rsa_clk_en = enable;
}
/**
* @brief Reset the MPI peripheral module
*/
static inline void mpi_ll_reset_register(void)
{
PCR.rsa_conf.rsa_rst_en = 1;
PCR.rsa_conf.rsa_rst_en = 0;
// Clear reset on digital signature also, otherwise RSA is held in reset
PCR.ds_conf.ds_rst_en = 0;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;
}
static inline void mpi_ll_power_up(void)
{
/* Power up the MPI peripheral (default is power-down state) */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD);
}
static inline void mpi_ll_power_down(void)
{
/* Power down the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU);
REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
}
static inline void mpi_ll_enable_interrupt(void)
{
REG_WRITE(RSA_INT_ENA_REG, 1);
}
static inline void mpi_ll_disable_interrupt(void)
{
REG_WRITE(RSA_INT_ENA_REG, 0);
}
static inline void mpi_ll_clear_interrupt(void)
{
REG_WRITE(RSA_INT_CLR_REG, 1);
}
static inline bool mpi_ll_check_memory_init_complete(void)
{
return REG_READ(RSA_QUERY_CLEAN_REG) == 0;
}
static inline void mpi_ll_start_op(mpi_op_t op)
{
REG_WRITE(MPI_OPERATIONS_REG[op], 1);
}
static inline bool mpi_ll_get_int_status(void)
{
return REG_READ(RSA_QUERY_IDLE_REG) == 0;
}
/* Copy MPI bignum (p) to hardware memory block at 'mem_base'.
If num_words is higher than the number of words (n) in the bignum then
these additional words will be zeroed in the memory buffer.
*/
static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words)
{
uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
uint32_t* pbase = (uint32_t*) mem_base;
uint32_t copy_words = MIN(num_words, n);
/* Copy MPI data to memory block registers */
for (int i = 0; i < copy_words; i++) {
pbase[i] = p[i];
}
/* Zero any remaining memory block data */
for (int i = copy_words; i < num_words; i++) {
pbase[i] = 0;
}
}
static inline void mpi_ll_write_m_prime(uint32_t Mprime)
{
REG_WRITE(RSA_M_PRIME_REG, Mprime);
}
static inline void mpi_ll_write_rinv(uint32_t rinv)
{
REG_WRITE(MPI_BLOCK_BASES[MPI_PARAM_Z], rinv);
}
static inline void mpi_ll_write_at_offset(mpi_param_t param, int offset, uint32_t value)
{
uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
REG_WRITE(mem_base, value);
}
/* Read MPI bignum (p) back from hardware memory block.
Reads z_words words from block.
*/
static inline void mpi_ll_read_from_mem_block(uint32_t* p, size_t n, size_t num_words)
{
uint32_t mem_base = MPI_BLOCK_BASES[MPI_PARAM_Z];
/* Copy data from memory block registers */
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < num_words; i++) {
p[i] = REG_READ(mem_base + (i * REG_WIDTH));
}
/* Zero any remaining limbs in the bignum, if the buffer is bigger
than num_words */
for (size_t i = num_words; i < n; i++) {
p[i] = 0;
}
}
static inline void mpi_ll_set_mode(size_t length)
{
REG_WRITE(RSA_MODE_REG, length);
}
static inline void mpi_ll_disable_constant_time(void)
{
REG_WRITE(RSA_CONSTANT_TIME_REG, 0);
}
static inline void mpi_ll_enable_constant_time(void)
{
REG_WRITE(RSA_CONSTANT_TIME_REG, 1);
}
static inline void mpi_ll_disable_search(void)
{
REG_WRITE(RSA_SEARCH_ENABLE_REG, 0);
}
static inline void mpi_ll_enable_search(void)
{
REG_WRITE(RSA_SEARCH_ENABLE_REG, 1);
}
static inline void mpi_ll_set_search_position(size_t pos)
{
REG_WRITE(RSA_SEARCH_POS_REG, pos);
}
#ifdef __cplusplus
}
#endif
components/esp_hal_security/esp32c5/include/esp_hal_security/sha_ll.h
+196
View File
@@ -0,0 +1,196 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "soc/pcr_struct.h"
#include "esp_hal_security/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
PCR.sha_conf.sha_clk_en = enable;
}
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
PCR.sha_conf.sha_rst_en = 1;
PCR.sha_conf.sha_rst_en = 0;
// Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset
PCR.ds_conf.ds_rst_en = 0;
PCR.hmac_conf.hmac_rst_en = 0;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
/**
* @brief Load the mode for the SHA engine
*
* @param sha_type The SHA algorithm type
*/
static inline void sha_ll_set_mode(esp_sha_type sha_type)
{
REG_WRITE(SHA_MODE_REG, sha_type);
}
/**
* @brief Start a new SHA block conversions (no initial hash in HW)
*
* @param sha_type The SHA algorithm type
*/
static inline void sha_ll_start_block(esp_sha_type sha_type)
{
(void) sha_type;
REG_WRITE(SHA_START_REG, 1);
}
/**
* @brief Continue a SHA block conversion (initial hash in HW)
*
* @param sha_type The SHA algorithm type
*/
static inline void sha_ll_continue_block(esp_sha_type sha_type)
{
(void) sha_type;
REG_WRITE(SHA_CONTINUE_REG, 1);
}
/**
* @brief Start a new SHA message conversion using DMA (no initial hash in HW)
*/
static inline void sha_ll_start_dma(void)
{
REG_WRITE(SHA_DMA_START_REG, 1);
}
/**
* @brief Continue a SHA message conversion using DMA (initial hash in HW)
*/
static inline void sha_ll_continue_dma(void)
{
REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
}
/**
* @brief Load the current hash digest to digest register
*
* @note Happens automatically on ESP32C6
*
* @param sha_type The SHA algorithm type
*/
static inline void sha_ll_load(esp_sha_type sha_type)
{
}
/**
* @brief Sets the number of message blocks to be hashed
*
* @note DMA operation only
*
* @param num_blocks Number of message blocks to process
*/
static inline void sha_ll_set_block_num(size_t num_blocks)
{
REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks);
}
/**
* @brief Checks if the SHA engine is currently busy hashing a block
*
* @return true SHA engine busy
* @return false SHA engine idle
*/
static inline bool sha_ll_busy(void)
{
return REG_READ(SHA_BUSY_REG);
}
/**
* @brief Write a text (message) block to the SHA engine
*
* @param input_text Input buffer to be written to the SHA engine
* @param block_word_len Number of words in block
*/
static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
{
uint32_t *data_words = (uint32_t *)input_text;
uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM);
for (int i = 0; i < block_word_len; i++) {
REG_WRITE(&reg_addr_buf[i], data_words[i]);
}
}
/**
* @brief Read the message digest from the SHA engine
*
* @param sha_type The SHA algorithm type
* @param digest_state Buffer that message digest will be written to
* @param digest_word_len Length of the message digest
*/
static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
{
uint32_t *digest_state_words = (uint32_t *)digest_state;
const size_t REG_WIDTH = sizeof(uint32_t);
for (size_t i = 0; i < digest_word_len; i++) {
digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH));
}
}
/**
* @brief Write the message digest to the SHA engine
*
* @param sha_type The SHA algorithm type
* @param digest_state Message digest to be written to SHA engine
* @param digest_word_len Length of the message digest
*/
static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
{
uint32_t *digest_state_words = (uint32_t *)digest_state;
uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM);
for (int i = 0; i < digest_word_len; i++) {
REG_WRITE(&reg_addr_buf[i], digest_state_words[i]);
}
}
/**
* @brief Sets SHA512_t T_string parameter
*
* @param t_string T_string parameter
*/
static inline void sha_ll_t_string_set(uint32_t t_string)
{
REG_WRITE(SHA_T_STRING_REG, t_string);
}
/**
* @brief Sets SHA512_t T_string parameter's length
*
* @param t_len T_string parameter length
*/
static inline void sha_ll_t_len_set(uint8_t t_len)
{
REG_WRITE(SHA_T_LENGTH_REG, t_len);
}
#ifdef __cplusplus
}
#endif