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refactor(mspi): move esp_mspi_align and mspi_mem_barrier to esp_mspi

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This commit is contained in:
Armando (Dou Yiwen)
2026-08-25 18:01:30 +08:00
parent 90dd358dcb
commit 5e181236b7
15 changed files with 61 additions and 54 deletions
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10
components/esp_hw_support/CMakeLists.txt
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@@ -14,8 +14,6 @@ endif()
set(public_include_dirs "include" "include/soc"
"ldo/include" "debug_probe/include" "etm/include"
"mspi/esp_mspi_align/include"
"mspi/mspi_mem_barrier/include"
"power_supply/include" "modem/include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/include/soc/${target}")
@@ -53,9 +51,6 @@ set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.
)
set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "mspi/esp_mspi_align/esp_mspi_align.c")
endif()
if(NOT non_os_build)
list(APPEND srcs "esp_clk.c"
"clk_ctrl_os.c"
@@ -74,8 +69,7 @@ if(NOT non_os_build)
"port/${target}/esp_clk_tree.c"
"spi_bus_lock.c"
"heap_align_hw.c"
"clk_utils.c"
"mspi/mspi_mem_barrier/mspi_mem_barrier.c")
"clk_utils.c")
if(CONFIG_SOC_USB_OTG_SUPPORTED)
list(APPEND srcs "usb_phy/usb_phy.c")
endif()
@@ -189,7 +183,7 @@ idf_component_register(SRCS ${srcs}
PRIV_INCLUDE_DIRS port/include include/esp_private
REQUIRES ${requires}
PRIV_REQUIRES "${priv_requires}"
LDFRAGMENTS linker.lf ldo/linker.lf mspi/linker.lf)
LDFRAGMENTS linker.lf ldo/linker.lf)
idf_define_esp_err_codes(HEADERS include/esp_memprot_err.h)

59
components/esp_hw_support/mspi/esp_mspi_align/esp_mspi_align.c
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@@ -1,59 +0,0 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <sys/param.h>
#include "sdkconfig.h"
#include "esp_efuse.h"
#include "esp_memory_utils.h"
#include "esp_private/esp_mspi_align.h"
#if CONFIG_SPIRAM
#include "esp_psram.h"
#endif /* CONFIG_SPIRAM */
#include "soc/soc_caps.h"
#define MSPI_FLASH_ENC_ALIGNMENT SOC_MEMSPI_ENCRYPTION_ALIGNMENT
#define MSPI_PSRAM_ECC_ALIGNMENT SOC_MEMSPI_ENCRYPTION_ALIGNMENT
size_t esp_mspi_get_alignment(const void *ptr)
{
size_t alignment = 1;
bool generic_query = ptr == NULL;
bool __attribute__((unused)) is_psram = esp_ptr_external_ram(ptr);
bool is_drom = esp_ptr_in_drom(ptr);
bool is_psram_enc = false;
#if CONFIG_SPIRAM
is_psram_enc = is_psram && !esp_psram_ptr_is_no_enc(ptr);
#endif /* CONFIG_SPIRAM */
if ((generic_query || is_drom || is_psram_enc) && esp_efuse_is_flash_encryption_enabled()) {
alignment = MAX(alignment, MSPI_FLASH_ENC_ALIGNMENT);
}
#if CONFIG_SPIRAM_ECC_ENABLE
if (generic_query || is_psram) {
alignment = MAX(alignment, MSPI_PSRAM_ECC_ALIGNMENT);
}
#endif
return alignment;
}
bool esp_mspi_buffer_alignment_satisfied(const void *ptr, size_t size)
{
// Zero-length is not a valid MSPI transfer, so it never satisfies the check.
if (ptr == NULL || size == 0) {
return false;
}
size_t alignment = esp_mspi_get_alignment(ptr);
if (alignment <= 1) {
return true;
}
uintptr_t addr = (uintptr_t)ptr;
return ((addr & (alignment - 1)) == 0) && ((size & (alignment - 1)) == 0);
}

46
components/esp_hw_support/mspi/esp_mspi_align/include/esp_private/esp_mspi_align.h
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@@ -1,46 +0,0 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get MSPI alignment requirement for an address
*
* The address is used so future targets can apply different alignment rules to
* different MSPI-backed regions. Pass NULL when only the generic external-memory
* requirement is needed and no concrete address is available yet.
*
* @param ptr Buffer pointer in the region to be accessed, or NULL for generic query
* @return Required alignment in bytes, or 1 when no extra MSPI alignment is needed
*/
size_t esp_mspi_get_alignment(const void *ptr);
/**
* @brief Check whether a buffer satisfies MSPI strict alignment requirements
*
* Returns false when @p ptr is NULL or @p size is 0 (not a valid transfer).
* When strict alignment is not required, returns true for any non-empty buffer.
* When required, both @p ptr and @p size must be aligned to the rule returned by
* @ref esp_mspi_get_alignment for that address.
*
* @param ptr Buffer pointer
* @param size Transfer size in bytes
* @return true if alignment requirements are satisfied
*/
bool esp_mspi_buffer_alignment_satisfied(const void *ptr, size_t size);
#ifdef __cplusplus
}
#endif

6
components/esp_hw_support/mspi/linker.lf
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@@ -1,6 +0,0 @@
[mapping:esp_mspi_align]
archive: libesp_hw_support.a
entries:
if APP_BUILD_TYPE_PURE_RAM_APP = n:
esp_mspi_align:esp_mspi_get_alignment (noflash)
esp_mspi_align:esp_mspi_buffer_alignment_satisfied (noflash)

37
components/esp_hw_support/mspi/mspi_mem_barrier/include/esp_private/mspi_mem_barrier.h
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@@ -1,37 +0,0 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the MSPI memory barrier workaround
*
* On targets affected by the MSPI memory barrier hardware issue, this allocates the
* dummy cacheline used by @ref esp_psram_mspi_mb to force a cache writeback/fence. On
* other targets this is a no-op.
*
* @return ESP_OK on success, otherwise an error code
*/
esp_err_t esp_psram_mspi_mb_init(void);
/**
* @brief MSPI memory barrier
*
* Some targets need this workaround after a DMA transfer into PSRAM to make sure the
* data is visible to the CPU. This is a no-op on targets that don't need the workaround.
*/
void esp_psram_mspi_mb(void);
#ifdef __cplusplus
}
#endif

47
components/esp_hw_support/mspi/mspi_mem_barrier/mspi_mem_barrier.c
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@@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_cache.h"
#include "esp_heap_caps.h"
#include "esp_private/mspi_mem_barrier.h"
#define MSPI_MEM_BARRIER_WORKAROUND ((CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101))
__attribute__((unused)) ESP_LOG_ATTR_TAG_DRAM(TAG, "mspi_mem_barrier");
#if MSPI_MEM_BARRIER_WORKAROUND
static void *s_psram_mb_dummy_cacheline; //dummy cacheline for cache memory barrier
#endif
esp_err_t esp_psram_mspi_mb_init(void)
{
#if MSPI_MEM_BARRIER_WORKAROUND
s_psram_mb_dummy_cacheline = heap_caps_calloc(1, CONFIG_CACHE_L1_CACHE_LINE_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_CACHE_ALIGNED);
if (!s_psram_mb_dummy_cacheline) {
ESP_EARLY_LOGE(TAG, "Failed to allocate dummy cacheline for PSRAM memory barrier!");
}
#endif
return ESP_OK;
}
void IRAM_ATTR esp_psram_mspi_mb(void)
{
#if MSPI_MEM_BARRIER_WORKAROUND
if (s_psram_mb_dummy_cacheline) {
uint32_t *p = (uint32_t *)s_psram_mb_dummy_cacheline;
*p = (*p + 1) % UINT32_MAX;
__attribute__((unused)) esp_err_t ret = ESP_FAIL;
ret = esp_cache_msync(s_psram_mb_dummy_cacheline, sizeof(uint32_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); //malloc is aligned, no need to writeback all
assert(ret == ESP_OK);
asm volatile("fence");
}
#endif
}