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refactoring(spi_flash): Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h

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- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
  MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
This commit is contained in:
Xiao Xufeng
2026-04-22 02:31:06 +08:00
parent 0bed60db48
commit 5cbeaaf7f9
14 changed files with 15 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/clk_utils.c
+2 -3
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@@ -11,7 +11,6 @@
#include "sdkconfig.h" #include "sdkconfig.h"
#include "esp_check.h" #include "esp_check.h"
#include "esp_log.h" #include "esp_log.h"
#include "soc/soc_caps.h"
#include "soc/rtc.h" #include "soc/rtc.h"
#include "hal/mspi_ll.h" #include "hal/mspi_ll.h"
#include "hal/clk_tree_ll.h" #include "hal/clk_tree_ll.h"
@@ -36,7 +35,7 @@ void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t targe
if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) { if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(true); mspi_timing_change_speed_mode_cache_safe(true);
} }
#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM #elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU /* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow. * frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
*/ */
@@ -58,7 +57,7 @@ void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target
if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) { if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(false); mspi_timing_change_speed_mode_cache_safe(false);
} }
#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM #elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU /* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow. * frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
*/ */
components/hal/esp32c5/include/hal/mspi_ll.h
+3
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@@ -38,6 +38,9 @@ extern "C" {
#define MSPI_LL_CORE_CLOCK_120_MHZ 120 #define MSPI_LL_CORE_CLOCK_120_MHZ 120
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ #define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
/*--------------------------------------------------------------- /*---------------------------------------------------------------
MSPI MSPI
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
components/hal/esp32c61/include/hal/mspi_ll.h
+3
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@@ -38,6 +38,9 @@ extern "C" {
#define MSPI_LL_CORE_CLOCK_120_MHZ 120 #define MSPI_LL_CORE_CLOCK_120_MHZ 120
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ #define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
/************************** MSPI pll clock configurations **************************/ /************************** MSPI pll clock configurations **************************/
/* /*
components/hal/esp32h21/include/hal/mspi_ll.h
+3
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@@ -26,6 +26,9 @@
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/assert.h" #include "hal/assert.h"
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
components/hal/esp32p4/include/hal/mspi_ll.h
+3
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@@ -48,6 +48,9 @@ extern "C" {
#define MSPI_TIMING_LL_MSPI_ID_0 0 #define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1 #define MSPI_TIMING_LL_MSPI_ID_1 1
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
#define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4 #define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4
#define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6 #define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6
#define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1 #define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
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@@ -1255,10 +1255,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool bool
default y default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_SPI_MEM_FLASH_SUPPORT_HPM config SOC_SPI_MEM_FLASH_SUPPORT_HPM
bool bool
default y default y
components/soc/esp32c5/include/soc/soc_caps.h
-1
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@@ -483,7 +483,6 @@
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ #define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-4
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@@ -863,10 +863,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool bool
default y default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_SPI_MEM_FLASH_SUPPORT_HPM config SOC_SPI_MEM_FLASH_SUPPORT_HPM
bool bool
default y default y
components/soc/esp32c61/include/soc/soc_caps.h
-1
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@@ -349,7 +349,6 @@
#define SOC_SPI_MEM_SUPPORT_WRAP (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */ #define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
-4
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@@ -267,10 +267,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool bool
default y default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
bool bool
default y default y
components/soc/esp32h4/include/soc/soc_caps.h
-1
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@@ -414,7 +414,6 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
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@@ -1691,10 +1691,6 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool bool
default y default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool bool
default y default y
components/soc/esp32p4/include/soc/soc_caps.h
-1
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@@ -618,7 +618,6 @@
#define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1) #define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1) #define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1) #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1)
components/spi_flash/esp_flash_spi_init.c
+1 -1
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@@ -146,7 +146,7 @@ esp_flash_t *esp_flash_default_chip = NULL;
// 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ) // 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ)
// 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz) // 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz)
// 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode // 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode
// This happens when: SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM && // This happens when: MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
// (target_cpu_freq < CONFIG_SPIRAM_SPEED) // (target_cpu_freq < CONFIG_SPIRAM_SPEED)
// Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c, // Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c,
// which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode. // which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode.