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refactoring(spi_flash): Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h

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- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
  MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
This commit is contained in:
Xiao Xufeng
2026-04-22 02:31:06 +08:00
parent 0bed60db48
commit 5cbeaaf7f9
14 changed files with 15 additions and 24 deletions
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components/spi_flash/esp_flash_spi_init.c
+1 -1
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@@ -146,7 +146,7 @@ esp_flash_t *esp_flash_default_chip = NULL;
// 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ)
// 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz)
// 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode
// This happens when: SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
// This happens when: MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
// (target_cpu_freq < CONFIG_SPIRAM_SPEED)
// Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c,
// which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode.