diff --git a/components/esp_phy/include/esp_private/phy.h b/components/esp_phy/include/esp_private/phy.h
index 25723d993f4..b08f0ede614 100644
--- a/components/esp_phy/include/esp_private/phy.h
+++ b/components/esp_phy/include/esp_private/phy.h
@@ -217,7 +217,7 @@ void phy_ant_clr_update_flag(void);
  */
 void phy_ant_update(void);
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 /**
  * @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode
  *
diff --git a/components/esp_phy/src/phy_common.c b/components/esp_phy/src/phy_common.c
index 91c2dcf0360..8de60bae03b 100644
--- a/components/esp_phy/src/phy_common.c
+++ b/components/esp_phy/src/phy_common.c
@@ -366,7 +366,7 @@ esp_err_t esp_phy_get_ant(esp_phy_ant_config_t *config)
     return ESP_OK;
 }
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 typedef enum {
     PHY_I2C_MST_CMD_TYPE_RF_OFF = 0,
     PHY_I2C_MST_CMD_TYPE_RF_ON,
@@ -376,8 +376,13 @@ typedef enum {
 
 static uint32_t phy_ana_i2c_master_burst_config(phy_i2c_master_command_attribute_t *attr, int size, phy_i2c_master_command_type_t type)
 {
+#if !CONFIG_IDF_TARGET_ESP32H4
     #define I2C1_BURST_VAL(en, start, end) (((en) << 31) | ((end) << 22) | ((start) << 16))
     #define I2C0_BURST_VAL(en, start, end) (((en) << 15) | ((end) <<  6) | ((start) <<  0))
+#else
+    #define I2C0_BURST_VAL(valid, start, end) (((valid) << 15) | ((end) << 7) | (start))
+    #define I2C1_BURST_VAL(valid, start, end) (((valid) << 31) | ((end) << 23) | ((start) << 16))
+#endif // !CONFIG_IDF_TARGET_ESP32H4
 
     uint32_t brust = 0;
     for (int i = 0; i < size; i++) {
diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c
index ac87a92e2bf..1bdff3bbf37 100644
--- a/components/esp_phy/src/phy_init.c
+++ b/components/esp_phy/src/phy_init.c
@@ -46,7 +46,7 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
-#elif SOC_PM_SUPPORT_PMU_MODEM_STATE
+#elif SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 #include "esp_private/sleep_modem.h"
 #endif
 #include "hal/efuse_hal.h"
diff --git a/components/esp_phy/src/phy_init_esp32hxx.c b/components/esp_phy/src/phy_init_esp32hxx.c
index 0f56118e3b3..6916ae0feb7 100644
--- a/components/esp_phy/src/phy_init_esp32hxx.c
+++ b/components/esp_phy/src/phy_init_esp32hxx.c
@@ -10,18 +10,24 @@
 #include "esp_private/phy.h"
 #include "esp_timer.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_log.h"
 
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT
 #include "esp_private/esp_modem_clock.h"
 #endif
 #include "phy_init_deps.h"
 #include "esp_private/phy_debug.h"
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#include "esp_private/sleep_modem.h"
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 
 #ifndef PHY_INIT_MODEM_CLOCK_REQUIRED_BITS
 #warning "PHY_INIT_MODEM_CLOCK_REQUIRED_BITS not defined; using default value 0"
 #define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0
 #endif
 
+static const char* TAG = "phy_init";
+
 static DRAM_ATTR portMUX_TYPE s_phy_int_mux = portMUX_INITIALIZER_UNLOCKED;
 
 extern void phy_version_print(void);
@@ -71,7 +77,14 @@ void esp_phy_enable(esp_phy_modem_t modem)
 #endif
             s_phy_is_enabled = true;
         } else {
-            phy_wakeup_init();
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+            if (sleep_modem_phy_link_enabled() && sleep_modem_phy_link_done()) {
+                sleep_modem_do_phy_retention(true, false, SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION);
+            } else
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+            {
+                phy_wakeup_init();
+            }
         }
 #if !CONFIG_ESP_PHY_DISABLE_PLL_TRACK
         phy_track_pll_init();
@@ -102,9 +115,16 @@ void esp_phy_disable(esp_phy_modem_t modem)
 #if !CONFIG_ESP_PHY_DISABLE_PLL_TRACK
         phy_track_pll_deinit();
 #endif
-        phy_close_rf();
-        phy_xpd_tsens();
-        phy_wait_freq_hw_hop_done();
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+        if (sleep_modem_phy_link_enabled()) {
+            sleep_modem_do_phy_retention(false, false, SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION);
+        } else
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
+        {
+            phy_close_rf();
+            phy_xpd_tsens();
+            phy_wait_freq_hw_hop_done();
+        }
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT
         modem_clock_module_disable(PERIPH_PHY_MODULE);
 #endif
@@ -116,3 +136,23 @@ _lock_t phy_get_lock(void)
 {
     return s_phy_access_lock;
 }
+
+void esp_phy_modem_init(uint8_t modem)
+{
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+    _lock_acquire(&s_phy_access_lock);
+    if (sleep_modem_phy_init(modem) != ESP_OK) {
+        ESP_LOGE(TAG, "failed to initialize sleep modem phy");
+    }
+    _lock_release(&s_phy_access_lock);
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
+}
+
+void esp_phy_modem_deinit(uint8_t modem)
+{
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+    _lock_acquire(&s_phy_access_lock);
+    sleep_modem_phy_deinit(modem);
+    _lock_release(&s_phy_access_lock);
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
+}