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Merge branch 'feat/esp32p4eco_sleep_feature_update_v5.3' into 'release/v5.3'

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feat(esp_hw_support): esp32p4eco1 sleep feature update (v5.3)

See merge request espressif/esp-idf!31682
This commit is contained in:
Jiang Jiang Jian
2024-07-15 19:35:56 +08:00
parent 172784733c 64ace5b6d8
commit 5c180bf3b6
15 changed files with 129 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/port/esp32c5/pmu_sleep.c
+5
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@@ -14,6 +14,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/pmu_struct.h"
#include "hal/efuse_hal.h"
#include "hal/lp_aon_hal.h"
#include "esp_private/esp_pmu.h"
#include "pmu_param.h"
@@ -280,6 +281,10 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
bool pmu_sleep_finish(bool dslp)
{
(void)dslp;
// Wait eFuse memory update done.
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
components/esp_hw_support/port/esp32c6/pmu_sleep.c
+4
View File
@@ -347,6 +347,10 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
bool pmu_sleep_finish(bool dslp)
{
(void)dslp;
// Wait eFuse memory update done.
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+19
View File
@@ -11,6 +11,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_private/rtc_clk.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp32p4/rom/cache.h"
#include "soc/chip_revision.h"
@@ -22,6 +23,7 @@
#include "soc/pau_reg.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "hal/clk_tree_hal.h"
#include "hal/lp_aon_hal.h"
#include "soc/lp_system_reg.h"
#include "hal/pmu_hal.h"
@@ -290,6 +292,8 @@ FORCE_INLINE_ATTR void sleep_writeback_l1_dcache(void) {
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE));
}
static TCM_DRAM_ATTR uint32_t s_mpll_freq_mhz_before_sleep = 0;
TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
{
lp_aon_hal_inform_wakeup_type(dslp);
@@ -302,8 +306,15 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
// !!! Need to manually check that data in L2 memory will not be modified from now on. !!!
sleep_writeback_l1_dcache();
// !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
if (s_mpll_freq_mhz_before_sleep) {
rtc_clk_mpll_disable();
}
/* Start entry into sleep mode */
pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
@@ -333,6 +344,14 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
pmu_sleep_shutdown_ldo();
}
if (s_mpll_freq_mhz_before_sleep) {
rtc_clk_mpll_enable();
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
}
// Wait eFuse memory update done.
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
unsigned chip_version = efuse_hal_chip_revision();
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
components/esp_hw_support/port/esp32p4/rtc_clk.c
+4 -4
View File
@@ -28,7 +28,7 @@ static const char *TAG = "rtc_clk";
static int s_cur_cpll_freq = 0;
// MPLL frequency option, 400MHz. Zero if MPLL is not enabled.
static DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
static TCM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
void rtc_clk_32k_enable(bool enable)
{
@@ -484,13 +484,13 @@ bool rtc_dig_8m_enabled(void)
}
//------------------------------------MPLL-------------------------------------//
void rtc_clk_mpll_disable(void)
TCM_IRAM_ATTR void rtc_clk_mpll_disable(void)
{
clk_ll_mpll_disable();
s_cur_mpll_freq = 0;
}
void rtc_clk_mpll_enable(void)
TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
{
clk_ll_mpll_enable();
}
@@ -508,7 +508,7 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
s_cur_mpll_freq = mpll_freq;
}
uint32_t rtc_clk_mpll_get_freq(void)
TCM_IRAM_ATTR uint32_t rtc_clk_mpll_get_freq(void)
{
return s_cur_mpll_freq;
}