Merge branch 'refactor/rename_h2_to_h4' into 'master'

esp32h2: renaming esp32h2 to esp32h4

Closes IDF-6098

See merge request espressif/esp-idf!20676

components/esp_hw_support/cpu.c

@@ -303,12 +303,12 @@ void esp_cpu_configure_region_protection(void)
 
     mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
 }
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4
 void esp_cpu_configure_region_protection(void)
 {
     /* Notes on implementation:
      *
-     * 1) Note: ESP32-C3/H2 CPU doesn't support overlapping PMP regions
+     * 1) Note: ESP32-C3/H4 CPU doesn't support overlapping PMP regions
      *
      * 2) Therefore, we use TOR (top of range) entries to map the whole address
      * space, bottom to top.

components/esp_hw_support/esp_clk.c

@@ -29,9 +29,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #include "esp32c3/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/rtc.h"
-#include "esp32h2/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rom/rtc.h"
+#include "esp32h4/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/rtc.h"
 #include "esp32c2/rtc.h"

components/esp_hw_support/include/esp_chip_info.h

@@ -24,7 +24,7 @@ typedef enum {
     CHIP_ESP32S2 = 2, //!< ESP32-S2
     CHIP_ESP32S3 = 9, //!< ESP32-S3
     CHIP_ESP32C3 = 5, //!< ESP32-C3
-    CHIP_ESP32H2 = 6, //!< ESP32-H2
+    CHIP_ESP32H4 = 6, //!< ESP32-H4
     CHIP_ESP32C2 = 12, //!< ESP32-C2
     CHIP_ESP32C6 = 13, //!< ESP32-C6
 } esp_chip_model_t;

components/esp_hw_support/include/esp_mac.h

@@ -37,8 +37,8 @@ typedef enum {
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
-#elif CONFIG_IDF_TARGET_ESP32H2
-#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H2_UNIVERSAL_MAC_ADDRESSES
+#elif CONFIG_IDF_TARGET_ESP32H4
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H4_UNIVERSAL_MAC_ADDRESSES
 #elif CONFIG_IDF_TARGET_ESP32C2
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES
 #elif CONFIG_IDF_TARGET_ESP32C6

components/esp_hw_support/include/esp_private/esp_sleep_internal.h

@@ -22,7 +22,7 @@ extern "C" {
 void esp_sleep_enable_adc_tsens_monitor(bool enable);
 
 // TODO: IDF-6051, IDF-6052
-#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
+#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
 /**
  * @brief Isolate all digital IOs except those that are held during deep sleep
  *

components/esp_hw_support/include/soc/esp32h4/rtc.h

@@ -13,7 +13,7 @@ extern "C" {
 #endif
 
 /**
- * @file esp32h2/rtc.h
+ * @file esp32h4/rtc.h
  *
  * This file contains declarations of rtc related functions.
  */

components/esp_hw_support/include/soc/esp32h4/soc_memprot_types.h

@@ -5,7 +5,7 @@
  */
 
 //////////////////////////////////////////////////////////
-// ESP32-H2 PMS memory protection types
+// ESP32-H4 PMS memory protection types
 //
 
 #pragma once

components/esp_hw_support/mac_addr.c

@@ -221,10 +221,10 @@ esp_err_t esp_read_mac(uint8_t *mac, esp_mac_type_t type)
     case ESP_MAC_BT:
 #if CONFIG_ESP_MAC_ADDR_UNIVERSE_BT
         memcpy(mac, efuse_mac, 6);
-#if !CONFIG_IDF_TARGET_ESP32H2
-        // esp32h2 chips do not have wifi module, so the mac address do not need to add the BT offset
+#if !CONFIG_IDF_TARGET_ESP32H4
+        // esp32h4 chips do not have wifi module, so the mac address do not need to add the BT offset
         mac[5] += MAC_ADDR_UNIVERSE_BT_OFFSET;
-#endif //!CONFIG_IDF_TARGET_ESP32H2
+#endif //!CONFIG_IDF_TARGET_ESP32H4
 #else
         return ESP_ERR_NOT_SUPPORTED;
 #endif // CONFIG_ESP_MAC_ADDR_UNIVERSE_BT

components/esp_hw_support/port/esp32h4/Kconfig.hw_support

@@ -1,6 +1,6 @@
-choice ESP32H2_REV_MIN
-    prompt "Minimum Supported ESP32-H2 Revision"
-    default ESP32H2_REV_MIN_0
+choice ESP32H4_REV_MIN
+    prompt "Minimum Supported ESP32-H4 Revision"
+    default ESP32H4_REV_MIN_0
     help
         Required minimum chip revision. ESP-IDF will check for it and
         reject to boot if the chip revision fails the check.
@@ -9,33 +9,33 @@ choice ESP32H2_REV_MIN
         The complied binary will only support chips above this revision,
         this will also help to reduce binary size.
 
-    config ESP32H2_REV_MIN_0
+    config ESP32H4_REV_MIN_0
         bool "Rev v0.0 (ECO0)"
 endchoice
 
-config ESP32H2_REV_MIN_FULL
+config ESP32H4_REV_MIN_FULL
     int
-    default 0 if ESP32H2_REV_MIN_0
+    default 0 if ESP32H4_REV_MIN_0
 
 config ESP_REV_MIN_FULL
     int
-    default ESP32H2_REV_MIN_FULL
+    default ESP32H4_REV_MIN_FULL
 
     #
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-H2 Revision (Rev v1.99)"
+    comment "Maximum Supported ESP32-H4 Revision (Rev v1.99)"
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
-    # Supports all chips starting from ESP32H2_REV_MIN_FULL to ESP32H2_REV_MAX_FULL
+    # Supports all chips starting from ESP32H4_REV_MIN_FULL to ESP32H4_REV_MAX_FULL
 
-config ESP32H2_REV_MAX_FULL
+config ESP32H4_REV_MAX_FULL
     int
     default 199
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL
     int
-    default ESP32H2_REV_MAX_FULL
+    default ESP32H4_REV_MAX_FULL

components/esp_hw_support/port/esp32h4/Kconfig.mac

@@ -1,18 +1,18 @@
-# ESP32H2-TODO: IDF-3390
-choice ESP32H2_UNIVERSAL_MAC_ADDRESSES
+# ESP32H4-TODO: IDF-3390
+choice ESP32H4_UNIVERSAL_MAC_ADDRESSES
     bool "Number of universally administered (by IEEE) MAC address"
-    default ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
+    default ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
     help
         Configure the number of universally administered (by IEEE) MAC addresses.
         During initialization, MAC addresses for each network interface are generated or derived from a
         single base MAC address.
 
-    config ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
+    config ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
         bool "Two"
         select ESP_MAC_ADDR_UNIVERSE_IEEE802154
         select ESP_MAC_ADDR_UNIVERSE_BT
 endchoice
 
-config ESP32H2_UNIVERSAL_MAC_ADDRESSES
+config ESP32H4_UNIVERSAL_MAC_ADDRESSES
     int
-    default 2 if ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
+    default 2 if ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO

components/esp_hw_support/port/esp32h4/chip_info.c

@@ -11,7 +11,7 @@
 void esp_chip_info(esp_chip_info_t *out_info)
 {
     memset(out_info, 0, sizeof(*out_info));
-    out_info->model = CHIP_ESP32H2;
+    out_info->model = CHIP_ESP32H4;
     out_info->revision = efuse_hal_chip_revision();
     out_info->cores = 1;
     out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;

components/esp_hw_support/port/esp32h4/esp_ds.c

@@ -15,7 +15,7 @@
 #include "hal/ds_hal.h"
 #include "hal/ds_ll.h"
 #include "hal/hmac_hal.h"
-#include "esp32h2/rom/digital_signature.h"
+#include "esp32h4/rom/digital_signature.h"
 #include "esp_timer.h"
 #include "esp_ds.h"
 

components/esp_hw_support/port/esp32h4/rtc_clk.c

@@ -10,10 +10,10 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32h2/rom/ets_sys.h"
-#include "esp32h2/rom/rtc.h"
-#include "esp32h2/rom/uart.h"
-#include "esp32h2/rom/gpio.h"
+#include "esp32h4/rom/ets_sys.h"
+#include "esp32h4/rom/rtc.h"
+#include "esp32h4/rom/uart.h"
+#include "esp32h4/rom/gpio.h"
 #include "soc/rtc.h"
 #include "soc/io_mux_reg.h"
 #include "hal/clk_tree_ll.h"
@@ -61,7 +61,7 @@ void rtc_clk_32k_enable_external(void)
 
 void rtc_clk_32k_bootstrap(uint32_t cycle)
 {
-    /* No special bootstrapping needed for ESP32-H2, 'cycle' argument is to keep the signature
+    /* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature
      * same as for the ESP32. Just enable the XTAL here.
      */
     (void)cycle;

components/esp_hw_support/port/esp32h4/rtc_clk_init.c

@@ -9,10 +9,10 @@
 #include <stddef.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32h2/rom/ets_sys.h"
-#include "esp32h2/rom/rtc.h"
-#include "esp32h2/rom/uart.h"
-#include "esp32h2/rom/gpio.h"
+#include "esp32h4/rom/ets_sys.h"
+#include "esp32h4/rom/rtc.h"
+#include "esp32h4/rom/uart.h"
+#include "esp32h4/rom/gpio.h"
 #include "soc/rtc.h"
 #include "soc/rtc_periph.h"
 #include "soc/rtc_cntl_reg.h"
@@ -38,9 +38,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
      * - CK8M_DFREQ value controls tuning of 8M clock.
      *   CLK_8M_DFREQ constant gives the best temperature characteristics.
      */
-#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
     REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
-#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
 #endif
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);

components/esp_hw_support/port/esp32h4/rtc_init.c

@@ -81,10 +81,10 @@ void rtc_init(rtc_config_t cfg)
             SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
         }
 
-#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
         CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
         CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU);
-#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
         CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
         CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
 #endif

components/esp_hw_support/port/esp32h4/rtc_pm.c

@@ -44,7 +44,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
 
     switch (sleep_mode) {
     case PM_LIGHT_SLEEP:
-        // cfg.wifi_pd_en = 1; // ESP32-H2 TO-DO: IDF-3693
+        // cfg.wifi_pd_en = 1; // ESP32-H4 TO-DO: IDF-3693
         cfg.dig_dbias_wak = 4;
         cfg.dig_dbias_slp = 0;
         cfg.rtc_dbias_wak = 0;

components/esp_hw_support/port/esp32h4/rtc_sleep.c

@@ -16,8 +16,8 @@
 #include "soc/fe_reg.h"
 #include "soc/timer_group_reg.h"
 #include "soc/system_reg.h"
-#include "esp32h2/rom/ets_sys.h"
-#include "esp32h2/rom/rtc.h"
+#include "esp32h4/rom/ets_sys.h"
+#include "esp32h4/rom/rtc.h"
 #include "regi2c_ctrl.h"
 #include "soc/regi2c_bias.h"
 #include "soc/regi2c_ulp.h"
@@ -26,10 +26,10 @@
 #include "esp_hw_log.h"
 #include "esp_rom_uart.h"
 
-#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
 #define RTC_CNTL_DIG_REGULATOR_REG1  RTC_CNTL_DIG_REGULATOR_REG
 #define RTC_CNTL_DIG_REGULATOR_REG2  RTC_CNTL_DIG_REGULATOR_REG
-#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
 #define RTC_CNTL_DIG_REGULATOR_REG1  RTC_CNTL_DIGULATOR_REG
 #define RTC_CNTL_DIG_REGULATOR_REG2  RTC_CNTL_REG
 #define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG  RTC_CNTL_DIGULATOR1_DBIAS_REG
@@ -244,7 +244,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
 
-    // ESP32-H2 TO-DO: IDF-3693
+    // ESP32-H4 TO-DO: IDF-3693
     if (cfg.deep_slp) {
         // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
         // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);

components/esp_hw_support/port/esp32h4/rtc_time.c

@@ -5,7 +5,7 @@
  */
 
 #include <stdint.h>
-#include "esp32h2/rom/ets_sys.h"
+#include "esp32h4/rom/ets_sys.h"
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "hal/clk_tree_ll.h"
@@ -32,7 +32,7 @@
  */
 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
 {
-    /* On ESP32H2, choosing RTC_CAL_RTC_MUX results in calibration of
+    /* On ESP32H4, choosing RTC_CAL_RTC_MUX results in calibration of
      * the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
      * On the ESP32, it used the currently selected SLOW_CLK.
      * The following code emulates ESP32 behavior:

components/esp_hw_support/sdkconfig.rename.esp32h2

@@ -1,7 +0,0 @@
-# sdkconfig replacement configurations for deprecated options formatted as
-# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
-
-CONFIG_ESP32H2_RTC_CLK_SRC_INT_RC                         CONFIG_RTC_CLK_SRC_INT_RC
-CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS                       CONFIG_RTC_CLK_SRC_EXT_CRYS
-CONFIG_ESP32H2_RTC_CLK_SRC_EXT_OSC                        CONFIG_RTC_CLK_SRC_EXT_OSC
-CONFIG_ESP32H2_RTC_CLK_CAL_CYCLES                         CONFIG_RTC_CLK_CAL_CYCLES

components/esp_hw_support/sleep_gpio.c

@@ -105,7 +105,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
 #endif // SOC_GPIO_SUPPORT_SLP_SWITCH
 
 // TODO: IDF-6051, IDF-6052
-#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
+#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
 IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
 {
     gpio_hal_context_t gpio_hal = {

components/esp_hw_support/sleep_modes.c

@@ -71,9 +71,9 @@
 #include "esp32c3/rom/rtc.h"
 #include "soc/extmem_reg.h"
 #include "esp_private/sleep_mac_bb.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/cache.h"
-#include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rom/cache.h"
+#include "esp32h4/rom/rtc.h"
 #include "soc/extmem_reg.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/cache.h"
@@ -106,7 +106,7 @@
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (105)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (37)
-#elif CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32H4
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (105)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (37)
 #elif CONFIG_IDF_TARGET_ESP32C2
@@ -510,7 +510,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     uint32_t result;
     if (deep_sleep) {
 // TODO: IDF-6051, IDF-6052
-#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
+#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
         esp_sleep_isolate_digital_gpio();
 #endif
 

components/esp_hw_support/test/test_rtc_clk.c

@@ -40,9 +40,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rtc.h"
 #include "esp32c3/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rtc.h"
-#include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rtc.h"
+#include "esp32h4/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rtc.h"
 #include "esp32c2/rom/rtc.h"