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fix(mpll): fix mpll calibration fail bug

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This commit is contained in:
Armando (Dou Yiwen)
2026-08-12 13:33:08 +08:00
parent c80598ef7f
commit 5af18cd40b
6 changed files with 92 additions and 10 deletions
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components/esp_hw_support/port/esp32p4/pmu_init.c
+9
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@@ -18,6 +18,9 @@
#include "pmu_param.h"
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_mpll.h"
#include "soc/regi2c_bias.h"
#include "hal/regi2c_ctrl_ll.h"
#include "soc/lp_system_reg.h"
#include "regi2c_ctrl.h"
#include "esp_rom_sys.h"
@@ -212,4 +215,10 @@ void pmu_init(void)
// For PVT func taking effect, need delay.
esp_rom_delay_us(1000);
#endif
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
REG_SET_BIT(PMU_RF_PWC_REG, PMU_MSPI_PHY_XPD);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 12);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
REGI2C_WRITE_MASK(I2C_MPLL, I2C_MPLL_IR_CAL_EXT_CAP, 3);
#endif
}
components/esp_hw_support/port/esp32p4/pmu_param.c
+1 -1
View File
@@ -53,7 +53,7 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param");
.clk_power = { \
.i2c_iso_en = 1, \
.i2c_retention = 1, \
.xpd_pll_i2c = 1, \
.xpd_pll_i2c = 0xf, \
.xpd_pll = 0 \
}, \
.xtal = { \
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+8 -1
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@@ -18,6 +18,7 @@
#include "soc/soc.h"
#include "soc/regi2c_syspll.h"
#include "soc/regi2c_cpll.h"
#include "soc/regi2c_mpll.h"
#include "soc/rtc.h"
#include "soc/cache_reg.h"
#include "soc/pau_reg.h"
@@ -486,6 +487,13 @@ SPM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
esp_rom_delay_us(DCDC_STARTUP_TIME_US);
}
pmu_sleep_shutdown_ldo();
} else if (s_mpll_freq_mhz_before_sleep) {
rtc_clk_mpll_enable();
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
_regi2c_ctrl_ll_master_enable_clock(true);
REGI2C_WRITE_MASK(I2C_MPLL, I2C_MPLL_IR_CAL_EXT_CAP, 3);
esp_rom_delay_us(10);
#endif
}
pmu_ll_imm_set_pad_slp_sel(&PMU, false);
@@ -495,7 +503,6 @@ SPM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
if (!dslp) {
if (s_mpll_freq_mhz_before_sleep) {
rtc_clk_mpll_enable();
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep, true);
#if CONFIG_SPIRAM
if (!s_pmu_sleep_regdma_backup_enabled) {
components/esp_hw_support/port/esp32p4/rtc_clk.c
+6 -7
View File
@@ -662,13 +662,12 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_
} else {
ANALOG_CLOCK_ENABLE();
}
/* MPLL calibration start */
regi2c_ctrl_ll_mpll_calibration_start();
clk_ll_mpll_set_config(mpll_freq, xtal_freq);
/* wait calibration done */
while(!regi2c_ctrl_ll_mpll_calibration_is_done());
/* MPLL calibration stop */
regi2c_ctrl_ll_mpll_calibration_stop();
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
clk_ll_mpll_set_config_v1(mpll_freq, xtal_freq);
#else
clk_ll_mpll_set_config_v3(mpll_freq, xtal_freq);
#endif
if (thread_safe) {
_regi2c_ctrl_ll_master_enable_clock(false);