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Merge branch 'fix/fix_sleep_exception_in_spi_flash_rom_impl_v6.0' into 'release/v6.0'

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fix(esp_hw_support): fix sleep exception in spi flash rom impl (v6.0)

See merge request espressif/esp-idf!46445
This commit is contained in:
Jiang Jiang Jian
2026-03-20 10:16:57 +08:00
parent 779fd7a52c 9ed0d4bc4e
commit 59a686ffac
13 changed files with 48 additions and 20 deletions
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components/esp_hw_support/sleep_modes.c
+3 -2
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@@ -555,6 +555,7 @@ static void s_do_deep_sleep_phy_callback(void)
#endif
static int s_cache_suspend_cnt = 0;
static uint32_t s_cache_state = 0;
// Must be called from critical sections.
static void FORCE_IRAM_ATTR suspend_cache(void) {
@@ -566,7 +567,7 @@ static void FORCE_IRAM_ATTR suspend_cache(void) {
// fully check the access to external memory, writeback & invalidate is needed here.
Cache_WriteBack_Invalidate_All(CACHE_MAP_MASK);
#endif
spi_flash_disable_cache(esp_cpu_get_core_id(), NULL);
spi_flash_disable_cache(esp_cpu_get_core_id(), &s_cache_state);
}
}
@@ -575,7 +576,7 @@ static void FORCE_IRAM_ATTR resume_cache(void) {
s_cache_suspend_cnt--;
assert(s_cache_suspend_cnt >= 0 && DRAM_STR("cache resume doesn't match suspend ops"));
if (s_cache_suspend_cnt == 0) {
spi_flash_restore_cache(esp_cpu_get_core_id(), 0);
spi_flash_restore_cache(esp_cpu_get_core_id(), s_cache_state);
}
}
components/esp_pm/test_apps/esp_pm/sdkconfig.ci.slp_iram_opt
+1
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@@ -2,3 +2,4 @@ CONFIG_PM_SLP_IRAM_OPT=y
CONFIG_PM_RTOS_IDLE_OPT=y
CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
CONFIG_SPI_FLASH_ROM_IMPL=y
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+2 -2
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@@ -139,8 +139,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );
PROVIDE( spi_flash_cache2phys = 0x400001ac );
PROVIDE( spi_flash_phys2cache = 0x400001b0 );
PROVIDE( spi_flash_disable_cache = 0x400001b4 );
PROVIDE( spi_flash_restore_cache = 0x400001b8 );
PROVIDE( rom_spi_flash_disable_cache = 0x400001b4 );
PROVIDE( rom_spi_flash_restore_cache = 0x400001b8 );
PROVIDE( spi_flash_cache_enabled = 0x400001bc );
PROVIDE( spi_flash_enable_cache = 0x400001c0 );
PROVIDE( spi_cache_mode_switch = 0x400001c4 );
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
+2 -2
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@@ -144,8 +144,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 );
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 );
PROVIDE( spi_flash_cache2phys = 0x400001bc );
PROVIDE( spi_flash_phys2cache = 0x400001c0 );
PROVIDE( spi_flash_disable_cache = 0x400001c4 );
PROVIDE( spi_flash_restore_cache = 0x400001c8 );
PROVIDE( rom_spi_flash_disable_cache = 0x400001c4 );
PROVIDE( rom_spi_flash_restore_cache = 0x400001c8 );
PROVIDE( spi_flash_cache_enabled = 0x400001cc );
PROVIDE( spi_flash_enable_cache = 0x400001d0 );
PROVIDE( spi_cache_mode_switch = 0x400001d4 );
components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x40000204;
spi_flash_restore_cache = 0x40000208;
rom_spi_flash_disable_cache = 0x40000204;
rom_spi_flash_restore_cache = 0x40000208;
spi_flash_cache_enabled = 0x4000020c;
spi_flash_enable_cache = 0x40000210;
esp_enable_cache_flash_wrap = 0x40000214;
components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x400001f0;
spi_flash_restore_cache = 0x400001f4;
rom_spi_flash_disable_cache = 0x400001f0;
rom_spi_flash_restore_cache = 0x400001f4;
spi_flash_cache_enabled = 0x400001f8;
esp_enable_cache_flash_wrap = 0x40000200;
components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x40000204;
spi_flash_restore_cache = 0x40000208;
rom_spi_flash_disable_cache = 0x40000204;
rom_spi_flash_restore_cache = 0x40000208;
spi_flash_cache_enabled = 0x4000020c;
spi_flash_enable_cache = 0x40000210;
esp_enable_cache_flash_wrap = 0x40000214;
components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x400001e8;
spi_flash_restore_cache = 0x400001ec;
rom_spi_flash_disable_cache = 0x400001e8;
rom_spi_flash_restore_cache = 0x400001ec;
spi_flash_cache_enabled = 0x400001f0;
esp_enable_cache_flash_wrap = 0x400001f8;
components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x400001e8;
spi_flash_restore_cache = 0x400001ec;
rom_spi_flash_disable_cache = 0x400001e8;
rom_spi_flash_restore_cache = 0x400001ec;
spi_flash_cache_enabled = 0x400001f0;
spi_flash_enable_cache = 0x400001f4;
esp_enable_cache_flash_wrap = 0x400001f8;
components/esp_rom/esp32h4/ld/esp32h4.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
spi_flash_disable_cache = 0x400001f8;
spi_flash_restore_cache = 0x400001fc;
rom_spi_flash_disable_cache = 0x400001f8;
rom_spi_flash_restore_cache = 0x400001fc;
spi_flash_cache_enabled = 0x40000200;
spi_flash_enable_cache = 0x40000204;
esp_enable_cache_flash_wrap = 0x40000208;
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+2 -2
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@@ -196,8 +196,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x40000bdc );
PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 );
PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); /* patched when XIP */
PROVIDE( spi_flash_phys2cache = 0x40000c00 ); /* patched when XIP */
PROVIDE( spi_flash_disable_cache = 0x40000c0c );
PROVIDE( spi_flash_restore_cache = 0x40000c18 );
PROVIDE( rom_spi_flash_disable_cache = 0x40000c0c );
PROVIDE( rom_spi_flash_restore_cache = 0x40000c18 );
PROVIDE( spi_flash_cache_enabled = 0x40000c24 );
PROVIDE( spi_flash_enable_cache = 0x40000c30 );
PROVIDE( spi_cache_mode_switch = 0x40000c3c );
components/esp_rom/patches/esp_rom_spiflash.c
+24
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@@ -13,6 +13,9 @@
#include "soc/spi_mem_reg.h"
#endif
#if SOC_BRANCH_PREDICTOR_SUPPORTED
#include "riscv/rv_utils.h"
#endif
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
@@ -806,3 +809,24 @@ void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
}
#endif // IDF_TARGET
#if CONFIG_SPI_FLASH_ROM_IMPL
extern void rom_spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
#if SOC_BRANCH_PREDICTOR_SUPPORTED
//branch predictor will start cache request as well
rv_utils_dis_branch_predictor();
#endif
rom_spi_flash_disable_cache(cpuid, saved_state);
}
extern void rom_spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
rom_spi_flash_restore_cache(cpuid, saved_state);
#if SOC_BRANCH_PREDICTOR_SUPPORTED
rv_utils_en_branch_predictor();
#endif
}
#endif
components/spi_flash/cache_utils.c
+2
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@@ -336,6 +336,7 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
#endif
}
#if !CONFIG_SPI_FLASH_ROM_IMPL
void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
#if SOC_BRANCH_PREDICTOR_SUPPORTED
@@ -357,6 +358,7 @@ bool IRAM_ATTR spi_flash_cache_enabled(void)
{
return cache_hal_is_cache_enabled(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
#endif
#if CONFIG_IDF_TARGET_ESP32S2
IRAM_ATTR void esp_config_instruction_cache_mode(void)