diff --git a/components/bt/controller/esp32/bt.c b/components/bt/controller/esp32/bt.c
index 1e06d46246f..ad2e88d6b07 100644
--- a/components/bt/controller/esp32/bt.c
+++ b/components/bt/controller/esp32/bt.c
@@ -47,6 +47,7 @@
 
 #include "esp_rom_sys.h"
 #include "hli_api.h"
+#include "esp_private/sleep_modem.h"
 
 #if CONFIG_BLE_LOG_ENABLED
 #include "ble_log.h"
@@ -1692,7 +1693,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 
     ESP_LOGI(BTDM_LOG_TAG, "BT controller compile version [%s]", btdm_controller_get_compile_version());
 
-    esp_phy_modem_init();
+    esp_phy_modem_init(SLEEP_MODEM_BT);
 
     esp_bt_power_domain_on();
 
@@ -1867,7 +1868,7 @@ static void bt_controller_deinit_internal(void)
 
     esp_bt_power_domain_off();
 
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
 }
 
 static void bt_controller_shutdown(void* arg)
diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c
index d7fb87eb60b..185a04a3c8b 100644
--- a/components/bt/controller/esp32c2/bt.c
+++ b/components/bt/controller/esp32c2/bt.c
@@ -48,9 +48,7 @@
 #include "esp_private/esp_clk_tree_common.h"
 #include "bt_osi_mem.h"
 
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_modem.h"
-#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/esp_modem_clock.h"
 
 #include "freertos/FreeRTOS.h"
@@ -957,7 +955,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 
     os_msys_init();
 
-    esp_phy_modem_init();
+    esp_phy_modem_init(SLEEP_MODEM_BT);
     periph_module_enable(PERIPH_BT_MODULE);
     periph_module_reset(PERIPH_BT_MODULE);
 
@@ -1037,7 +1035,7 @@ controller_init_err:
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     ble_controller_deinit();
 modem_deint:
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
     periph_module_disable(PERIPH_BT_MODULE);
 
 free_mem:
@@ -1077,7 +1075,7 @@ esp_err_t esp_bt_controller_deinit(void)
 
     npl_freertos_mempool_deinit();
 
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
 
     ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
 
diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c
index 72c02864934..b3aa280660b 100644
--- a/components/bt/controller/esp32c3/bt.c
+++ b/components/bt/controller/esp32c3/bt.c
@@ -62,6 +62,8 @@
 #endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
 #include "esp_rom_gpio.h"
 #if CONFIG_BT_ENABLED
+#include "esp_private/sleep_modem.h"
+
 
 /* Macro definition
  ************************************************************************
@@ -1850,7 +1852,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #if CONFIG_MAC_BB_PD
     esp_mac_bb_pd_mem_init();
 #endif
-    esp_phy_modem_init();
+    esp_phy_modem_init(SLEEP_MODEM_BT);
     esp_bt_power_domain_on();
 
     btdm_controller_mem_init();
@@ -2049,7 +2051,7 @@ static void bt_controller_deinit_internal(void)
 #if CONFIG_MAC_BB_PD
     esp_mac_bb_pd_mem_deinit();
 #endif
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
 
 #if CONFIG_BT_CTRL_LE_LOG_EN
     esp_bt_controller_log_deinit();
diff --git a/components/bt/controller/esp32c5/bt.c b/components/bt/controller/esp32c5/bt.c
index 9cbc5830b79..40a1980de4a 100644
--- a/components/bt/controller/esp32c5/bt.c
+++ b/components/bt/controller/esp32c5/bt.c
@@ -44,8 +44,8 @@
 #include "soc/regdma.h"
 #include "bt_osi_mem.h"
 
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_modem.h"
+#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_retention.h"
 #include "esp_private/pm_impl.h"
 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
@@ -1041,7 +1041,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
     modem_clock_module_mac_reset(PERIPH_BT_MODULE);
     /* Select slow clock source for BT momdule */
     ble_rtc_clk_init(cfg);
-    esp_phy_modem_init();
+    esp_phy_modem_init(SLEEP_MODEM_BT);
 
     if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
@@ -1136,7 +1136,7 @@ modem_deint:
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     esp_bt_controller_log_deinit();
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
@@ -1161,7 +1161,7 @@ esp_err_t esp_bt_controller_deinit(void)
 
     os_msys_deinit();
 
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c
index 56f38faf548..b7a1ff7f9b4 100644
--- a/components/bt/controller/esp32c6/bt.c
+++ b/components/bt/controller/esp32c6/bt.c
@@ -45,8 +45,8 @@
 #include "esp_private/esp_clk_tree_common.h"
 #include "bt_osi_mem.h"
 
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_modem.h"
+#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_retention.h"
 #include "esp_private/pm_impl.h"
 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
@@ -1121,7 +1121,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
     modem_clock_module_mac_reset(PERIPH_BT_MODULE);
     /* Select slow clock source for BT momdule */
     ble_rtc_clk_init(cfg);
-    esp_phy_modem_init();
+    esp_phy_modem_init(SLEEP_MODEM_BT);
 
     if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
@@ -1219,7 +1219,7 @@ modem_deint:
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     esp_bt_controller_log_deinit();
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
@@ -1244,7 +1244,7 @@ esp_err_t esp_bt_controller_deinit(void)
 
     os_msys_deinit();
 
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_BT);
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
diff --git a/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c b/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c
index b526ff00d21..46cf5dded9b 100644
--- a/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c
+++ b/components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c
@@ -19,9 +19,9 @@
 #include "esp_pm.h"
 #endif
 
+#include "esp_private/sleep_modem.h"
 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/pm_impl.h"
-#include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 #endif
 #include "soc/rtc.h"
@@ -455,7 +455,9 @@ btdm_lp_reset(bool enable_stage)
 #if CONFIG_PM_ENABLE
         esp_pm_lock_acquire(s_pm_lock);
 #endif // CONFIG_PM_ENABLE
-
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+        esp_phy_modem_init(SLEEP_MODEM_BT);
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
         esp_phy_enable(PHY_MODEM_BT);
 #if CONFIG_IDF_TARGET_ESP32H4
         // TODO: Need to be deleted.
@@ -468,6 +470,9 @@ btdm_lp_reset(bool enable_stage)
         esp_btbb_disable();
         if (s_bt_active) {
             esp_phy_disable(PHY_MODEM_BT);
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+            esp_phy_modem_deinit(SLEEP_MODEM_BT);
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 #if CONFIG_PM_ENABLE
             esp_pm_lock_release(s_pm_lock);
 #endif // CONFIG_PM_ENABLE
diff --git a/components/esp_hal_pmu/esp32c5/pau_hal.c b/components/esp_hal_pmu/esp32c5/pau_hal.c
index f627c746c34..c26d100473f 100644
--- a/components/esp_hal_pmu/esp32c5/pau_hal.c
+++ b/components/esp_hal_pmu/esp32c5/pau_hal.c
@@ -15,14 +15,26 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
     pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]);
 }
 
-void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_regdma_wait_done(pau_hal_context_t *hal)
+{
+    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+}
+
+void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
-    pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC);
+    pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_PHY);
     pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
+}
+
+bool IRAM_ATTR pau_hal_get_regdma_done_status(pau_hal_context_t *hal)
+{
+    return (pau_ll_get_regdma_intr_status(hal->dev) & 0x1);
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
@@ -33,14 +45,16 @@ void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
 }
 
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
-void IRAM_ATTR pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
     pau_ll_set_regdma_select_wifimac_link(hal->dev);
     pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_wifimac_link(pau_hal_context_t *hal)
diff --git a/components/esp_hal_pmu/esp32c6/pau_hal.c b/components/esp_hal_pmu/esp32c6/pau_hal.c
index ac9e4a0759e..469f5a9c222 100644
--- a/components/esp_hal_pmu/esp32c6/pau_hal.c
+++ b/components/esp_hal_pmu/esp32c6/pau_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,14 +18,26 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
      * REGDMA link 3 */
 }
 
-void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_regdma_wait_done(pau_hal_context_t *hal)
+{
+    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+}
+
+void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
     pau_ll_set_regdma_select_wifimac_link(hal->dev);
     pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
+}
+
+bool IRAM_ATTR pau_hal_get_regdma_done_status(pau_hal_context_t *hal)
+{
+    return (pau_ll_get_regdma_intr_status(hal->dev) & 0x1);
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
diff --git a/components/esp_hal_pmu/esp32c61/pau_hal.c b/components/esp_hal_pmu/esp32c61/pau_hal.c
index 69e5323b993..273ca6b7ed5 100644
--- a/components/esp_hal_pmu/esp32c61/pau_hal.c
+++ b/components/esp_hal_pmu/esp32c61/pau_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,14 +18,26 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
      * REGDMA link 3 */
 }
 
-void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_regdma_wait_done(pau_hal_context_t *hal)
+{
+    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+}
+
+void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
     pau_ll_set_regdma_select_wifimac_link(hal->dev);
     pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
+}
+
+bool IRAM_ATTR pau_hal_get_regdma_done_status(pau_hal_context_t *hal)
+{
+    return (pau_ll_get_regdma_intr_status(hal->dev) & 0x1);
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
diff --git a/components/esp_hal_pmu/esp32p4/pau_hal.c b/components/esp_hal_pmu/esp32p4/pau_hal.c
index 963e6e7228f..8d991551fe9 100644
--- a/components/esp_hal_pmu/esp32p4/pau_hal.c
+++ b/components/esp_hal_pmu/esp32p4/pau_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,14 +26,21 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
     lp_sys_ll_set_pau_link_addr((uint32_t)(*link_addr)[0]);
 }
 
-void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_regdma_wait_done(pau_hal_context_t *hal)
+{
+    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+}
+
+void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
     pau_ll_set_regdma_select_wifimac_link(hal->dev);
     pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
diff --git a/components/esp_hal_pmu/esp32s31/pau_hal.c b/components/esp_hal_pmu/esp32s31/pau_hal.c
index 2cc34821e10..682d85b3541 100644
--- a/components/esp_hal_pmu/esp32s31/pau_hal.c
+++ b/components/esp_hal_pmu/esp32s31/pau_hal.c
@@ -15,14 +15,26 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
     lp_sys_ll_set_pau_link_addr((uint32_t)(*link_addr)[0]);
 }
 
-void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_regdma_wait_done(pau_hal_context_t *hal)
+{
+    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+}
+
+void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
-    pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC);
+    pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_PHY);
     pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
+}
+
+bool IRAM_ATTR pau_hal_get_regdma_done_status(pau_hal_context_t *hal)
+{
+    return (pau_ll_get_regdma_intr_status(hal->dev) & 0x1);
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
@@ -33,14 +45,16 @@ void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
 }
 
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
-void IRAM_ATTR pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore)
+void IRAM_ATTR pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking)
 {
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
     pau_ll_set_regdma_select_wifimac_link(hal->dev);
     pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
     pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
 
-    while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
+    if (blocking) {
+        pau_hal_regdma_wait_done(hal);
+    }
 }
 
 void IRAM_ATTR pau_hal_stop_regdma_wifimac_link(pau_hal_context_t *hal)
diff --git a/components/esp_hal_pmu/include/hal/pau_hal.h b/components/esp_hal_pmu/include/hal/pau_hal.h
index 60b5c129599..2494c0e7bf6 100644
--- a/components/esp_hal_pmu/include/hal/pau_hal.h
+++ b/components/esp_hal_pmu/include/hal/pau_hal.h
@@ -36,8 +36,8 @@ typedef struct {
  */
 void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr);
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
 /**
  * @brief Set regdma modem link address
  *
@@ -47,13 +47,21 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
 #define pau_hal_set_regdma_modem_link_addr(hal, addr)   pau_ll_set_regdma_wifimac_link_addr((hal)->dev, (addr))
 #endif
 
+/**
+ * @brief Wait until regdma completes
+ *
+ * @param hal           regdma hal context
+ */
+void pau_hal_regdma_wait_done(pau_hal_context_t *hal);
+
 /**
  * @brief Start transmission on regdma modem link
  *
  * @param hal           regdma hal context
  * @param backup_or_restore        false:restore true:backup
+ * @param blocking                 software wait till regdma completes
  */
-void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore);
+void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking);
 
 /**
  * @brief Stop transmission on regdma modem link
@@ -68,8 +76,9 @@ void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal);
  *
  * @param hal           regdma hal context
  * @param backup_or_restore        false: restore, true: backup
+ * @param blocking                 software wait till regdma completes
  */
-void pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore);
+void pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_restore, bool blocking);
 
 /**
  * @brief Stop transmission on regdma WiFi MAC SEL link
@@ -78,6 +87,33 @@ void pau_hal_start_regdma_wifimac_link(pau_hal_context_t *hal, bool backup_or_re
  */
 void pau_hal_stop_regdma_wifimac_link(pau_hal_context_t *hal);
 #endif
+/**
+ * @brief Enable regdma done interrupt
+ *
+ * @param hal            regdma hal context
+ */
+#define pau_hal_regdma_done_int_enable(hal)    pau_ll_set_regdma_backup_done_intr_enable((hal)->dev, true)
+
+/**
+ * @brief Disable regdma done interrupt
+ *
+ * @param hal            regdma hal context
+ */
+#define pau_hal_regdma_done_int_disable(hal)    pau_ll_set_regdma_backup_done_intr_enable((hal)->dev, false)
+
+/**
+ * @brief Get regdma done interrupt status
+ *
+ * @param hal            regdma hal context
+ */
+bool pau_hal_get_regdma_done_status(pau_hal_context_t *hal);
+
+/**
+ * @brief Clear regdma done interrupt status
+ *
+ * @param hal            regdma hal context
+ */
+#define pau_hal_clear_regdma_backup_done_intr_state(hal)    pau_ll_clear_regdma_backup_done_intr_state((hal)->dev)
 #endif
 
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
diff --git a/components/esp_hw_support/include/esp_private/esp_pau.h b/components/esp_hw_support/include/esp_private/esp_pau.h
index 89b628affa9..2a4e8a78bcf 100644
--- a/components/esp_hw_support/include/esp_private/esp_pau.h
+++ b/components/esp_hw_support/include/esp_private/esp_pau.h
@@ -25,36 +25,73 @@ extern "C" {
  */
 void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries);
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
 /**
- * @brief Set the address of WiFi MAC REGDMA Link in modem state
+ * @brief Set the address of modem REGDMA Link in modem state
  * @param link_addr linked lists address
  */
 void pau_regdma_set_modem_link_addr(void *link_addr);
+#endif // SOC_PM_PAU_REGDMA_LINK_MODEM
 
 /**
  * @brief Software trigger regdma to perform modem link backup
+ *
+ * @param blocking software waits for regdma to complete
  */
-void pau_regdma_trigger_modem_link_backup(void);
+void pau_regdma_trigger_modem_link_backup(bool blocking);
 
 /**
  * @brief Software trigger regdma to perform modem link restore
+ *
+ * @param blocking software waits for regdma to complete
  */
-void pau_regdma_trigger_modem_link_restore(void);
+void pau_regdma_trigger_modem_link_restore(bool blocking);
+
+/**
+ * @brief Completion process of regdma for modem link retention
+ *
+ */
+void pau_regdma_modem_link_complete(void);
 
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
 /**
  * @brief Software trigger REGDMA backup on WiFi MAC SEL link
  */
-void pau_regdma_trigger_wifimac_link_backup(void);
+void pau_regdma_trigger_wifimac_link_backup(bool blocking);
 
 /**
  * @brief Software trigger REGDMA restore on WiFi MAC SEL link
  */
-void pau_regdma_trigger_wifimac_link_restore(void);
-#endif
+void pau_regdma_trigger_wifimac_link_restore(bool blocking);
 #endif
 
+/**
+ * @brief Enable pau done interrupt
+ *
+ */
+void pau_regdma_done_int_enable(void);
+
+/**
+ * @brief Disable pau done interrupt
+ *
+ */
+void pau_regdma_done_int_disable(void);
+
+/**
+ * @brief Check pau done interrupt status
+ *
+ */
+bool pau_get_regdma_done_status(void);
+
+/**
+ * @brief Clear pau done interrupt status
+ *
+ */
+void pau_clear_regdma_done_status(void);
+
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
+
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
 /**
  * @brief Set the address of system REGDMA Link in active state
@@ -101,6 +138,25 @@ void pau_regdma_trigger_extra_link_restore(void);
 bool pau_regdma_enable_aon_link_entry(bool enable);
 #endif
 
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+/**
+ * @brief Callback function type for modem link protect.
+ *
+ */
+typedef void (* pau_regdma_modem_link_protect_cb_t)(bool protect);
+
+/**
+ * @brief Register the modem link trigger hook callback function
+ * @param cb the callback function
+ */
+void pau_regdma_register_modem_link_protect(pau_regdma_modem_link_protect_cb_t cb);
+
+/**
+ * @brief Unregister the modem link trigger hook callback function
+ */
+void pau_regdma_unregister_modem_link_protect(void);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/include/esp_private/sleep_modem.h b/components/esp_hw_support/include/esp_private/sleep_modem.h
index 47ad7548e6e..2430d3f9ce6 100644
--- a/components/esp_hw_support/include/esp_private/sleep_modem.h
+++ b/components/esp_hw_support/include/esp_private/sleep_modem.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,11 +10,24 @@
 #include "sdkconfig.h"
 #include "esp_err.h"
 #include "esp_sleep.h"
+#include "esp_attr.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#define SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION    (BIT(0))
+#define SLEEP_MODEM_SKIP_WIFI_RETENTION           (BIT(1))
+#define SLEEP_MODEM_RESET_RETENTION               (0)
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+typedef enum {
+    SLEEP_MODEM_WIFI       = 1,
+    SLEEP_MODEM_BT         = 2,
+    SLEEP_MODEM_IEEE802154 = 4,
+} sleep_modem_type_t;
+#define SLEEP_MODEM_MAX_CNT 3
+
 /**
  * @file sleep_modem.h
  *
@@ -77,31 +90,36 @@ void sleep_modem_mac_bb_power_down_prepare(void);
 void sleep_modem_mac_bb_power_up_prepare(void);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+/**
+ * @brief Phy retention completes
+ *
+ */
+void sleep_modem_phy_retention_complete(void);
 
 /**
- * @brief The retention action in the modem state of WiFi PHY module
+ * @brief The retention action of PHY module
  *
  * @param restore  true for restore the PHY context, false for backup the PHY context
- * @param wifimac_link_is_sel  true to trigger REGDMA via WiFi MAC link
+ * @param flags Configure flags for phy link
  */
-void sleep_modem_wifi_do_phy_retention(bool restore, bool wifimac_link_is_sel);
+void sleep_modem_do_phy_retention(bool restore, bool wifimac_link_is_sel, uint8_t flags);
 
 /**
- * @brief Get WiFi modem state
+ * @brief Get phy link state
  *
- * @return true or false for WiFi modem state is enabled or disabled
+ * @return true or false for phy link is enabled or disabled
  */
-bool sleep_modem_wifi_modem_state_enabled(void);
+bool sleep_modem_phy_link_enabled(void);
 
 /**
- * @brief Get WiFi modem link done state
+ * @brief Get phy link done state
  *
- * @return true or false for WiFi modem link can be used to enable RF by REGDMA or can not be used
+ * @return true or false for phy link can be used to enable RF by REGDMA or can not be used
  */
-bool sleep_modem_wifi_modem_link_done(void);
+bool sleep_modem_phy_link_done(void);
 
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 
 /**
  * @brief Whether the current target allows Modem or the TOP power domain to be powered off during light sleep
@@ -199,23 +217,36 @@ void esp_pm_register_light_sleep_default_params_config_callback(update_light_sle
  */
 void esp_pm_unregister_light_sleep_default_params_config_callback(void);
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 /**
- * @brief Init Wi-Fi modem state.
+ * @brief Init phy link.
  *
- * This function init wifi modem state.
-  * @return
-  *   - ESP_OK on success
-  *   - ESP_ERR_NO_MEM if no memory for link
+ * This function init phy link.
+ *
+ * @param modem_mask bit mask of modems
+ * @return
+ *    - ESP_OK on success
+ *    - ESP_ERR_NO_MEM if no memory for link
  */
-esp_err_t sleep_modem_wifi_modem_state_init(void);
+esp_err_t sleep_modem_phy_init(sleep_modem_type_t modem_mask);
 
 /**
- * @brief  Deinit Wi-Fi modem state.
+ * @brief Deinit phy link.
  *
- * This function deinit wifi modem state.
+ * This function deinit phy link.
+ *
+ * @param modem_mask bit mask of modems
  */
-void sleep_modem_wifi_modem_state_deinit(void);
+void sleep_modem_phy_deinit(sleep_modem_type_t modem_mask);
+
+/**
+ * @brief Check if Wi-Fi modem state is enabled
+ *
+ * @return
+ *  - true Wi-Fi modem state is enabled
+ *  - false Wi-Fi modem state is disabled
+ */
+bool sleep_modem_wifi_modem_state_is_enabled(void);
 
 /**
  * @brief Function to check Wi-Fi modem state to skip light sleep.
@@ -228,33 +259,33 @@ void sleep_modem_wifi_modem_state_deinit(void);
 bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
 
 /**
- * @brief Function to initialize and create the modem state phy link
- * @param link_head the pointer that point to the head of the created phy link
+ * @brief Function to initialize and create the phy link
+ * @param link_context PHY link regdma description conteoxt pointer
  * @return
  *   - ESP_OK on success
  *   - ESP_ERR_NO_MEM if no memory for link
  *   - ESP_ERR_INVALID_ARG if value is out of range
  *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
  */
-esp_err_t sleep_modem_state_phy_link_init(void **link_head);
+esp_err_t sleep_phy_link_init(void **link_context);
 
 /**
- * @brief Function to destroy and de-initialize modem state phy link
- * @param link_head the phy link head will be destroyed
+ * @brief Function to destroy and de-initialize phy link
+ * @param link_context PHY link regdma description conteoxt pointer
  * @return
  *   - ESP_OK on success
  *   - ESP_ERR_INVALID_ARG if value is out of range
  *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
  */
-esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
+esp_err_t sleep_phy_link_deinit(void *link_context);
 
 /**
  * @brief Function to configure PHY link regdma description at runtime
  * @param link_context PHY link regdma description conteoxt pointer
  * @param flags A bitmap to indicate the PHY link regdma description configuration flag
  */
-void sleep_modem_state_phy_link_config(void *link_context, uint32_t flags);
-#endif
+void sleep_phy_link_config(void *link_context, uint32_t flags);
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_hw_support/include/esp_private/sleep_retention.h b/components/esp_hw_support/include/esp_private/sleep_retention.h
index aed019c1202..d9a4e7f3bbc 100644
--- a/components/esp_hw_support/include/esp_private/sleep_retention.h
+++ b/components/esp_hw_support/include/esp_private/sleep_retention.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -340,7 +340,7 @@ void sleep_retention_do_extra_retention(bool backup_or_restore);
 void sleep_retention_do_system_retention(bool backup_or_restore);
 #endif
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 /**
  * @brief Software trigger REGDMA to do phy linked list retention
  *
@@ -348,9 +348,16 @@ void sleep_retention_do_system_retention(bool backup_or_restore);
  *                          or false for restore to register from memory
  * @param wifimac_link_is_sel true to use dedicated WiFi MAC link,
  *                             false to use modem entry link
+ * @param blocking Software wait for REGDMA to complete
  */
-void sleep_retention_do_phy_retention(bool backup_or_restore, bool wifimac_link_is_sel);
-#endif /*SOC_PM_SUPPORT_PMU_MODEM_STATE */
+void sleep_retention_do_phy_retention(bool backup_or_restore, bool wifimac_link_is_sel, bool blocking);
+
+/**
+ * @brief Completion process of REGDMA for PHY linked list retention
+ *
+ */
+void sleep_retention_phy_retention_complete(void);
+#endif /*SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 #endif // SOC_PAU_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt
index 46acd179560..f997c8b2666 100644
--- a/components/esp_hw_support/lowpower/CMakeLists.txt
+++ b/components/esp_hw_support/lowpower/CMakeLists.txt
@@ -46,8 +46,8 @@ if(CONFIG_BT_CTRL_SLEEP_ENABLE AND CONFIG_SOC_PM_MODEM_LOCK_CLK_WORKAROUND)
             APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u sleep_power_system_retention_init")
 endif()
 
-if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
-    list(APPEND srcs "port/${target}/sleep_modem_state.c")
+if(CONFIG_SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY)
+    list(APPEND srcs "port/${target}/sleep_phy.c")
 endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c
deleted file mode 100644
index 81d607ab9ac..00000000000
--- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "esp_log.h"
-#include "esp_check.h"
-#include "esp_attr.h"
-
-#include "soc/soc_caps.h"
-#include "soc/pmu_reg.h"
-
-#include "modem/i2c_ana_mst_reg.h"
-#include "modem/modem_syscon_reg.h"
-#include "modem/modem_lpcon_reg.h"
-
-#include "esp_private/sleep_modem.h"
-#include "esp_private/sleep_retention.h"
-
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
-
-#define SARADC_TSENS_REG                (0x6000e058)
-#define SARADC_TSENS_PU                 (BIT(22))
-#define PMU_RF_PWR_REG                  (0x600b0158)
-
-#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
-#define FECOEX_SET_CHAN_EN              (BIT(17))
-#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
-#define FECOEX_SET_CHAN_DONE            (BIT(8))
-#define FECOEX_AGC_CONF_REG             (0x600a7030)
-#define FECOEX_AGC_DIS                  (BIT(29))
-
-#define WDEVTXQ_BLOCK                   (0x600A4ca8)
-#define WDEV_RXBLOCK                    (BIT(12))
-#define MODEM_FE_DATA_BASE              (0x600a0400)
-#define MODEM_FE_CTRL_BASE              (0x600a0800)
-
-ESP_LOG_ATTR_TAG(TAG, "sleep");
-
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-
-typedef struct {
-#define DESC_IDX_I2C_MST_ENA (0)
-#define DESC_IDX_I2C_MST_DIS (1)
-    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
-} sleep_modem_state_phy_link_context_t;
-
-static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
-{
-    #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
-
-    static sleep_retention_entries_config_t wifi_modem_config[] = {
-        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
-
-        /* PMU or software to trigger enable RF PHY */
-        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
-        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xf3800000,                0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = WIFIMAC_ENTRY() },
-        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0), .owner = WIFIMAC_ENTRY() },
-        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
-        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
-        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = WIFIMAC_ENTRY() },
-        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = WIFIMAC_ENTRY() },
-        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
-
-        /* PMU to trigger enable RXBLOCK */
-        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = WIFIMAC_ENTRY() },
-
-        /* PMU or software to trigger disable RF PHY */
-        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
-        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = WIFIMAC_ENTRY() },
-        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1), .owner = WIFIMAC_ENTRY() },
-        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
-        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 1), .owner = WIFIMAC_ENTRY() },
-        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = WIFIMAC_ENTRY() },
-        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
-        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
-
-        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
-
-        /* PMU to trigger disable RXBLOCK */
-        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
-        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = WIFIMAC_ENTRY() },
-        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
-
-        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
-    };
-    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
-    wifi_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
-    wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
-    esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
-    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
-    return ESP_OK;
-}
-#endif
-
-esp_err_t sleep_modem_state_phy_link_init(void **link_head)
-{
-    esp_err_t err = ESP_OK;
-
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
-    err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
-    if (err == ESP_OK) {
-        err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
-        if (err == ESP_OK) {
-            const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x14) };
-            static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
-
-            for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
-                void *desc = sleep_retention_find_link_by_id(id_array[i]);
-                if (desc) {
-                    phy_link_context.regdma_desc[i] = desc;
-                } else {
-                    err = ESP_ERR_NOT_FOUND;
-                }
-            }
-            if (err == ESP_OK) {
-                *link_head = (void *)&phy_link_context;
-            }
-        }
-    }
-#endif
-    return err;
-}
-
-void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
-{
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
-
-    if (flags & BIT(0)) {
-        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
-        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], true, true);
-    } else {
-        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, false);
-        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], false, true);
-    }
-#endif
-}
-
-esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
-{
-    esp_err_t err = ESP_OK;
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
-    if (err == ESP_OK) {
-        sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
-    }
-#endif
-    return err;
-}
-
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_phy.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_phy.c
new file mode 100644
index 00000000000..07ae281b1da
--- /dev/null
+++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_phy.c
@@ -0,0 +1,178 @@
+/*
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_attr.h"
+
+#include "soc/soc_caps.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/i2c_ana_mst_reg.h"
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0158)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
+#define FECOEX_SET_CHAN_EN              (BIT(17))
+#define FECOEX_SET_FREQ_RESETN          (BIT(30))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+ESP_LOG_ATTR_TAG(TAG, "sleep");
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+
+typedef struct {
+#define DESC_IDX_I2C_MST_ENA (0)
+#define DESC_IDX_I2C_MST_DIS (1)
+#define DESC_IDX_SKIP_WIFI               (2)
+#define DESC_SKIP_WIFI_ENTRY_CNT         (4)
+#define DESC_SKIP_WIFI_RESTORE_ENTRY_CNT (1)
+    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1 + DESC_SKIP_WIFI_ENTRY_CNT];
+} sleep_phy_link_context_t;
+
+static esp_err_t sleep_phy_retention_init(void *arg)
+{
+    #define PHY_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_PHY))
+
+    static sleep_retention_entries_config_t phy_modem_config[] = {
+        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = PHY_ENTRY() }, /* I2C MST enable */
+
+        /* Reset SET_FREQ fsm */
+        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), FECOEX_SET_FREQ_SET_CHAN_REG,     0,    FECOEX_SET_FREQ_RESETN,                         1, 0), .owner = PHY_ENTRY() },
+        /* PMU or software to trigger enable RF PHY */
+        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = PHY_ENTRY() }, /* BBPLL calibration enable */
+        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf3800000,                0xf3800000, 1, 0), .owner = PHY_ENTRY() },
+        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = PHY_ENTRY() },
+        [5]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = PHY_ENTRY() },
+        [6]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0), .owner = PHY_ENTRY() },
+        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_FREQ_RESETN,    FECOEX_SET_FREQ_RESETN,    1, 0), .owner = PHY_ENTRY() },\
+        [8]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0), .owner = PHY_ENTRY() },
+        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0), .owner = PHY_ENTRY() },
+        [10]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = PHY_ENTRY() },
+        [11]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = PHY_ENTRY() },
+        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = PHY_ENTRY() },
+
+        /* PMU to trigger enable RXBLOCK */
+        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = PHY_ENTRY() },
+
+        /* PMU or software to trigger disable RF PHY */
+        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = PHY_ENTRY() },
+        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = PHY_ENTRY() },
+        [16] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1), .owner = PHY_ENTRY() },
+        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1), .owner = PHY_ENTRY() },
+        [18] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x12), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1), .owner = PHY_ENTRY() },
+        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = PHY_ENTRY() },
+        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), PMU_RF_PWR_REG,                   0,                         0xf3800000, 0, 1), .owner = PHY_ENTRY() },
+        [21] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = PHY_ENTRY() }, /* BBPLL calibration disable */
+
+        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = PHY_ENTRY() }, /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = PHY_ENTRY() },
+        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = PHY_ENTRY() },
+        [25] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = PHY_ENTRY() },
+
+        [26] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = PHY_ENTRY() },
+        [27] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = PHY_ENTRY() }
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    phy_modem_config[5].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    phy_modem_config[17].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    esp_err_t err = sleep_retention_entries_create(phy_modem_config, ARRAY_SIZE(phy_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link");
+    return ESP_OK;
+}
+#endif
+
+esp_err_t sleep_phy_link_init(void **link_context)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_phy_retention_init, .arg = NULL } } };
+    err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
+    if (err == ESP_OK) {
+        err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
+        if (err == ESP_OK) {
+            const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x16),                                              /* I2C MST CLK entries */
+                                     REGDMA_PHY_LINK(0x0d), REGDMA_PHY_LINK(0x17), REGDMA_PHY_LINK(0x18), REGDMA_PHY_LINK(0x19) /* WiFi Related entries */
+                                    };
+            static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
+
+            for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
+                void *desc = sleep_retention_find_link_by_id(id_array[i]);
+                if (desc) {
+                    phy_link_context.regdma_desc[i] = desc;
+                } else {
+                    err = ESP_ERR_NOT_FOUND;
+                }
+            }
+            if (err == ESP_OK) {
+                *link_context = (void *)&phy_link_context;
+            }
+        }
+    }
+    if (err != ESP_OK) {
+        sleep_phy_link_deinit(NULL);
+    }
+#endif
+    return err;
+}
+
+void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
+{
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
+
+    if (flags & SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION) {
+        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
+        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], true, true);
+    } else {
+        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, false);
+        regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], false, true);
+    }
+
+    if (flags & SLEEP_MODEM_SKIP_WIFI_RETENTION) {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, true);
+        }
+    } else {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            if (i < DESC_SKIP_WIFI_RESTORE_ENTRY_CNT) {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, false);
+            } else {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], false, true);
+            }
+        }
+    }
+#endif
+}
+
+esp_err_t sleep_phy_link_deinit(void *link_context)
+{
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+#endif
+    return ESP_OK;
+}
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
diff --git a/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c6/sleep_phy.c
similarity index 56%
rename from components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c
rename to components/esp_hw_support/lowpower/port/esp32c6/sleep_phy.c
index 410855a9d80..3d2e5ca55a1 100644
--- a/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c
+++ b/components/esp_hw_support/lowpower/port/esp32c6/sleep_phy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,13 +16,14 @@
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 
 #define SARADC_TSENS_REG                (0x6000e058)
 #define SARADC_TSENS_PU                 (BIT(22))
 #define PMU_RF_PWR_REG                  (0x600b0154)
 
 #define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
+#define FECOEX_SET_FREQ_RESETN          (BIT(30))
 #define FECOEX_SET_CHAN_EN              (BIT(14))
 #define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
 #define FECOEX_SET_CHAN_DONE            (BIT(8))
@@ -39,73 +40,79 @@ typedef struct {
 #define DESC_IDX_I2C_MST_ENA (0)
 #define DESC_IDX_I2C_MST_SEL (1)
 #define DESC_IDX_I2C_MST_DIS (2)
-    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
-} sleep_modem_state_phy_link_context_t;
+#define DESC_IDX_SKIP_WIFI               (3)
+#define DESC_SKIP_WIFI_ENTRY_CNT         (8)
+#define DESC_SKIP_WIFI_RESTORE_ENTRY_CNT (1)
+    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1 + DESC_SKIP_WIFI_ENTRY_CNT];
+} sleep_phy_link_context_t;
 
-esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+esp_err_t sleep_phy_link_init(void **link_context)
 {
     esp_err_t err = ESP_OK;
 
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
-    static regdma_link_config_t wifi_modem_config[] = {
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
+    static regdma_link_config_t phy_modem_config[] = {
         [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
         [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
 
         [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
         [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
 
+        /* Reset SET_FREQ fsm */
+        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), FECOEX_SET_FREQ_SET_CHAN_REG,     0,    FECOEX_SET_FREQ_RESETN,                         1, 0),
         /* PMU or software to trigger enable RF PHY */
-        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
-        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
-        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
-        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
-        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
-        [9]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
-        [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
-        [11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
-        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
-        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
-        [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
-        [15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
-        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
-        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
+        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
+        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
+        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
+        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
+        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x09), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
+        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_FREQ_RESETN,    FECOEX_SET_FREQ_RESETN,          1, 0),
+        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
+        [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
+        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [16] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0e), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [17] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0f), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
+        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
+        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
 
         /* PMU to trigger enable RXBLOCK */
-        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
+        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
 
         /* PMU or software to trigger disable RF PHY */
-        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
-        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
-        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
-        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
-        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
-        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
-        [25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
-        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
-        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
-        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
+        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
+        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
+        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
+        [24] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
+        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x17), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [26] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x18), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [27] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
+        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
+        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
+        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
 
-        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
+        [31] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1d), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
 
         /* PMU to trigger disable RXBLOCK */
-        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-        [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
-        [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [32] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1e), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [33] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1f), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [34] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x20), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [35] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x21), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
+        [36] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x22), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [37] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x23), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [38] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x24), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
 
-        [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
-        [38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
+        [39] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x25), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
+        [40] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x26), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
     };
     extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
-    wifi_modem_config[7].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
-    wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    phy_modem_config[8].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    phy_modem_config[24].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
 
     void *link = NULL;
-    for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
-        void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
+    for (int i = ARRAY_SIZE(phy_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
+        void *next = regdma_link_init_safe(&phy_modem_config[i], false, 0, link);
         if (next) {
             link = next;
         } else {
@@ -116,8 +123,11 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
     if (err == ESP_OK) {
         pau_regdma_set_modem_link_addr(link);
 
-        const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x01), REGDMA_PHY_LINK(0x1b) };
-        static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
+        const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x01), REGDMA_PHY_LINK(0x1d),                           /* I2C MST CLK entries */
+                                 REGDMA_PHY_LINK(0x12), REGDMA_PHY_LINK(0x1e), REGDMA_PHY_LINK(0x1f), REGDMA_PHY_LINK(0x20),
+                                 REGDMA_PHY_LINK(0x21), REGDMA_PHY_LINK(0x22), REGDMA_PHY_LINK(0x23), REGDMA_PHY_LINK(0x24)     /* WiFi Related entries */
+                                };
+        static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
 
         for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
             void *desc = regdma_find_link_by_id(link, 0, id_array[i]);
@@ -129,18 +139,20 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
         }
         if (err == ESP_OK) {
             phy_link_context.link_head = link;
-            *link_head = (void *)&phy_link_context;
+            *link_context = (void *)&phy_link_context;
+        } else {
+            regdma_link_destroy(link, 0);
         }
     }
 #endif
     return err;
 }
 
-void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
+void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
 {
-    sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
+    sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
 
-    if (flags & BIT(0)) {
+    if (flags & SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION) {
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_SEL], true, true);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], true, true);
@@ -149,14 +161,27 @@ void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t fl
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_SEL], true, false);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], false, true);
     }
+
+    if (flags & SLEEP_MODEM_SKIP_WIFI_RETENTION) {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, true);
+        }
+    } else {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            if (i < DESC_SKIP_WIFI_RESTORE_ENTRY_CNT) {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, false);
+            } else {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], false, true);
+            }
+        }
+    }
 }
 
-esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+esp_err_t sleep_phy_link_deinit(void *link_context)
 {
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
-    regdma_link_destroy(((sleep_modem_state_phy_link_context_t *)link_head)->link_head, 0);
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
+    regdma_link_destroy(((sleep_phy_link_context_t *)link_context)->link_head, 0);
 #endif
     return ESP_OK;
 }
-
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_phy.c
similarity index 52%
rename from components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c
rename to components/esp_hw_support/lowpower/port/esp32c61/sleep_phy.c
index 49a619a3fd6..cfcaf31fb50 100644
--- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c
+++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_phy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +16,7 @@
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 
 #define SARADC_TSENS_REG                (0x6000e058)
 #define SARADC_TSENS_PU                 (BIT(22))
@@ -24,6 +24,7 @@
 
 #define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
 #define FECOEX_SET_CHAN_EN              (BIT(17))
+#define FECOEX_SET_FREQ_RESETN          (BIT(30))
 #define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
 #define FECOEX_SET_CHAN_DONE            (BIT(8))
 #define FECOEX_AGC_CONF_REG             (0x600a7030)
@@ -36,71 +37,77 @@ typedef struct {
     void *link_head;
 #define DESC_IDX_I2C_MST_ENA (0)
 #define DESC_IDX_I2C_MST_DIS (1)
-    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
-} sleep_modem_state_phy_link_context_t;
+#define DESC_IDX_SKIP_WIFI               (2)
+#define DESC_SKIP_WIFI_ENTRY_CNT         (8)
+#define DESC_SKIP_WIFI_RESTORE_ENTRY_CNT (1)
+    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1 + DESC_SKIP_WIFI_ENTRY_CNT];
+} sleep_phy_link_context_t;
 
-esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+esp_err_t sleep_phy_link_init(void **link_context)
 {
     esp_err_t err = ESP_OK;
 
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
-    static regdma_link_config_t wifi_modem_config[] = {
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
+    static regdma_link_config_t phy_modem_config[] = {
         [0]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
 
+        /* Reset SET_FREQ fsm */
+        [1]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), FECOEX_SET_FREQ_SET_CHAN_REG,     0,    FECOEX_SET_FREQ_RESETN,                         1, 0),
         /* PMU or software to trigger enable RF PHY */
-        [1]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
-        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
-        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
+        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
+        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
+        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
 
-        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
-        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
-        [6]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
-        [7]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
+        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
+        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [7]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [8]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
 
-        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0),
-        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0),
-        [10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
-        [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0b), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
-        [12] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
-        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
-        [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
+        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_FREQ_RESETN,    FECOEX_SET_FREQ_RESETN,    1, 0),\
+        [10]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0),
+        [11]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0),
+        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [13] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
+        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
+        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
 
         /* PMU to trigger enable RXBLOCK */
-        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
+        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
 
         /* PMU or software to trigger disable RF PHY */
-        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
-        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
-        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
-        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
-        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
-        [21] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
-        [22] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
-        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x17), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
-        [24] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
-        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
+        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
+        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
+        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1),
+        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
+        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [23] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x18), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
+        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
+        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
+        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
 
-        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
+        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
 
         /* PMU to trigger disable RXBLOCK */
-        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [28] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1c), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [29] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
-        [31] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x20), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
-        [33] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1d), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [30] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [32] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
+        [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x21), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [34] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x23), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
 
-        [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x22), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
-        [35] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
+        [36] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
+        [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x25), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
     };
     extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
-    wifi_modem_config[4].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
-    wifi_modem_config[19].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    phy_modem_config[5].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    phy_modem_config[21].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
 
     void *link = NULL;
-    for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
-        void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
+    for (int i = ARRAY_SIZE(phy_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
+        void *next = regdma_link_init_safe(&phy_modem_config[i], false, 0, link);
         if (next) {
             link = next;
         } else {
@@ -111,8 +118,11 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
     if (err == ESP_OK) {
         pau_regdma_set_modem_link_addr(link);
 
-        const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x1a) };
-        static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
+        const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x1c),                                                  /* I2C MST CLK entries */
+                                 REGDMA_PHY_LINK(0x11), REGDMA_PHY_LINK(0x1d), REGDMA_PHY_LINK(0x1e), REGDMA_PHY_LINK(0x1f),
+                                 REGDMA_PHY_LINK(0x20), REGDMA_PHY_LINK(0x21), REGDMA_PHY_LINK(0x22), REGDMA_PHY_LINK(0x23)     /* WiFi Related entries */
+                                };
+        static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
 
         for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
             void *desc = regdma_find_link_by_id(link, 0, id_array[i]);
@@ -124,32 +134,47 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
         }
         if (err == ESP_OK) {
             phy_link_context.link_head = link;
-            *link_head = (void *)&phy_link_context;
+            *link_context = (void *)&phy_link_context;
+        } else {
+            regdma_link_destroy(link, 0);
         }
     }
 #endif
     return err;
 }
 
-void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
+void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
 {
-    sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
+    sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
 
-    if (flags & BIT(0)) {
+    if (flags & SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION) {
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], true, true);
     } else {
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, false);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], false, true);
     }
+
+    if (flags & SLEEP_MODEM_SKIP_WIFI_RETENTION) {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, true);
+        }
+    } else {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            if (i < DESC_SKIP_WIFI_RESTORE_ENTRY_CNT) {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, false);
+            } else {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], false, true);
+            }
+        }
+    }
 }
 
-esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+esp_err_t sleep_phy_link_deinit(void *link_context)
 {
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
-    regdma_link_destroy(((sleep_modem_state_phy_link_context_t *)link_head)->link_head, 0);
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
+    regdma_link_destroy(((sleep_phy_link_context_t *)link_context)->link_head, 0);
 #endif
     return ESP_OK;
 }
-
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
diff --git a/components/esp_hw_support/lowpower/port/esp32s31/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32s31/sleep_phy.c
similarity index 60%
rename from components/esp_hw_support/lowpower/port/esp32s31/sleep_modem_state.c
rename to components/esp_hw_support/lowpower/port/esp32s31/sleep_phy.c
index b7414494ab6..6f3d214bd16 100644
--- a/components/esp_hw_support/lowpower/port/esp32s31/sleep_modem_state.c
+++ b/components/esp_hw_support/lowpower/port/esp32s31/sleep_phy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,7 +17,7 @@
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 
 #define SARADC_TSENS_REG                (0x20818000)
 #define SARADC_TSENS_PU                 (BIT(22))
@@ -35,78 +35,82 @@
 
 static __attribute__((unused)) const char *TAG = "sleep";
 
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
 
 typedef struct {
 #define DESC_IDX_I2C_MST_ENA (0)
 #define DESC_IDX_I2C_MST_DIS (1)
-    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
-} sleep_modem_state_phy_link_context_t;
+#define DESC_IDX_SKIP_WIFI               (2)
+#define DESC_SKIP_WIFI_ENTRY_CNT         (4)
+#define DESC_SKIP_WIFI_RESTORE_ENTRY_CNT (1)
+    void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1 + DESC_SKIP_WIFI_ENTRY_CNT];
+} sleep_phy_link_context_t;
 
-static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
+static esp_err_t sleep_phy_retention_init(void *arg)
 {
-    #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
+    #define PHY_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_PHY))
 
-    static sleep_retention_entries_config_t wifi_modem_config[] = {
-        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
+    static sleep_retention_entries_config_t phy_modem_config[] = {
+        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = PHY_ENTRY() }, /* I2C MST enable */
 
         /* PMU or software to trigger enable RF PHY */
-        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
-        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xffff0000,                0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = WIFIMAC_ENTRY() },
-        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_I2C_MST_BURST_DONE,    0x1,        1, 0), .owner = WIFIMAC_ENTRY() },
-        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x80000,    1, 0), .owner = WIFIMAC_ENTRY() },
-        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x80000,    1, 0), .owner = WIFIMAC_ENTRY() },
-        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = WIFIMAC_ENTRY() },
-        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = WIFIMAC_ENTRY() },
-        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = PHY_ENTRY() }, /* BBPLL calibration enable */
+        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xffff0000,                0xffff0000, 1, 0), .owner = PHY_ENTRY() },
+        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = PHY_ENTRY() },
+        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = PHY_ENTRY() },
+        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_I2C_MST_BURST_DONE,    0x1,        1, 0), .owner = PHY_ENTRY() },
+        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x80000,    1, 0), .owner = PHY_ENTRY() },
+        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x80000,    1, 0), .owner = PHY_ENTRY() },
+        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = PHY_ENTRY() },
+        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = PHY_ENTRY() },
+        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = PHY_ENTRY() },
 
         /* PMU to trigger enable RXBLOCK */
-        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = WIFIMAC_ENTRY() },
+        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = PHY_ENTRY() },
 
         /* PMU or software to trigger disable RF PHY */
-        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
-        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = WIFIMAC_ENTRY() },
-        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x80000,    0, 1), .owner = WIFIMAC_ENTRY() },
-        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
-        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_I2C_MST_BURST_DONE,    0x1,        1, 1), .owner = WIFIMAC_ENTRY() },
-        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = WIFIMAC_ENTRY() },
-        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() },
-        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
+        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = PHY_ENTRY() },
+        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = PHY_ENTRY() },
+        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x80000,    0, 1), .owner = PHY_ENTRY() },
+        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1), .owner = PHY_ENTRY() },
+        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_I2C_MST_BURST_DONE,    0x1,        0, 1), .owner = PHY_ENTRY() },
+        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = PHY_ENTRY() },
+        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xffff0000, 0, 1), .owner = PHY_ENTRY() },
+        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = PHY_ENTRY() }, /* BBPLL calibration disable */
 
-        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
+        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = PHY_ENTRY() }, /* I2C MST disable */
 
         /* PMU to trigger disable RXBLOCK */
-        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
-        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = WIFIMAC_ENTRY() },
-        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = PHY_ENTRY() },
+        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = PHY_ENTRY() },
+        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = PHY_ENTRY() },
 
-        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
-        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
+        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = PHY_ENTRY() },
+        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = PHY_ENTRY() }
     };
     extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
-    wifi_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
-    wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
-    esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
-    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
+    phy_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    phy_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    esp_err_t err = sleep_retention_entries_create(phy_modem_config, ARRAY_SIZE(phy_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link");
     return ESP_OK;
 }
 #endif
 
-esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+esp_err_t sleep_phy_link_init(void **link_head)
 {
     esp_err_t err = ESP_OK;
 
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_phy_retention_init, .arg = NULL } } };
     err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
     if (err == ESP_OK) {
         err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
         if (err == ESP_OK) {
-            const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x14) };
-            static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
-
+            const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x14),
+                                     REGDMA_PHY_LINK(0x0b), REGDMA_PHY_LINK(0x15), REGDMA_PHY_LINK(0x16), REGDMA_PHY_LINK(0x17) /* WiFi Related entries */
+                                    };
+            static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
             for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
                 void *desc = sleep_retention_find_link_by_id(id_array[i]);
                 if (desc) {
@@ -120,35 +124,49 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
             }
         }
     }
+    if (err != ESP_OK) {
+        sleep_phy_link_deinit(NULL);
+    }
 #endif
     return err;
 }
 
-void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
+void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
 {
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
 
-    if (flags & BIT(0)) {
+    if (flags & SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION) {
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], true, true);
     } else {
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, false);
         regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_DIS], false, true);
     }
-#endif
-}
 
-esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
-{
-    esp_err_t err = ESP_OK;
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
-    if (err == ESP_OK) {
-        sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    if (flags & SLEEP_MODEM_SKIP_WIFI_RETENTION) {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, true);
+        }
+    } else {
+        for (int i = 0; i < DESC_SKIP_WIFI_ENTRY_CNT; i++) {
+            if (i < DESC_SKIP_WIFI_RESTORE_ENTRY_CNT) {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], true, false);
+            } else {
+                regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_SKIP_WIFI + i], false, true);
+            }
+        }
     }
 #endif
-    return err;
 }
 
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
+esp_err_t sleep_phy_link_deinit(void *link_head)
+{
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+#endif
+    return ESP_OK;
+}
+
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c
index 8ec4cb64055..a64c43c80e0 100644
--- a/components/esp_hw_support/port/pau_regdma.c
+++ b/components/esp_hw_support/port/pau_regdma.c
@@ -27,12 +27,19 @@ ESP_LOG_ATTR_TAG(TAG, "pau_regdma");
 
 typedef struct {
     pau_hal_context_t *hal;
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_modem_link_protect_cb_t modem_link_protect;
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
 } pau_context_t;
 
 pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
 {
     static pau_hal_context_t pau_hal = { .dev = NULL };
-    static pau_context_t pau_context = { .hal = &pau_hal };
+    static pau_context_t pau_context = { .hal = &pau_hal,
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+        .modem_link_protect = NULL,
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    };
 
     /* periph_module_enable don not need to be put in iram because it is
      * called before the flash is powered off and will not be called again. */
@@ -61,40 +68,116 @@ void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries)
     pau_hal_set_regdma_entry_link_addr(PAU_instance()->hal, link_entries);
 }
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
-#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+void pau_regdma_register_modem_link_protect(pau_regdma_modem_link_protect_cb_t cb)
+{
+    PAU_instance()->modem_link_protect = cb;
+}
+
+void pau_regdma_unregister_modem_link_protect(void)
+{
+    PAU_instance()->modem_link_protect = NULL;
+}
+
+static void IRAM_ATTR pau_regdma_invoke_modem_link_procect(bool protect)
+{
+    if (PAU_instance()->modem_link_protect) {
+        PAU_instance()->modem_link_protect(protect);
+    }
+}
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#if SOC_PM_PAU_REGDMA_LINK_MODEM
 void pau_regdma_set_modem_link_addr(void *link_addr)
 {
     pau_hal_set_regdma_modem_link_addr(PAU_instance()->hal, link_addr);
 }
 #endif
 
-void IRAM_ATTR pau_regdma_trigger_modem_link_backup(void)
+void IRAM_ATTR pau_regdma_trigger_modem_link_backup(bool blocking)
+{
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(true);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_hal_start_regdma_modem_link(PAU_instance()->hal, true, blocking);
+    if (blocking) {
+        pau_hal_stop_regdma_modem_link(PAU_instance()->hal);
+    }
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(false);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+}
+
+void IRAM_ATTR pau_regdma_trigger_modem_link_restore(bool blocking)
+{
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(true);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_hal_start_regdma_modem_link(PAU_instance()->hal, false, blocking);
+    if (blocking) {
+        pau_hal_stop_regdma_modem_link(PAU_instance()->hal);
+    }
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(false);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+}
+
+void IRAM_ATTR pau_regdma_modem_link_complete(void)
 {
-    pau_hal_start_regdma_modem_link(PAU_instance()->hal, true);
     pau_hal_stop_regdma_modem_link(PAU_instance()->hal);
 }
 
-void IRAM_ATTR pau_regdma_trigger_modem_link_restore(void)
+void IRAM_ATTR pau_regdma_done_int_enable(void)
 {
-    pau_hal_start_regdma_modem_link(PAU_instance()->hal, false);
-    pau_hal_stop_regdma_modem_link(PAU_instance()->hal);
+    pau_hal_regdma_done_int_enable(PAU_instance()->hal);
+}
+
+void IRAM_ATTR pau_regdma_done_int_disable(void)
+{
+    pau_hal_regdma_done_int_disable(PAU_instance()->hal);
+}
+
+bool IRAM_ATTR pau_get_regdma_done_status(void)
+{
+    return pau_hal_get_regdma_done_status(PAU_instance()->hal);
+}
+
+void IRAM_ATTR pau_clear_regdma_done_status(void)
+{
+    pau_hal_clear_regdma_backup_done_intr_state(PAU_instance()->hal);
 }
 
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
-void IRAM_ATTR pau_regdma_trigger_wifimac_link_backup(void)
+void IRAM_ATTR pau_regdma_trigger_wifimac_link_backup(bool blocking)
 {
-    pau_hal_start_regdma_wifimac_link(PAU_instance()->hal, true);
-    pau_hal_stop_regdma_wifimac_link(PAU_instance()->hal);
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(true);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_hal_start_regdma_wifimac_link(PAU_instance()->hal, true, blocking);
+    if (blocking) {
+        pau_hal_stop_regdma_wifimac_link(PAU_instance()->hal);
+    }
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(false);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
 }
 
-void IRAM_ATTR pau_regdma_trigger_wifimac_link_restore(void)
+void IRAM_ATTR pau_regdma_trigger_wifimac_link_restore(bool blocking)
 {
-    pau_hal_start_regdma_wifimac_link(PAU_instance()->hal, false);
-    pau_hal_stop_regdma_wifimac_link(PAU_instance()->hal);
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(true);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_hal_start_regdma_wifimac_link(PAU_instance()->hal, false, blocking);
+    if (blocking) {
+        pau_hal_stop_regdma_wifimac_link(PAU_instance()->hal);
+    }
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_invoke_modem_link_procect(false);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
 }
 #endif
-#endif
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
 void IRAM_ATTR pau_regdma_set_system_link_addr(void *link_addr)
diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c
index 72d9cc20ef0..f7c19fac44d 100644
--- a/components/esp_hw_support/sleep_modem.c
+++ b/components/esp_hw_support/sleep_modem.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -129,69 +129,98 @@ void mac_bb_power_up_cb_execute(void)
 
 #endif ///CONFIG_MAC_BB_PD
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
-
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 typedef struct sleep_modem_config {
-    struct {
-        void    *phy_link;
-        union {
-            struct {
-                uint32_t modem_state_phy_done: 1;
-                uint32_t reserved: 31;
-            };
-            uint32_t flags;
+    _lock_t phy_link_lock;
+    void    *phy_link;
+    union {
+        struct {
+            uint32_t phy_link_done: 1;
+            uint32_t modem_mask: SLEEP_MODEM_MAX_CNT;
+            uint32_t reserved: 27 - SLEEP_MODEM_MAX_CNT;
         };
-    } wifi;
+        uint32_t flags;
+    };
 } sleep_modem_config_t;
 
-static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 };
+static sleep_modem_config_t s_sleep_modem = { .phy_link = NULL, .flags = 0 };
 
+bool IRAM_ATTR sleep_modem_wifi_modem_state_is_enabled(void)
+{
+    return !!(s_sleep_modem.modem_mask & SLEEP_MODEM_WIFI);
+}
 
-esp_err_t sleep_modem_wifi_modem_state_init(void)
+esp_err_t sleep_modem_phy_init(sleep_modem_type_t modem_mask)
 {
     esp_err_t err = ESP_OK;
-
     void *link = NULL;
-    if (s_sleep_modem.wifi.phy_link == NULL) {
-        err = sleep_modem_state_phy_link_init(&link);
-        if (err == ESP_OK) {
-            s_sleep_modem.wifi.phy_link = link;
-            s_sleep_modem.wifi.flags = 0;
+
+    _lock_acquire(&s_sleep_modem.phy_link_lock);
+    if (s_sleep_modem.modem_mask & modem_mask) {
+        _lock_release(&s_sleep_modem.phy_link_lock);
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (!s_sleep_modem.modem_mask) {
+        s_sleep_modem.flags = 0;
+        if (!s_sleep_modem.phy_link) {
+            err = sleep_phy_link_init(&link);
+            if (err == ESP_OK) {
+                s_sleep_modem.phy_link = link;
+            } else {
+                _lock_release(&s_sleep_modem.phy_link_lock);
+                return err;
+            }
         }
     }
+    s_sleep_modem.modem_mask |= modem_mask;
+    _lock_release(&s_sleep_modem.phy_link_lock);
     return err;
 }
 
-__attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
+__attribute__((unused)) void sleep_modem_phy_deinit(sleep_modem_type_t modem_mask)
 {
-    if (s_sleep_modem.wifi.phy_link) {
-        sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link);
-        s_sleep_modem.wifi.phy_link = NULL;
-        s_sleep_modem.wifi.flags = 0;
+    _lock_acquire(&s_sleep_modem.phy_link_lock);
+    if (!(s_sleep_modem.modem_mask & modem_mask)) {
+        _lock_release(&s_sleep_modem.phy_link_lock);
+        return;
     }
+
+    s_sleep_modem.modem_mask &= ~modem_mask;
+    if (s_sleep_modem.phy_link && !s_sleep_modem.modem_mask) {
+        sleep_phy_link_deinit(s_sleep_modem.phy_link);
+        s_sleep_modem.phy_link = NULL;
+        s_sleep_modem.flags = 0;
+    }
+    _lock_release(&s_sleep_modem.phy_link_lock);
 }
 
-void IRAM_ATTR sleep_modem_wifi_do_phy_retention(bool restore, bool wifimac_link_is_sel)
+void IRAM_ATTR sleep_modem_phy_retention_complete(void)
 {
-    sleep_modem_state_phy_link_config(s_sleep_modem.wifi.phy_link, 1);
-    sleep_retention_do_phy_retention(!restore, wifimac_link_is_sel);
-    sleep_modem_state_phy_link_config(s_sleep_modem.wifi.phy_link, 0);
+    sleep_retention_phy_retention_complete();
+}
+
+void IRAM_ATTR sleep_modem_do_phy_retention(bool restore, bool wifimac_link_is_sel, uint8_t flags)
+{
+    sleep_phy_link_config(s_sleep_modem.phy_link, flags);
+    sleep_retention_do_phy_retention(!restore, wifimac_link_is_sel, true);
+    sleep_phy_link_config(s_sleep_modem.phy_link, SLEEP_MODEM_RESET_RETENTION);
     if (!restore) {
-        s_sleep_modem.wifi.modem_state_phy_done = 1;
+        s_sleep_modem.phy_link_done = 1;
     }
 }
 
-inline __attribute__((always_inline)) bool sleep_modem_wifi_modem_state_enabled(void)
+inline __attribute__((always_inline)) bool sleep_modem_phy_link_enabled(void)
 {
-    return (s_sleep_modem.wifi.phy_link != NULL);
+    return s_sleep_modem.modem_mask;
 }
 
-inline __attribute__((always_inline)) bool sleep_modem_wifi_modem_link_done(void)
+inline __attribute__((always_inline)) bool sleep_modem_phy_link_done(void)
 {
-    return (s_sleep_modem.wifi.modem_state_phy_done == 1);
+    return (s_sleep_modem.phy_link_done == 1);
 }
 
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 
 bool modem_domain_pd_allowed(void)
 {
@@ -229,8 +258,8 @@ uint32_t sleep_modem_reject_triggers(void)
 {
     uint32_t reject_triggers = 0;
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
-    reject_triggers = (s_sleep_modem.wifi.phy_link != NULL) ? PMU_MODEM_WAKEUP_PROTECT : 0;
-#endif
+    reject_triggers = sleep_modem_wifi_modem_state_is_enabled() ? PMU_MODEM_WAKEUP_PROTECT : 0;
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
     return reject_triggers;
 }
 
@@ -241,8 +270,8 @@ bool IRAM_ATTR sleep_modem_wifi_modem_state_skip_light_sleep(void)
     /* To block the system from entering sleep before modem link done. In light
      * sleep mode, the system may switch to modem state, which will cause
      * hardware to fail to enable RF */
-    skip = sleep_modem_wifi_modem_state_enabled() && !sleep_modem_wifi_modem_link_done();
-#endif
+    skip = sleep_modem_wifi_modem_state_is_enabled() && !sleep_modem_phy_link_done();
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
     return skip;
 }
 
diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c
index 54bad4f9901..3d0e0349a1d 100644
--- a/components/esp_hw_support/sleep_retention.c
+++ b/components/esp_hw_support/sleep_retention.c
@@ -1303,8 +1303,8 @@ void IRAM_ATTR sleep_retention_do_system_retention(bool backup_or_restore)
 }
 #endif
 
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE
-void IRAM_ATTR sleep_retention_do_phy_retention(bool backup_or_restore, bool wifimac_link_is_sel)
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+void IRAM_ATTR sleep_retention_do_phy_retention(bool backup_or_restore, bool wifimac_link_is_sel, bool blocking)
 {
 /* since the PHY link and other module links are within the sleep-retention entry (4) context，
 *  add mutex protection to avoid data race.
@@ -1315,24 +1315,35 @@ void IRAM_ATTR sleep_retention_do_phy_retention(bool backup_or_restore, bool wif
     if (backup_or_restore) {
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
         if (wifimac_link_is_sel) {
-            pau_regdma_trigger_wifimac_link_backup();
+            pau_regdma_trigger_wifimac_link_backup(blocking);
         } else
 #endif
         {
-            pau_regdma_trigger_modem_link_backup();
+            pau_regdma_trigger_modem_link_backup(blocking);
         }
     } else {
 #if SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
         if (wifimac_link_is_sel) {
-            pau_regdma_trigger_wifimac_link_restore();
+            pau_regdma_trigger_wifimac_link_restore(blocking);
         } else
 #endif
         {
-            pau_regdma_trigger_modem_link_restore();
+            pau_regdma_trigger_modem_link_restore(blocking);
         }
     }
 #if SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
     _lock_release_recursive(&s_retention.lock);
 #endif
 }
-#endif /*SOC_PM_SUPPORT_PMU_MODEM_STATE */
+
+void IRAM_ATTR sleep_retention_phy_retention_complete(void)
+{
+#if SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
+    _lock_acquire_recursive(&s_retention.lock);
+#endif
+    pau_regdma_modem_link_complete();
+#if SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
+    _lock_release_recursive(&s_retention.lock);
+#endif
+}
+#endif // SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
diff --git a/components/esp_phy/Kconfig b/components/esp_phy/Kconfig
index e51102d1da3..2e14e8f89c9 100644
--- a/components/esp_phy/Kconfig
+++ b/components/esp_phy/Kconfig
@@ -260,5 +260,11 @@ menu "PHY"
             help
                 Select to print PHY version in esp_phy_enable. This config only applies to esp32hxx for now.
 
+        config ESP_PHY_HW_SWITCH_RF
+            bool "Enable Hardware Triggered RF Switch"
+            depends on SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+            default n
+            help
+                Enabling this feature will allow PHY disable and enable using REGDMA.
     endif
 endmenu  # PHY
diff --git a/components/esp_phy/esp32c5/phy_init_data.c b/components/esp_phy/esp32c5/phy_init_data.c
index 0ee2aa51599..836eb5b715d 100644
--- a/components/esp_phy/esp32c5/phy_init_data.c
+++ b/components/esp_phy/esp32c5/phy_init_data.c
@@ -276,13 +276,16 @@ const esp_phy_init_data_t phy_init_data= { {
 } };
 
 const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+#include "esp_private/sleep_retention.h"
+uint8_t s_phy_fe_retention_ref = 0;
+static _lock_t s_phy_fe_retention_lock;
+static const char* TAG = "phy_sleep";
+
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 
 #if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 
-#include "esp_private/sleep_retention.h"
-
-static const char* TAG = "phy_sleep";
-
 static esp_err_t sleep_retention_wifi_bb_init(void *arg)
 {
     #define N_REGS_WIFI_AGC()           (130)
@@ -290,21 +293,13 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
     #define N_REGS_WIFI_NRX()           (145)
     #define N_REGS_WIFI_BB()            (82)
     #define N_REGS_WIFI_BRX()           (39)
-    #define N_REGS_WIFI_FE_COEX()       (21)
-    #define N_REGS_WIFI_FE_DATA()       (35)
-    #define N_REGS_WIFI_FE_CTRL()       (56)
-    #define N_REGS_WIFI_FE_DATA_WIFI()  (22)
 
     const static sleep_retention_entries_config_t bb_regs_retention[] = {
         [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(),         0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(),          0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(),          0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
-        [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
-        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
-        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
-        [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, N_REGS_WIFI_FE_DATA_WIFI(),0, 0), .owner = BIT(0) | BIT(1) }  /* FE WIFI DATA */
+        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b04, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
@@ -337,6 +332,7 @@ void esp_phy_sleep_data_init(void)
         .attribute = SLEEP_RETENTION_MODULE_ATTR_ATTACH,
         .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
     };
+    RETENTION_MODULE_BITMAP_SET(&init_param.depends, SLEEP_RETENTION_MODULE_PHY_FE);
     esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
     if (err != ESP_OK) {
         ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
@@ -360,5 +356,65 @@ void esp_phy_sleep_data_deinit(void)
         ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
     }
 }
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 
-#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+static esp_err_t sleep_retention_phy_fe_init(void *arg)
+{
+    #define N_REGS_FE_COEX()           (21)
+    #define N_REGS_FE_DATA()           (35)
+    #define N_REGS_FE_CTRL()           (56)
+    #define N_REGS_FE_DATA_WIFI()      (22)
+    #define REG_FECOEX_BASE             0x600a0000
+    #define REG_FEDATA_BASE             0x600a0400
+    #define REG_FECTRL_BASE             0x600a0800
+    #define REG_FEDATAWIFI_BASE         0x600a0c00
+    const static sleep_retention_entries_config_t phy_fe_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), REG_FECOEX_BASE, REG_FECOEX_BASE, N_REGS_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), REG_FEDATA_BASE, REG_FEDATA_BASE, N_REGS_FE_DATA(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
+        [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(2), REG_FECTRL_BASE, REG_FECTRL_BASE, N_REGS_FE_CTRL(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
+        [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(3), REG_FEDATAWIFI_BASE, REG_FEDATAWIFI_BASE, N_REGS_FE_DATA_WIFI(),0, 0), .owner = BIT(0) | BIT(1) }  /* FE WIFI DATA */
+    };
+    esp_err_t err = sleep_retention_entries_create(phy_fe_regs_retention, ARRAY_SIZE(phy_fe_regs_retention), 3, SLEEP_RETENTION_MODULE_PHY_FE);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "PHY FE");
+    ESP_LOGD(TAG, "PHY FE sleep retention initialization");
+    return ESP_OK;
+}
+
+esp_err_t esp_phy_fe_sleep_data_init(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref++ == 0) {
+        sleep_retention_module_init_param_t init_param = {
+            .cbs     = { .create = { .handle = sleep_retention_phy_fe_init, .arg = NULL } },
+            .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
+        };
+        esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_PHY_FE, &init_param);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention init failed");
+            s_phy_fe_retention_ref --;
+            _lock_release(&s_phy_fe_retention_lock);
+            return err;
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+    return ESP_OK;
+}
+
+void esp_phy_fe_sleep_data_deinit(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref == 0) {
+        _lock_release(&s_phy_fe_retention_lock);
+        return;
+    }
+
+    if (--s_phy_fe_retention_ref == 0) {
+        esp_err_t err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_PHY_FE);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention deinit failed");
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+}
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
diff --git a/components/esp_phy/esp32c6/phy_init_data.c b/components/esp_phy/esp32c6/phy_init_data.c
index 068b66a6088..383d82a19eb 100644
--- a/components/esp_phy/esp32c6/phy_init_data.c
+++ b/components/esp_phy/esp32c6/phy_init_data.c
@@ -148,12 +148,15 @@ const esp_phy_init_data_t phy_init_data= { {
 
 const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
 
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
-
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 #include "esp_private/sleep_retention.h"
 
 static const char* TAG = "phy_sleep";
+static _lock_t s_phy_fe_retention_lock;
+uint8_t s_phy_fe_retention_ref = 0;
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 static esp_err_t sleep_retention_wifi_bb_init(void *arg)
 {
     #define N_REGS_WIFI_AGC()       (121)
@@ -161,14 +164,12 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
     #define N_REGS_WIFI_NRX()       (136)
     #define N_REGS_WIFI_BB()        (53)
     #define N_REGS_WIFI_BRX()       (39)
-    #define N_REGS_WIFI_FE_COEX()   (58)
 
     const static sleep_retention_entries_config_t bb_regs_retention[] = {
         [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(),     0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(),      0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(),      0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
@@ -201,6 +202,7 @@ void esp_phy_sleep_data_init(void)
         .attribute = SLEEP_RETENTION_MODULE_ATTR_ATTACH,
         .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
     };
+    RETENTION_MODULE_BITMAP_SET(&init_param.depends, SLEEP_RETENTION_MODULE_PHY_FE);
     esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
     if (err != ESP_OK) {
         ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
@@ -224,5 +226,57 @@ void esp_phy_sleep_data_deinit(void)
         ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
     }
 }
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 
-#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+static esp_err_t sleep_retention_phy_fe_init(void *arg)
+{
+    #define N_REGS_FE_COEX()       (58)
+    #define REG_FECOEX_BASE         0x600a0000
+
+    const static sleep_retention_entries_config_t phy_fe_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), REG_FECOEX_BASE, REG_FECOEX_BASE, N_REGS_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+    };
+    esp_err_t err = sleep_retention_entries_create(phy_fe_regs_retention, ARRAY_SIZE(phy_fe_regs_retention), 3, SLEEP_RETENTION_MODULE_PHY_FE);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "PHY FE");
+    ESP_LOGD(TAG, "PHY FE sleep retention initialization");
+    return ESP_OK;
+}
+
+esp_err_t esp_phy_fe_sleep_data_init(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref++ == 0) {
+        sleep_retention_module_init_param_t init_param = {
+            .cbs     = { .create = { .handle = sleep_retention_phy_fe_init, .arg = NULL } },
+            .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
+        };
+        esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_PHY_FE, &init_param);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention init failed");
+            s_phy_fe_retention_ref --;
+            _lock_release(&s_phy_fe_retention_lock);
+            return err;
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+    return ESP_OK;
+}
+
+void esp_phy_fe_sleep_data_deinit(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref == 0) {
+        _lock_release(&s_phy_fe_retention_lock);
+        return;
+    }
+
+    if (--s_phy_fe_retention_ref == 0) {
+        esp_err_t err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_PHY_FE);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention deinit failed");
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+}
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
diff --git a/components/esp_phy/esp32c61/phy_init_data.c b/components/esp_phy/esp32c61/phy_init_data.c
index 081df9a8261..e491a4f0a62 100644
--- a/components/esp_phy/esp32c61/phy_init_data.c
+++ b/components/esp_phy/esp32c61/phy_init_data.c
@@ -148,13 +148,15 @@ const esp_phy_init_data_t phy_init_data= { {
 } };
 
 const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
-
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
-
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 #include "esp_private/sleep_retention.h"
 
 static const char* TAG = "phy_sleep";
+static _lock_t s_phy_fe_retention_lock;
+uint8_t s_phy_fe_retention_ref = 0;
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 static esp_err_t sleep_retention_wifi_bb_init(void *arg)
 {
     #define N_REGS_WIFI_AGC()       (130)
@@ -162,21 +164,13 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
     #define N_REGS_WIFI_NRX()       (145)
     #define N_REGS_WIFI_BB()        (82)
     #define N_REGS_WIFI_BRX()       (39)
-    #define N_REGS_WIFI_FE_COEX()   (21)
-    #define N_REGS_WIFI_FE_DATA()   (34)
-    #define N_REGS_WIFI_FE_CTRL()   (56)
-    #define N_REGS_WIFI_FE_WIFI()   (21)
 
     const static sleep_retention_entries_config_t bb_regs_retention[] = {
         [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(),     0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(),      0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(),      0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
-        [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
-        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
-        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
-        [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, N_REGS_WIFI_FE_WIFI(), 0, 0), .owner = BIT(0) | BIT(1) }  /* FE WiFi DATA */
+        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b04, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
@@ -209,6 +203,7 @@ void esp_phy_sleep_data_init(void)
         .attribute = SLEEP_RETENTION_MODULE_ATTR_ATTACH,
         .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
     };
+    RETENTION_MODULE_BITMAP_SET(&init_param.depends, SLEEP_RETENTION_MODULE_PHY_FE);
     esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
     if (err != ESP_OK) {
         ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
@@ -233,4 +228,66 @@ void esp_phy_sleep_data_deinit(void)
     }
 }
 
-#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD.
+
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+static esp_err_t sleep_retention_phy_fe_init(void *arg)
+{
+    #define N_REGS_FE_COEX()            (21)
+    #define N_REGS_FE_DATA()            (34)
+    #define N_REGS_FE_CTRL()            (56)
+    #define N_REGS_FE_DATA_WIFI()       (21)
+    #define REG_FECOEX_BASE             0x600a0000
+    #define REG_FEDATA_BASE             0x600a0400
+    #define REG_FECTRL_BASE             0x600a0800
+    #define REG_FEDATAWIFI_BASE         0x600a0c00
+
+    const static sleep_retention_entries_config_t phy_fe_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), REG_FECOEX_BASE, REG_FECOEX_BASE, N_REGS_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), REG_FEDATA_BASE, REG_FEDATA_BASE, N_REGS_FE_DATA(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
+        [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(2), REG_FECTRL_BASE, REG_FECTRL_BASE, N_REGS_FE_CTRL(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
+        [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(3), REG_FEDATAWIFI_BASE, REG_FEDATAWIFI_BASE, N_REGS_FE_DATA_WIFI(),0, 0), .owner = BIT(0) | BIT(1) }  /* FE WIFI DATA */
+    };
+    esp_err_t err = sleep_retention_entries_create(phy_fe_regs_retention, ARRAY_SIZE(phy_fe_regs_retention), 3, SLEEP_RETENTION_MODULE_PHY_FE);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "PHY FE");
+    ESP_LOGD(TAG, "PHY FE sleep retention initialization");
+    return ESP_OK;
+}
+
+esp_err_t esp_phy_fe_sleep_data_init(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref++ == 0) {
+        sleep_retention_module_init_param_t init_param = {
+            .cbs     = { .create = { .handle = sleep_retention_phy_fe_init, .arg = NULL } },
+            .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
+        };
+        esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_PHY_FE, &init_param);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention init failed");
+            s_phy_fe_retention_ref --;
+            _lock_release(&s_phy_fe_retention_lock);
+            return err;
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+    return ESP_OK;
+}
+
+void esp_phy_fe_sleep_data_deinit(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref == 0) {
+        _lock_release(&s_phy_fe_retention_lock);
+        return;
+    }
+
+    if (--s_phy_fe_retention_ref == 0) {
+        esp_err_t err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_PHY_FE);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention deinit failed");
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+}
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
diff --git a/components/esp_phy/esp32s31/phy_init_data.c b/components/esp_phy/esp32s31/phy_init_data.c
index 4d635da82bb..5f83a25756c 100644
--- a/components/esp_phy/esp32s31/phy_init_data.c
+++ b/components/esp_phy/esp32s31/phy_init_data.c
@@ -149,12 +149,17 @@ const esp_phy_init_data_t phy_init_data= { {
 
 const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
 
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 
 #include "esp_private/sleep_retention.h"
 
 static const char* TAG = "phy_sleep";
+static _lock_t s_phy_fe_retention_lock;
+uint8_t s_phy_fe_retention_ref = 0;
 
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 static esp_err_t sleep_retention_wifi_bb_init(void *arg)
 {
     #define N_REGS_WIFI_AGC()           (130)
@@ -162,19 +167,11 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
     #define N_REGS_WIFI_NRX()           (145)
     #define N_REGS_WIFI_BB()            (84)
     #define N_REGS_WIFI_BRX()           (39)
-    #define N_REGS_WIFI_FE_COEX()       (22)
-    #define N_REGS_WIFI_FE_DATA()       (35)
-    #define N_REGS_WIFI_FE_CTRL()       (57)
-    #define N_REGS_WIFI_FE_DATA_WIFI()  (22)
     #define AGC_BASE            0x20107000
     #define BB_TX_BASE          0x20107400
     #define NRX_BASE            0x20107800
     #define BB_BASE             0x20107C00
     #define BRX_BASE            0x20108000
-    #define REG_FECOEX_BASE             0x20100000
-    #define REG_FEDATA_BASE             0x20100400
-    #define REG_FECTRL_BASE             0x20100800
-    #define REG_FEDATAWIFI_BASE         0x20100c00
 /*
 AGC agc_reg: 0x000 ~0x204         130
 BB bb_reg: 0x000~0x14c            84
@@ -188,11 +185,7 @@ NRX: 0x000~0x240                  145
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, BB_TX_BASE,          BB_TX_BASE,             N_REGS_WIFI_TX(),          0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, NRX_BASE,            NRX_BASE,               N_REGS_WIFI_NRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, BB_BASE,             BB_BASE,                N_REGS_WIFI_BB(),          0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, REG_FECOEX_BASE,     REG_FECOEX_BASE,        N_REGS_WIFI_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
-        [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, BRX_BASE,            BRX_BASE,               N_REGS_WIFI_BRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
-        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, REG_FEDATA_BASE,     REG_FEDATA_BASE,        N_REGS_WIFI_FE_DATA(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
-        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, REG_FECTRL_BASE,     REG_FECTRL_BASE,        N_REGS_WIFI_FE_CTRL(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
-        [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, REG_FEDATAWIFI_BASE, REG_FEDATAWIFI_BASE, N_REGS_WIFI_FE_DATA_WIFI(),   0, 0), .owner = BIT(0) | BIT(1) }  /* FE WIFI DATA */
+        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b04, BRX_BASE,            BRX_BASE,               N_REGS_WIFI_BRX(),         0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
@@ -225,6 +218,7 @@ void esp_phy_sleep_data_init(void)
         .attribute = SLEEP_RETENTION_MODULE_ATTR_ATTACH,
         .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
     };
+    RETENTION_MODULE_BITMAP_SET(&init_param.depends, SLEEP_RETENTION_MODULE_PHY_FE);
     esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
     if (err != ESP_OK) {
         ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
@@ -248,5 +242,66 @@ void esp_phy_sleep_data_deinit(void)
         ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
     }
 }
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 
-#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+static esp_err_t sleep_retention_phy_fe_init(void *arg)
+{
+    #define N_REGS_FE_COEX()            (22)
+    #define N_REGS_FE_DATA()            (35)
+    #define N_REGS_FE_CTRL()            (57)
+    #define N_REGS_FE_DATA_WIFI()       (22)
+    #define REG_FECOEX_BASE             0x20100000
+    #define REG_FEDATA_BASE             0x20100400
+    #define REG_FECTRL_BASE             0x20100800
+    #define REG_FEDATAWIFI_BASE         0x20100c00
+
+    const static sleep_retention_entries_config_t phy_fe_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), REG_FECOEX_BASE, REG_FECOEX_BASE, N_REGS_FE_COEX(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), REG_FEDATA_BASE, REG_FEDATA_BASE, N_REGS_FE_DATA(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
+        [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(2), REG_FECTRL_BASE, REG_FECTRL_BASE, N_REGS_FE_CTRL(),     0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
+        [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(3), REG_FEDATAWIFI_BASE, REG_FEDATAWIFI_BASE, N_REGS_FE_DATA_WIFI(),0, 0), .owner = BIT(0) | BIT(1) }  /* FE WIFI DATA */
+    };
+    esp_err_t err = sleep_retention_entries_create(phy_fe_regs_retention, ARRAY_SIZE(phy_fe_regs_retention), 3, SLEEP_RETENTION_MODULE_PHY_FE);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "PHY FE");
+    ESP_LOGD(TAG, "PHY FE sleep retention initialization");
+    return ESP_OK;
+}
+
+esp_err_t esp_phy_fe_sleep_data_init(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref++ == 0) {
+        sleep_retention_module_init_param_t init_param = {
+            .cbs     = { .create = { .handle = sleep_retention_phy_fe_init, .arg = NULL } },
+            .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
+        };
+        esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_PHY_FE, &init_param);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention init failed");
+            s_phy_fe_retention_ref --;
+            _lock_release(&s_phy_fe_retention_lock);
+            return err;
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+    return ESP_OK;
+}
+
+void esp_phy_fe_sleep_data_deinit(void)
+{
+    _lock_acquire(&s_phy_fe_retention_lock);
+    if (s_phy_fe_retention_ref == 0) {
+        _lock_release(&s_phy_fe_retention_lock);
+        return;
+    }
+
+    if (--s_phy_fe_retention_ref == 0) {
+        esp_err_t err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_PHY_FE);
+        if (err != ESP_OK) {
+            ESP_LOGW(TAG, "PHY FE sleep retention deinit failed");
+        }
+    }
+    _lock_release(&s_phy_fe_retention_lock);
+}
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
diff --git a/components/esp_phy/include/esp_phy_init.h b/components/esp_phy/include/esp_phy_init.h
index c41e970c5a6..edf27e7a21e 100644
--- a/components/esp_phy/include/esp_phy_init.h
+++ b/components/esp_phy/include/esp_phy_init.h
@@ -200,14 +200,18 @@ void esp_phy_load_cal_and_init(void);
 
 /**
  * @brief Initialize backup memory for Phy power up/down
+ *
+ * @param modem Modem calling phy retention
  */
-void esp_phy_modem_init(void);
+void esp_phy_modem_init(uint8_t modem);
 
 /**
  * @brief Deinitialize backup memory for Phy power up/down
  * Set phy_init_flag if all modems deinit on ESP32C3
+ *
+ * @param modem Modem calling phy retention
  */
-void esp_phy_modem_deinit(void);
+void esp_phy_modem_deinit(uint8_t modem);
 
 #if CONFIG_MAC_BB_PD
 /**
diff --git a/components/esp_phy/include/esp_private/phy.h b/components/esp_phy/include/esp_private/phy.h
index dcbafcab296..21d4374fb35 100644
--- a/components/esp_phy/include/esp_private/phy.h
+++ b/components/esp_phy/include/esp_private/phy.h
@@ -257,7 +257,7 @@ void esp_phy_modem_rf_flag_update(void);
 
 #if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
 /**
- * @brief PHY module sleep data (includes AGC, TX, NRX, BB, FE, etc..) initialize.
+ * @brief PHY module sleep data (includes AGC, TX, NRX, BB, etc..) initialize.
  */
 void esp_phy_sleep_data_init(void);
 
@@ -300,7 +300,19 @@ void phy_wait_freq_hw_hop_done(void);
  */
 void phy_track_temp_debug(uint8_t debug_flag, uint8_t track_temp);
 #endif
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
+/**
+ * @brief PHY module common memory (FE) initialize
+ *
+ */
+esp_err_t esp_phy_fe_sleep_data_init(void);
 
+/**
+ * @brief PHY module common memory (FE) de-initialize
+ *
+ */
+void esp_phy_fe_sleep_data_deinit(void);
+#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && (CONFIG_MAC_BB_PD || CONFIG_ESP_PHY_HW_SWITCH_RF)
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_phy/src/btbb_init.c b/components/esp_phy/src/btbb_init.c
index bcd7768ec37..a0199764577 100644
--- a/components/esp_phy/src/btbb_init.c
+++ b/components/esp_phy/src/btbb_init.c
@@ -21,6 +21,7 @@ static uint8_t s_btbb_access_ref = 0;
 #if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #include "esp_private/sleep_retention.h"
 #include "btbb_retention_reg.h"
+#include "esp_private/phy.h"
 static const char* TAG = "btbb_init";
 
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG
@@ -32,13 +33,13 @@ static const char* TAG = "btbb_init";
 static esp_err_t btbb_sleep_retention_init(void *arg)
 {
     const static sleep_retention_entries_config_t btbb_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x00), BB_PART_0_ADDR, BB_PART_0_ADDR, BB_PART_0_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
-        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x01), BB_PART_1_ADDR, BB_PART_1_ADDR, BB_PART_1_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
+        { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x00), BB_PART_0_ADDR, BB_PART_0_ADDR, BB_PART_0_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
+        { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x01), BB_PART_1_ADDR, BB_PART_1_ADDR, BB_PART_1_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
 #if BB_PART_CNT > 2
-        [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x02), BB_PART_2_ADDR, BB_PART_2_ADDR, BB_PART_2_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
+        { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x02), BB_PART_2_ADDR, BB_PART_2_ADDR, BB_PART_2_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
 #endif // BB_PART_CNT > 2
 #if BB_PART_CNT > 3
-        [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x03), BB_PART_3_ADDR, BB_PART_3_ADDR, BB_PART_3_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
+        { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x03), BB_PART_3_ADDR, BB_PART_3_ADDR, BB_PART_3_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
 #endif // BB_PART_CNT > 3
     };
     esp_err_t err = sleep_retention_entries_create(btbb_regs_retention, ARRAY_SIZE(btbb_regs_retention), REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BT_BB);
@@ -70,6 +71,9 @@ static esp_err_t btbb_sleep_retention_enable(void)
         .attribute = SLEEP_RETENTION_MODULE_ATTR_ATTACH,
     };
         init_param.depends.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32);
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+        init_param.depends.bitmap[SLEEP_RETENTION_MODULE_PHY_FE >> 5] |= BIT(SLEEP_RETENTION_MODULE_PHY_FE % 32);
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
 #if SOC_PM_MODEM_LOCK_CLK_WORKAROUND && CONFIG_BT_CTRL_SLEEP_ENABLE
         init_param.depends.bitmap[SLEEP_RETENTION_MODULE_POWER >> 5] |= BIT(SLEEP_RETENTION_MODULE_POWER % 32);
 #endif
@@ -97,9 +101,20 @@ void esp_btbb_enable(void)
     if (s_btbb_access_ref == 0) {
         bt_bb_v2_init_cmplx(BTBB_ENABLE_VERSION_PRINT);
 #if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE
-        esp_err_t err = btbb_sleep_retention_enable();
+        esp_err_t err = ESP_OK;
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+        err = esp_phy_fe_sleep_data_init();
+        if (err != ESP_OK) {
+            _lock_release(&s_btbb_access_lock);
+            return;
+        }
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
+        err = btbb_sleep_retention_enable();
         if (err != ESP_OK) {
             btbb_sleep_retention_disable();
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+            esp_phy_fe_sleep_data_deinit();
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
             _lock_release(&s_btbb_access_lock);
             return;
         }
@@ -115,6 +130,9 @@ void esp_btbb_disable(void)
     if (s_btbb_access_ref && (--s_btbb_access_ref == 0)) {
 #if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE
         btbb_sleep_retention_disable();
+#if CONFIG_ESP_PHY_HW_SWITCH_RF
+        esp_phy_fe_sleep_data_deinit();
+#endif // CONFIG_ESP_PHY_HW_SWITCH_RF
 #endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE
     }
     _lock_release(&s_btbb_access_lock);
diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c
index dc2dbf0dccf..7f63b8efba0 100644
--- a/components/esp_phy/src/phy_init.c
+++ b/components/esp_phy/src/phy_init.c
@@ -55,6 +55,9 @@
 #include "soc/periph_defs.h"
 #endif
 #include "phy_init_deps.h"
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+#include "esp_private/esp_pau.h"
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
 
 #ifndef PHY_INIT_MODEM_CLOCK_REQUIRED_BITS
 #warning "PHY_INIT_MODEM_CLOCK_REQUIRED_BITS not defined; using default value 0"
@@ -68,11 +71,16 @@ extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
 extern void pm_mac_modem_clear_rf_power_state(void);
 extern bool pm_mac_modem_rf_already_enabled(void);
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
 extern bool pm_get_wifimac_regdma_link_selection(void);
 #endif
 #endif
 
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+extern void phy_i2c_enter_critical(void);
+extern void phy_i2c_exit_critical(void);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+
 static const char* TAG = "phy_init";
 
 static _lock_t s_phy_access_lock;
@@ -103,7 +111,7 @@ static bool s_is_phy_reg_stored = false;
 /* Memory to store PHY digital registers */
 static uint32_t* s_phy_digital_regs_mem = NULL;
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP || CONFIG_ESP_PHY_HW_SWITCH_RF
 static uint8_t s_phy_modem_init_ref = 0;
 #endif
 
@@ -341,11 +349,18 @@ void esp_phy_enable(esp_phy_modem_t modem)
 #endif
             s_is_phy_calibrated = true;
         } else {
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
-            bool wifimac_link_is_sel = false;
             if (!pm_mac_modem_rf_already_enabled()) {
-                if (sleep_modem_wifi_modem_state_enabled() && sleep_modem_wifi_modem_link_done()) {
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
+                if (sleep_modem_phy_link_enabled() && sleep_modem_phy_link_done()) {
+                    uint8_t modem_flags = SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION;
+                    if (!sleep_modem_wifi_modem_state_is_enabled()) {
+                        modem_flags |= SLEEP_MODEM_SKIP_WIFI_RETENTION;
+                    }
+                    bool wifimac_link_is_sel = false;
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && \
+    SOC_PM_PAU_REGDMA_LINK_IDX_PHY && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
 /*
  * A race exists between SoC wakeup and modem state sleep. After modem initiates sleep,
  * SoC may wake up before REGDMA completes RF close, leaving mac_modem_sleep_flag uncleared
@@ -356,18 +371,20 @@ void esp_phy_enable(esp_phy_modem_t modem)
  * cleared by regdma closing RF with wifimac link.
  * See WIFI-7246 for details.
 */
-                wifimac_link_is_sel = pm_get_wifimac_regdma_link_selection();
+                    wifimac_link_is_sel = pm_get_wifimac_regdma_link_selection();
 #endif
-                sleep_modem_wifi_do_phy_retention(true, wifimac_link_is_sel);
+                    sleep_modem_do_phy_retention(true, wifimac_link_is_sel, modem_flags);
                 } else {
                     phy_wakeup_init();
                 }
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
             } else {
                 phy_wakeup_from_modem_state_extra_init();
             }
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
 #else
             phy_wakeup_init();
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
 
 #if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
             phy_digital_regs_load();
@@ -421,16 +438,23 @@ void esp_phy_disable(esp_phy_modem_t modem)
 #if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
         phy_digital_regs_store();
 #endif
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
         pm_mac_modem_clear_rf_power_state();
-        if (sleep_modem_wifi_modem_state_enabled()) {
-            bool wifimac_link_is_sel = false;
-#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
+        if (sleep_modem_phy_link_enabled()) {
+            uint8_t modem_flags = SLEEP_MODEM_SKIP_I2C_MST_CLK_RETENTION;
+            if (!sleep_modem_wifi_modem_state_is_enabled()) {
+                modem_flags |= SLEEP_MODEM_SKIP_WIFI_RETENTION;
+            }
+             bool wifimac_link_is_sel = false;
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && \
+    SOC_PM_PAU_REGDMA_LINK_IDX_PHY && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
             wifimac_link_is_sel = pm_get_wifimac_regdma_link_selection();
 #endif
-            sleep_modem_wifi_do_phy_retention(false, wifimac_link_is_sel);
+            sleep_modem_do_phy_retention(false, wifimac_link_is_sel, modem_flags);
         } else
-#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
+#endif /* SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY */
         {
             // Disable PHY and RF.
             phy_close_rf();
@@ -495,9 +519,20 @@ void esp_wifi_bt_power_domain_off(void)
 #endif // SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD
 }
 
-void esp_phy_modem_init(void)
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+void IRAM_ATTR esp_phy_regi2c_lock_apply(bool enable)
 {
-#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    if (enable) {
+        phy_i2c_enter_critical();
+    } else {
+        phy_i2c_exit_critical();
+    }
+}
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+
+void esp_phy_modem_init(uint8_t modem)
+{
+#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP || CONFIG_ESP_PHY_HW_SWITCH_RF
     _lock_acquire(&s_phy_access_lock);
     s_phy_modem_init_ref++;
 #if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
@@ -505,18 +540,27 @@ void esp_phy_modem_init(void)
         s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
     }
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
-    sleep_modem_wifi_modem_state_init();
-#endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if (SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP) || CONFIG_ESP_PHY_HW_SWITCH_RF
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    pau_regdma_register_modem_link_protect(esp_phy_regi2c_lock_apply);
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    if (sleep_modem_phy_init(modem) != ESP_OK) {
+        ESP_LOGE(TAG, "failed to initialize sleep modem phy");
+    }
+#endif // (SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP) || CONFIG_ESP_PHY_HW_SWITCH_RF
     _lock_release(&s_phy_access_lock);
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
 }
 
-void esp_phy_modem_deinit(void)
+void esp_phy_modem_deinit(uint8_t modem)
 {
-#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP || CONFIG_ESP_PHY_HW_SWITCH_RF
     _lock_acquire(&s_phy_access_lock);
 
+    if (s_phy_modem_init_ref == 0) {
+        _lock_release(&s_phy_access_lock);
+        return;
+    }
     s_phy_modem_init_ref--;
     if (s_phy_modem_init_ref == 0) {
 #if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
@@ -530,10 +574,15 @@ void esp_phy_modem_deinit(void)
         phy_init_flag();
 #endif // CONFIG_IDF_TARGET_ESP32C3
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
-        sleep_modem_wifi_modem_state_deinit();
-#endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if (SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP) || CONFIG_ESP_PHY_HW_SWITCH_RF
+#if SOC_PM_REGDMA_MODEM_LINK_PROTECT
+        pau_regdma_unregister_modem_link_protect();
+#endif // SOC_PM_REGDMA_MODEM_LINK_PROTECT
     }
+    sleep_modem_phy_deinit(modem);
+#else
+    }
+#endif // (SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP) || CONFIG_ESP_PHY_HW_SWITCH_RF
     _lock_release(&s_phy_access_lock);
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA || CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
 }
@@ -557,6 +606,7 @@ void esp_mac_bb_pd_mem_init(void)
     }
     _lock_release(&s_phy_access_lock);
 #elif SOC_PM_MODEM_RETENTION_BY_REGDMA
+    esp_phy_fe_sleep_data_init();
     esp_phy_sleep_data_init();
 #endif
 }
@@ -573,6 +623,7 @@ void esp_mac_bb_pd_mem_deinit(void)
     _lock_release(&s_phy_access_lock);
 #elif SOC_PM_MODEM_RETENTION_BY_REGDMA
     esp_phy_sleep_data_deinit();
+    esp_phy_fe_sleep_data_deinit();
 #endif
 }
 
diff --git a/components/esp_wifi/src/wifi_init.c b/components/esp_wifi/src/wifi_init.c
index e50a7f4a19c..7209805dbe5 100644
--- a/components/esp_wifi/src/wifi_init.c
+++ b/components/esp_wifi/src/wifi_init.c
@@ -282,7 +282,7 @@ static esp_err_t wifi_deinit_internal(void)
 #endif
 #endif /* CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
 #ifdef CONFIG_ESP_PHY_ENABLED
-    esp_phy_modem_deinit();
+    esp_phy_modem_deinit(SLEEP_MODEM_WIFI);
 #endif
     s_wifi_inited = false;
 
@@ -475,10 +475,10 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config)
         esp_wifi_mac_pd_mem_init();
 #endif
 #ifdef CONFIG_ESP_PHY_ENABLED
-        esp_phy_modem_init();
+        esp_phy_modem_init(SLEEP_MODEM_WIFI);
 #endif
 #if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
-        if (sleep_modem_wifi_modem_state_enabled()) {
+        if (sleep_modem_wifi_modem_state_is_enabled()) {
             esp_pm_register_skip_light_sleep_callback(sleep_modem_wifi_modem_state_skip_light_sleep);
             esp_wifi_internal_modem_state_configure(true); /* require WiFi to enable automatically receives the beacon */
 #if ESP_MODEM_RF_FLAG_UPDATE_CB_REQUIRED
diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c
index 9e2cca3098b..16cdd05de3c 100644
--- a/components/ieee802154/driver/esp_ieee802154_dev.c
+++ b/components/ieee802154/driver/esp_ieee802154_dev.c
@@ -35,13 +35,15 @@
 #include "esp_pm.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/sleep_retention.h"
-#include "esp_private/sleep_modem.h"
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG
 #define IEEE802154_LINK_OWNER  ENTRY(3)
 #else
 #define IEEE802154_LINK_OWNER  ENTRY(0) | ENTRY(2)
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
 #endif // CONFIG_PM_ENABLE
+#if CONFIG_PM_ENABLE || SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+#include "esp_private/sleep_modem.h"
+#endif // CONFIG_PM_ENABLE || SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
 
 static bool s_rf_closed = true;
 #define CCA_DETECTION_TIME 8
@@ -935,17 +937,31 @@ esp_err_t ieee802154_mac_init(void)
     ret = esp_intr_alloc(ieee802154_periph.irq_id, 0, ieee802154_isr, NULL, &s_ieee802154_isr_handle);
     ESP_RETURN_ON_FALSE(ret == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC init failed");
 
-    ESP_RETURN_ON_FALSE(ieee802154_sleep_init() == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC sleep init failed");
+    ret = ieee802154_sleep_init();
+    if (unlikely(ret != ESP_OK)) {
+        ESP_LOGE(IEEE802154_TAG, "%s(%d): IEEE802154 MAC sleep init failed", __FUNCTION__, __LINE__);
+        if (esp_intr_free(s_ieee802154_isr_handle) != ESP_OK) {
+            ESP_LOGE(IEEE802154_TAG, "%s(%d): IEEE802154 MAC ISR deinit failed", __FUNCTION__, __LINE__);
+        }
+        s_ieee802154_isr_handle = NULL;
+        return ret;
+    }
 
 #if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE
     esp_coex_ieee802154_force_rx_enable(true);
 #endif
 
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    esp_phy_modem_init(SLEEP_MODEM_IEEE802154);
+#endif
     return ret;
 }
 
 esp_err_t ieee802154_mac_deinit(void)
 {
+#if SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    esp_phy_modem_deinit(SLEEP_MODEM_IEEE802154);
+#endif
     esp_err_t ret = ESP_OK;
 #if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE
     esp_coex_ieee802154_force_rx_enable(false);
@@ -953,7 +969,9 @@ esp_err_t ieee802154_mac_deinit(void)
     if (s_ieee802154_isr_handle) {
         ret = esp_intr_free(s_ieee802154_isr_handle);
         s_ieee802154_isr_handle = NULL;
-        ESP_RETURN_ON_FALSE(ret == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC ISR deinit failed");
+        if (unlikely(ret != ESP_OK)) {
+            ESP_LOGE(IEEE802154_TAG, "%s(%d): IEEE802154 MAC ISR deinit failed", __FUNCTION__, __LINE__);
+        }
     }
     ESP_RETURN_ON_FALSE(ieee802154_sleep_deinit() == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC sleep deinit failed");
     return ret;
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 37f25ca57a0..8de8f132074 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1407,10 +1407,18 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_MODEM_STATE
     bool
     default y
 
+config SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_CLK_ICG
     bool
     default y
@@ -1443,10 +1451,6 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
     bool
     default y
 
-config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
-    int
-    default 4
-
 config SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
     bool
     default y
@@ -1455,13 +1459,17 @@ config SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
     bool
     default y
 
+config SOC_PM_PAU_REGDMA_LINK_IDX_PHY
+    int
+    default 4
+
 config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
     bool
     default y
 
 config SOC_PM_RETENTION_MODULE_NUM
     int
-    default 32
+    default 40
 
 config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
     bool
diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h
index 3bc72fa0bb7..70b88570a1c 100644
--- a/components/soc/esp32c5/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h
@@ -55,6 +55,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_BT_BB        = 29,
     SLEEP_RETENTION_MODULE_802154_MAC   = 30,
     SLEEP_RETENTION_MODULE_MODEM_PHY    = 31,
+    SLEEP_RETENTION_MODULE_PHY_FE       = 32,
 
     SLEEP_RETENTION_MODULE_MAX          = SOC_PM_RETENTION_MODULE_NUM - 1
 } periph_retention_module_t;
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index dd1eabff2c1..755291265aa 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -570,9 +570,11 @@
 #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 
+#define SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY (1)
 #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
 /* macro redefine for pass esp_wifi headers md5sum check */
 #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define SOC_PM_REGDMA_MODEM_LINK_PROTECT (1)
 
 #define SOC_PM_SUPPORT_PMU_CLK_ICG          (1)
 #define SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG      (1)
@@ -585,14 +587,14 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (5)
 #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
-#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC  (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 #define SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY (1)
 /** Workaround: software-triggered modem PHY retention uses dedicated WiFi MAC REGDMA, not entry link_sel */
 #define SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND (1)
+#define SOC_PM_PAU_REGDMA_LINK_IDX_PHY      (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 
 #define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
 
-#define SOC_PM_RETENTION_MODULE_NUM         (32)
+#define SOC_PM_RETENTION_MODULE_NUM         (40)
 
 #define SOC_PM_FLASH_KEEP_POWER_IN_LSLP     (1)  /*!<Keep flash on in light sleep to reduce wake latency and current leakage*/
 
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index e031cfeb211..b1fc40a3996 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1143,10 +1143,18 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_MODEM_STATE
     bool
     default y
 
+config SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_CLK_ICG
     bool
     default y
@@ -1183,7 +1191,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
     bool
     default y
 
-config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+config SOC_PM_PAU_REGDMA_LINK_MODEM
     bool
     default y
 
diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h
index 6a17ad6ccfc..134d3500cec 100644
--- a/components/soc/esp32c6/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h
@@ -54,6 +54,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
     SLEEP_RETENTION_MODULE_BT_BB        = 29,
     SLEEP_RETENTION_MODULE_802154_MAC   = 30,
+    SLEEP_RETENTION_MODULE_PHY_FE       = 31,
 
     SLEEP_RETENTION_MODULE_MAX          = SOC_PM_RETENTION_MODULE_NUM - 1
 } periph_retention_module_t;
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 4736fd8ff30..9e14ad1cd28 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -469,9 +469,11 @@
 #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 
-#define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
+#define SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY (1)
+#define SOC_PM_SUPPORT_PMU_MODEM_STATE      (1)
 /* macro redefine for pass esp_wifi headers md5sum check */
 #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define SOC_PM_REGDMA_MODEM_LINK_PROTECT (1)
 
 #define SOC_PM_SUPPORT_PMU_CLK_ICG          (1)
 #define SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG      (1)
@@ -486,7 +488,7 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (4)
 #define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR   (1)
-#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
+#define SOC_PM_PAU_REGDMA_LINK_MODEM      (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 #define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index 7b651651812..eaf89fb890b 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1059,10 +1059,18 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_MODEM_STATE
     bool
     default y
 
+config SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_CLK_ICG
     bool
     default y
@@ -1091,7 +1099,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
     bool
     default y
 
-config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+config SOC_PM_PAU_REGDMA_LINK_MODEM
     bool
     default y
 
diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h
index 1db16def943..24b0883b775 100644
--- a/components/soc/esp32c61/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h
@@ -47,6 +47,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
     SLEEP_RETENTION_MODULE_BT_BB        = 29,
     SLEEP_RETENTION_MODULE_802154_MAC   = 30,
+    SLEEP_RETENTION_MODULE_PHY_FE       = 31,
 
     SLEEP_RETENTION_MODULE_MAX          = SOC_PM_RETENTION_MODULE_NUM - 1
 } periph_retention_module_t;
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index 7d3f851f83d..ed31a89265b 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -437,9 +437,11 @@
 #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 
+#define SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY (1)
 #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
 /* macro redefine for pass esp_wifi headers md5sum check */
 #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define SOC_PM_REGDMA_MODEM_LINK_PROTECT    (1)
 
 #define SOC_PM_SUPPORT_PMU_CLK_ICG          (1)
 #define SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG      (1)
@@ -450,7 +452,7 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (4)
 #define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR   (1)
-#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
+#define SOC_PM_PAU_REGDMA_LINK_MODEM      (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 #define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 36e7b09e47f..57d1f665730 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -1131,7 +1131,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
     bool
     default y
 
-config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+config SOC_PM_PAU_REGDMA_LINK_MODEM
     bool
     default y
 
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index ba4f0d68352..56ca4055c91 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -487,7 +487,7 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (4)
 #define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR   (1)
-#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
+#define SOC_PM_PAU_REGDMA_LINK_MODEM      (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index e331dd01469..0ff9a7f497d 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -1575,7 +1575,11 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
     bool
     default y
 
-config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+config SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
+    bool
+    default y
+
+config SOC_PM_PAU_REGDMA_LINK_IDX_PHY
     int
     default 4
 
@@ -1587,10 +1591,18 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA
     bool
     default y
 
+config SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY
+    bool
+    default y
+
 config SOC_PM_SUPPORT_PMU_MODEM_STATE
     bool
     default y
 
+config SOC_PM_REGDMA_MODEM_LINK_PROTECT
+    bool
+    default y
+
 config SOC_PM_MODEM_STATE_USE_XTAL
     bool
     default y
diff --git a/components/soc/esp32s31/include/soc/retention_periph_defs.h b/components/soc/esp32s31/include/soc/retention_periph_defs.h
index 1f18489dd3e..3dbc6a61039 100644
--- a/components/soc/esp32s31/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32s31/include/soc/retention_periph_defs.h
@@ -78,6 +78,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_802154_MAC   = 50,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 51,
     SLEEP_RETENTION_MODULE_MODEM_PHY    = 52,
+    SLEEP_RETENTION_MODULE_PHY_FE       = 53,
 
     SLEEP_RETENTION_MODULE_ASRC         = 53,
 
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index e0463986b46..170a4d30245 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -582,13 +582,16 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (5)
 #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
-#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC  (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
+#define SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY (1)
+#define SOC_PM_PAU_REGDMA_LINK_IDX_PHY      (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 /** Workaround: software-triggered modem PHY retention uses dedicated WiFi MAC REGDMA, not entry link_sel */
 #define SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND (1)
 
 #define SOC_PM_MODEM_RETENTION_BY_REGDMA           (1)
+#define SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY        (1)
 #define SOC_PM_SUPPORT_PMU_MODEM_STATE             (1)
 #define MAC_SUPPORT_PMU_MODEM_STATE                SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define SOC_PM_REGDMA_MODEM_LINK_PROTECT           (1)
 /* Since SOC APB and MODEM APB on ESP32-S31 are decoupled, XTAL can be used as SOC clock in modem state */
 #define SOC_PM_MODEM_STATE_USE_XTAL                (1)