diff --git a/components/efuse/esp32c61/include/esp_efuse_chip.h b/components/efuse/esp32c61/include/esp_efuse_chip.h index 55f71d09c56..91c80fd0c22 100644 --- a/components/efuse/esp32c61/include/esp_efuse_chip.h +++ b/components/efuse/esp32c61/include/esp_efuse_chip.h @@ -64,10 +64,6 @@ typedef enum { ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c index 8248049ef18..2ee386fe447 100644 --- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c +++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c @@ -300,35 +300,38 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo } #endif // SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK - if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY || + if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 || - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 || -#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 +#endif //#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256 #if SOC_EFUSE_ECDSA_KEY - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY #endif #if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P192) || EFUSE_LL_HAS_ECDSA_KEY_P192 - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 #endif #if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P384) || EFUSE_LL_HAS_ECDSA_KEY_P384 - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L || - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H #endif #if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY #endif #if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 || - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 || + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 #endif #if SOC_KEY_MANAGER_SUPPORTED - purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY #endif - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL || - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG || - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE || - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) { +#if SOC_HMAC_SUPPORTED + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP +#endif + ) { ESP_EFUSE_CHK(esp_efuse_set_key_dis_read(block)); } #if SOC_EFUSE_ECDSA_USE_HARDWARE_K diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c index 4ac209ec54c..f094d16ecfc 100644 --- a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c +++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c @@ -86,35 +86,38 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key) #endif // not CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_get_key_dis_write(num_key)); - if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY || + if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 || - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 || + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 #endif #if SOC_EFUSE_ECDSA_KEY - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY #endif #if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P192) || EFUSE_LL_HAS_ECDSA_KEY_P192 - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 #endif #if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P384) || EFUSE_LL_HAS_ECDSA_KEY_P384 - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L || - purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H || + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L + || purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H #endif #if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY #endif #if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256 - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 || - purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 || + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 + || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 +#endif +#if SOC_HMAC_SUPPORTED + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP #endif - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL || - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG || - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE || #if SOC_KEY_MANAGER_SUPPORTED - purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY || + || purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY #endif - purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) { + ) { TEST_ASSERT_TRUE(esp_efuse_get_key_dis_read(num_key)); #if CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL TEST_ASSERT_EACH_EQUAL_HEX8(0, rd_key, sizeof(rd_key)); @@ -233,7 +236,11 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]") ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, #endif ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, +#if SOC_HMAC_SUPPORTED ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL, +#else + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, +#endif }; int max_keys = EFUSE_BLK_KEY_MAX - EFUSE_BLK_KEY0; @@ -261,9 +268,15 @@ TEST_CASE("Test 2 esp_efuse_write_key for FPGA", "[efuse]") TEST_ASSERT_EQUAL_MESSAGE(EFUSE_BLK_KEY_MAX - EFUSE_BLK_KEY0, esp_efuse_count_unused_key_blocks(), "Efuses should be in initial state"); esp_efuse_purpose_t purpose [] = { +#if SOC_HMAC_SUPPORTED ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG, ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE, ESP_EFUSE_KEY_PURPOSE_HMAC_UP, +#else + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, +#endif ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0, ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1, ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2, @@ -309,7 +322,11 @@ TEST_CASE("Test esp_efuse_write_keys", "[efuse]") #else esp_efuse_purpose_t purpose1[BLOCKS_NEEDED1] = { ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, +#if SOC_HMAC_SUPPORTED ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL +#else + ESP_EFUSE_KEY_PURPOSE_USER +#endif }; #endif uint8_t keys1[BLOCKS_NEEDED1][32] = {{0xEE}}; diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/efuse.h b/components/esp_rom/esp32c61/include/esp32c61/rom/efuse.h index be4bdf9c797..f394ab59f02 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/efuse.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/efuse.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,10 +29,6 @@ typedef enum { ETS_EFUSE_KEY_PURPOSE_USER = 0, ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, - ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, @@ -246,21 +242,6 @@ uint32_t ets_efuse_get_flash_delay_us(void); #define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 #define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) -/** - * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into - * the JTAG_CTRL registers. - * - * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. - * - * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. - * - * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. - * @param key_block Index of a key block containing the source for this key. - * - * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. - */ -int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); - /** * @brief A crc8 algorithm used for MAC addresses in efuse * diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index 20eddb5481e..0d793bbeadc 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -83,18 +83,10 @@ void esp_system_reset_modules_on_exit(void) // all the peripherals are reset at the same time, which triggers a hardware SEC reset. The SEC reset // causes the crypto -> APB path to be reset, but the APB -> crypto path is not reset. This asymmetry // results in the crypto module hanging and refusing all access. - SET_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN); - CLEAR_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN); - SET_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); - CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN); SET_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN); CLEAR_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN); SET_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN); - SET_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); - CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); - SET_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); - CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); diff --git a/components/hal/esp32c61/include/hal/sha_ll.h b/components/hal/esp32c61/include/hal/sha_ll.h index 7f9b945b47e..b97881be80a 100644 --- a/components/hal/esp32c61/include/hal/sha_ll.h +++ b/components/hal/esp32c61/include/hal/sha_ll.h @@ -33,9 +33,7 @@ static inline void sha_ll_reset_register(void) PCR.sha_conf.sha_rst_en = 1; PCR.sha_conf.sha_rst_en = 0; - // Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset - PCR.ds_conf.ds_rst_en = 0; - PCR.hmac_conf.hmac_rst_en = 0; + // Clear reset on ecdsa also, otherwise SHA is held in reset PCR.ecdsa_conf.ecdsa_rst_en = 0; } diff --git a/components/soc/esp32c61/register/soc/pcr_reg.h b/components/soc/esp32c61/register/soc/pcr_reg.h index c6d3a60ba94..b46b97820e0 100644 --- a/components/soc/esp32c61/register/soc/pcr_reg.h +++ b/components/soc/esp32c61/register/soc/pcr_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1166,32 +1166,6 @@ extern "C" { #define PCR_SPI2_CLKM_EN_V 0x00000001U #define PCR_SPI2_CLKM_EN_S 22 -/** PCR_AES_CONF_REG register - * AES configuration register - */ -#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0x9c) -/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable aes clock - */ -#define PCR_AES_CLK_EN (BIT(0)) -#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) -#define PCR_AES_CLK_EN_V 0x00000001U -#define PCR_AES_CLK_EN_S 0 -/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to reset aes module - */ -#define PCR_AES_RST_EN (BIT(1)) -#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) -#define PCR_AES_RST_EN_V 0x00000001U -#define PCR_AES_RST_EN_S 1 -/** PCR_AES_READY : RO; bitpos: [2]; default: 1; - * Query this field after reset aes module - */ -#define PCR_AES_READY (BIT(2)) -#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) -#define PCR_AES_READY_V 0x00000001U -#define PCR_AES_READY_S 2 - /** PCR_SHA_CONF_REG register * SHA configuration register */ @@ -1218,58 +1192,6 @@ extern "C" { #define PCR_SHA_READY_V 0x00000001U #define PCR_SHA_READY_S 2 -/** PCR_RSA_CONF_REG register - * RSA configuration register - */ -#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xa4) -/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rsa clock - */ -#define PCR_RSA_CLK_EN (BIT(0)) -#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) -#define PCR_RSA_CLK_EN_V 0x00000001U -#define PCR_RSA_CLK_EN_S 0 -/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to reset rsa module - */ -#define PCR_RSA_RST_EN (BIT(1)) -#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) -#define PCR_RSA_RST_EN_V 0x00000001U -#define PCR_RSA_RST_EN_S 1 -/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; - * Query this field after reset rsa module - */ -#define PCR_RSA_READY (BIT(2)) -#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) -#define PCR_RSA_READY_V 0x00000001U -#define PCR_RSA_READY_S 2 - -/** PCR_RSA_PD_CTRL_REG register - * RSA power control register - */ -#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xa8) -/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to power down rsa internal memory. - */ -#define PCR_RSA_MEM_PD (BIT(0)) -#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) -#define PCR_RSA_MEM_PD_V 0x00000001U -#define PCR_RSA_MEM_PD_S 0 -/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up rsa internal memory - */ -#define PCR_RSA_MEM_FORCE_PU (BIT(1)) -#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) -#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U -#define PCR_RSA_MEM_FORCE_PU_S 1 -/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down rsa internal memory. - */ -#define PCR_RSA_MEM_FORCE_PD (BIT(2)) -#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) -#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U -#define PCR_RSA_MEM_FORCE_PD_S 2 - /** PCR_ECC_CONF_REG register * ECC configuration register */ @@ -1322,58 +1244,6 @@ extern "C" { #define PCR_ECC_MEM_FORCE_PD_V 0x00000001U #define PCR_ECC_MEM_FORCE_PD_S 2 -/** PCR_DS_CONF_REG register - * DS configuration register - */ -#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xb4) -/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ds clock - */ -#define PCR_DS_CLK_EN (BIT(0)) -#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) -#define PCR_DS_CLK_EN_V 0x00000001U -#define PCR_DS_CLK_EN_S 0 -/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to reset ds module - */ -#define PCR_DS_RST_EN (BIT(1)) -#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) -#define PCR_DS_RST_EN_V 0x00000001U -#define PCR_DS_RST_EN_S 1 -/** PCR_DS_READY : RO; bitpos: [2]; default: 1; - * Query this field after reset ds module - */ -#define PCR_DS_READY (BIT(2)) -#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) -#define PCR_DS_READY_V 0x00000001U -#define PCR_DS_READY_S 2 - -/** PCR_HMAC_CONF_REG register - * HMAC configuration register - */ -#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xb8) -/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable hmac clock - */ -#define PCR_HMAC_CLK_EN (BIT(0)) -#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) -#define PCR_HMAC_CLK_EN_V 0x00000001U -#define PCR_HMAC_CLK_EN_S 0 -/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to reset hmac module - */ -#define PCR_HMAC_RST_EN (BIT(1)) -#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) -#define PCR_HMAC_RST_EN_V 0x00000001U -#define PCR_HMAC_RST_EN_S 1 -/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; - * Query this field after reset hmac module - */ -#define PCR_HMAC_READY (BIT(2)) -#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) -#define PCR_HMAC_READY_V 0x00000001U -#define PCR_HMAC_READY_S 2 - /** PCR_ECDSA_CONF_REG register * ECDSA configuration register */ diff --git a/components/soc/esp32c61/register/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h index 97b48ecdb5e..180c5c722bd 100644 --- a/components/soc/esp32c61/register/soc/pcr_struct.h +++ b/components/soc/esp32c61/register/soc/pcr_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -997,28 +997,6 @@ typedef union { uint32_t val; } pcr_spi2_clkm_conf_reg_t; -/** Type of aes_conf register - * AES configuration register - */ -typedef union { - struct { - /** aes_clk_en : R/W; bitpos: [0]; default: 1; - * Set 1 to enable aes clock - */ - uint32_t aes_clk_en:1; - /** aes_rst_en : R/W; bitpos: [1]; default: 0; - * Set 1 to reset aes module - */ - uint32_t aes_rst_en:1; - /** aes_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset aes module - */ - uint32_t aes_ready:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_aes_conf_reg_t; - /** Type of sha_conf register * SHA configuration register */ @@ -1041,50 +1019,6 @@ typedef union { uint32_t val; } pcr_sha_conf_reg_t; -/** Type of rsa_conf register - * RSA configuration register - */ -typedef union { - struct { - /** rsa_clk_en : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rsa clock - */ - uint32_t rsa_clk_en:1; - /** rsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 1 to reset rsa module - */ - uint32_t rsa_rst_en:1; - /** rsa_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset rsa module - */ - uint32_t rsa_ready:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_rsa_conf_reg_t; - -/** Type of rsa_pd_ctrl register - * RSA power control register - */ -typedef union { - struct { - /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to power down rsa internal memory. - */ - uint32_t rsa_mem_pd:1; - /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up rsa internal memory - */ - uint32_t rsa_mem_force_pu:1; - /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down rsa internal memory. - */ - uint32_t rsa_mem_force_pd:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_rsa_pd_ctrl_reg_t; - /** Type of ecc_conf register * ECC configuration register */ @@ -1129,50 +1063,6 @@ typedef union { uint32_t val; } pcr_ecc_pd_ctrl_reg_t; -/** Type of ds_conf register - * DS configuration register - */ -typedef union { - struct { - /** ds_clk_en : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ds clock - */ - uint32_t ds_clk_en:1; - /** ds_rst_en : R/W; bitpos: [1]; default: 0; - * Set 1 to reset ds module - */ - uint32_t ds_rst_en:1; - /** ds_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset ds module - */ - uint32_t ds_ready:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_ds_conf_reg_t; - -/** Type of hmac_conf register - * HMAC configuration register - */ -typedef union { - struct { - /** hmac_clk_en : R/W; bitpos: [0]; default: 1; - * Set 1 to enable hmac clock - */ - uint32_t hmac_clk_en:1; - /** hmac_rst_en : R/W; bitpos: [1]; default: 0; - * Set 1 to reset hmac module - */ - uint32_t hmac_rst_en:1; - /** hmac_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset hmac module - */ - uint32_t hmac_ready:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_hmac_conf_reg_t; - /** Type of ecdsa_conf register * ECDSA configuration register */ @@ -1952,14 +1842,14 @@ typedef struct { volatile pcr_gdma_conf_reg_t gdma_conf; volatile pcr_spi2_conf_reg_t spi2_conf; volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; - volatile pcr_aes_conf_reg_t aes_conf; + uint32_t reserved_9c; volatile pcr_sha_conf_reg_t sha_conf; - volatile pcr_rsa_conf_reg_t rsa_conf; - volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + uint32_t reserved_a4; + uint32_t reserved_a8; volatile pcr_ecc_conf_reg_t ecc_conf; volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; - volatile pcr_ds_conf_reg_t ds_conf; - volatile pcr_hmac_conf_reg_t hmac_conf; + uint32_t reserved_b4; + uint32_t reserved_b8; volatile pcr_ecdsa_conf_reg_t ecdsa_conf; volatile pcr_iomux_conf_reg_t iomux_conf; volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;