diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
index b1843a958e7..fa28b6948d7 100644
--- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
+++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,6 +54,7 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
     uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
     if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
+
         /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
          * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
          * command memory */
@@ -70,21 +71,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
     }
 #endif
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-        /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's
-         * located in TOP domain) is used to fix the issue where the modem
-         * module fails to transmit and receive packets due to the loss of The
-         * modem root clock caused by automatic clock gating during soc root
-         * clock source switching. For detailed information, refer to IDF-11064 */
-    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
-        const static sleep_retention_entries_config_t rootclk_workaround[] = {
-            [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) }
-        };
-        err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
-        ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority");
-    }
-#endif
-
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
 }
diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c
index c151b3d1146..28b20301191 100644
--- a/components/esp_system/port/soc/esp32c5/clk.c
+++ b/components/esp_system/port/soc/esp32c5/clk.c
@@ -19,9 +19,7 @@
 #include "soc/rtc.h"
 #include "soc/rtc_periph.h"
 #include "soc/i2s_reg.h"
-#include "soc/chip_revision.h"
 #include "esp_cpu.h"
-#include "hal/efuse_hal.h"
 #include "hal/wdt_hal.h"
 #include "hal/clk_tree_ll.h"
 #if SOC_MODEM_CLOCK_SUPPORTED
@@ -261,13 +259,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
 #endif
 
-    /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
-     * the issue where the modem module fails to transmit and receive packets
-     * due to the loss of the modem root clock caused by automatic clock gating
-     * during soc root clock source switching. For detailed information, refer
-     * to IDF-11064. */
-    clk_ll_soc_root_clk_auto_gating_bypass(true);
-
     soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
     if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1)          \
             && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)    \