From 1862fdec74829d56a0a525754225035b3ecdd99b Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 27 Oct 2025 19:09:27 +0800 Subject: [PATCH 1/2] refactor(gpio): split GPIO HAL into separate component cleaned up some includes in GPIO peripheral files --- components/bootloader_support/CMakeLists.txt | 6 +- .../src/bootloader_flash_config_esp32.c | 1 - .../src/bootloader_flash_config_esp32c2.c | 1 - .../src/bootloader_flash_config_esp32c3.c | 1 - .../src/bootloader_flash_config_esp32c5.c | 1 - .../src/bootloader_flash_config_esp32c6.c | 1 - .../src/bootloader_flash_config_esp32c61.c | 1 - .../src/bootloader_flash_config_esp32h2.c | 1 - .../src/bootloader_flash_config_esp32p4.c | 2 +- .../src/bootloader_common.c | 2 +- .../src/bootloader_common_loader.c | 2 - .../src/bootloader_random_esp32s2.c | 1 - .../src/esp32/bootloader_esp32.c | 1 - .../src/esp32s2/bootloader_esp32s2.c | 1 - .../test_driver_utils/test_spi_utils.c | 4 +- .../legacy_i2c_driver/main/test_i2c.c | 4 +- components/esp_coex/src/coexist.c | 1 + components/esp_driver_gpio/CMakeLists.txt | 1 + components/esp_driver_gpio/linker.lf | 2 +- components/esp_driver_gpio/src/dedic_gpio.c | 2 +- components/esp_driver_gpio/src/rtc_io.c | 2 +- .../test_apps/.build-test-rules.yml | 3 + .../test_apps/gpio/main/test_gpio.c | 1 - .../test_apps/gpio/main/test_rtcio.c | 2 +- .../main/test_dedicated_gpio.c | 2 +- .../test_apps/.build-test-rules.yml | 1 + components/esp_driver_sdio/src/sdio_slave.c | 1 - components/esp_driver_sdm/CMakeLists.txt | 2 + components/esp_driver_sdm/src/sdm.c | 2 +- .../test_apps/.build-test-rules.yml | 1 + .../test_apps/sigma_delta/main/test_sdm.cpp | 2 +- .../test_apps/master/main/test_spi_master.c | 1 - .../test_apps/master/main/test_spi_sio.c | 2 +- .../esp_eth/src/mac/esp_eth_mac_esp_gpio.c | 1 - components/esp_hal_gpio/CMakeLists.txt | 24 +++++++ components/esp_hal_gpio/README.md | 9 +++ .../esp32/include/hal/gpio_ll.h | 18 ++--- .../esp32/include/hal/rtc_io_ll.h | 6 +- .../esp32/include/hal/sdm_ll.h | 8 +-- .../esp32/rtc_io_periph.c | 4 +- .../esp32}/sdm_periph.c | 2 +- .../esp32c2/dedic_gpio_periph.c | 2 +- .../esp32c2/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32c2/include/hal/gpio_ll.h | 15 +++-- .../esp32c3}/dedic_gpio_periph.c | 2 +- .../esp32c3/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32c3/include/hal/gpio_ll.h | 12 ++-- .../esp32c3/include/hal/sdm_ll.h | 8 +-- .../esp32c3/sdm_periph.c | 2 +- .../esp32c5/dedic_gpio_periph.c | 2 +- .../esp32c5}/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32c5/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32c5/include/hal/gpio_ll.h | 14 ++-- .../esp32c5/include/hal/rtc_io_ll.h | 4 +- .../esp32c5/include/hal/sdm_ll.h | 8 +-- .../esp32c5/rtc_io_periph.c | 3 +- .../esp32c5/sdm_periph.c | 2 +- .../esp32c6/dedic_gpio_periph.c | 2 +- .../esp32c6}/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32c6/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32c6/include/hal/gpio_ll.h | 12 ++-- .../esp32c6/include/hal/rtc_io_ll.h | 4 +- .../esp32c6/include/hal/sdm_ll.h | 8 +-- .../esp32c6/rtc_io_periph.c | 3 +- .../esp32c6/sdm_periph.c | 2 +- .../esp32c61/dedic_gpio_periph.c | 2 +- .../esp32c61/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32c61/include/hal/gpio_etm_ll.h | 0 .../esp32c61/include/hal/gpio_ll.h | 12 ++-- .../esp32c61/include/hal/rtc_io_ll.h | 4 +- .../esp32c61/rtc_io_periph.c | 3 +- .../esp32h2}/dedic_gpio_periph.c | 2 +- .../esp32h2/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32h2/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32h2/include/hal/gpio_ll.h | 12 ++-- .../esp32h2/include/hal/rtc_io_ll.h | 6 +- .../esp32h2}/include/hal/sdm_ll.h | 8 +-- .../esp32h2/rtc_io_periph.c | 3 +- .../esp32h2/sdm_periph.c | 2 +- .../esp32h21/dedic_gpio_periph.c | 2 +- .../esp32h21/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32h21/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32h21/include/hal/gpio_ll.h | 12 ++-- .../esp32h21/include/hal/rtc_io_ll.h | 6 +- .../esp32h21}/include/hal/sdm_ll.h | 8 +-- .../esp32h21/rtc_io_periph.c | 3 +- .../esp32h21}/sdm_periph.c | 4 +- .../esp32h4/dedic_gpio_periph.c | 2 +- .../esp32h4/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32h4/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32h4/include/hal/gpio_ll.h | 13 ++-- .../esp32h4/include/hal/rtc_io_ll.h | 4 +- .../esp32h4}/include/hal/sdm_ll.h | 8 +-- .../esp32h4/rtc_io_periph.c | 3 +- .../esp32h4}/sdm_periph.c | 4 +- .../esp32p4/dedic_gpio_periph.c | 2 +- .../esp32p4/include/hal/dedic_gpio_cpu_ll.h | 8 +-- .../esp32p4/include/hal/gpio_etm_ll.h | 0 .../include/hal/gpio_glitch_filter_ll.h | 0 .../esp32p4/include/hal/gpio_ll.h | 11 ++-- .../esp32p4/include/hal/rtc_io_ll.h | 4 +- .../esp32p4}/include/hal/sdm_ll.h | 8 +-- .../esp32p4/rtc_io_periph.c | 3 +- .../esp32p4/sdm_periph.c | 2 +- .../esp32s2/dedic_gpio_periph.c | 2 +- .../esp32s2/include/hal/dedic_gpio_cpu_ll.h | 0 .../esp32s2/include/hal/dedic_gpio_ll.h | 4 +- .../esp32s2/include/hal/gpio_ll.h | 12 ++-- .../esp32s2/include/hal/rtc_io_ll.h | 6 +- .../esp32s2/include/hal/sdm_ll.h | 8 +-- .../esp32s2/rtc_io_periph.c | 4 +- .../esp32s2}/sdm_periph.c | 2 +- .../esp32s3/dedic_gpio_periph.c | 2 +- .../esp32s3/include/hal/dedic_gpio_cpu_ll.h | 0 .../esp32s3/include/hal/dedic_gpio_ll.h | 0 .../esp32s3/include/hal/gpio_ll.h | 13 ++-- .../esp32s3/include/hal/rtc_io_ll.h | 11 ++-- .../esp32s3/include/hal/sdm_ll.h | 8 +-- .../esp32s3/rtc_io_periph.c | 4 +- .../esp32s3}/sdm_periph.c | 2 +- .../esp32s31/include/hal/gpio_caps.h | 9 +++ .../esp32s31/include/hal/gpio_ll.h | 65 +++++++------------ components/{hal => esp_hal_gpio}/gpio_hal.c | 1 - .../include/hal}/dedic_gpio_periph.h | 0 .../include/hal/gpio_hal.h | 4 +- .../include/hal/gpio_types.h | 0 .../include/hal/rtc_io_hal.h | 2 +- .../include/hal}/rtc_io_periph.h | 6 -- .../include/hal/rtc_io_types.h | 2 +- .../include/hal/sdm_hal.h | 0 .../include/hal}/sdm_periph.h | 0 .../include/hal/sdm_types.h | 0 components/{hal => esp_hal_gpio}/rtc_io_hal.c | 0 components/{hal => esp_hal_gpio}/sdm_hal.c | 0 components/esp_hw_support/CMakeLists.txt | 2 +- components/esp_hw_support/linker.lf | 5 ++ .../esp_hw_support/port/esp32/rtc_clk.c | 2 +- .../esp_hw_support/port/esp32/rtc_init.c | 2 +- components/esp_hw_support/sleep_gpio.c | 2 +- .../test_apps/rtc_clk/main/test_rtc_clk.c | 4 +- .../test_apps/esp_pm/main/CMakeLists.txt | 2 +- .../esp_pm/test_apps/esp_pm/main/test_pm.c | 5 +- components/esp_psram/CMakeLists.txt | 2 +- .../esp_system/port/soc/esp32/reset_reason.c | 1 - .../port/soc/esp32/system_internal.c | 3 +- .../port/soc/esp32c2/reset_reason.c | 1 - .../port/soc/esp32c2/system_internal.c | 1 - .../port/soc/esp32c3/reset_reason.c | 1 - .../port/soc/esp32c3/system_internal.c | 1 - .../port/soc/esp32c5/reset_reason.c | 1 - .../port/soc/esp32c5/system_internal.c | 1 - .../port/soc/esp32c6/reset_reason.c | 1 - .../port/soc/esp32c6/system_internal.c | 1 - .../port/soc/esp32c61/reset_reason.c | 1 - .../port/soc/esp32c61/system_internal.c | 1 - .../port/soc/esp32h2/reset_reason.c | 1 - .../port/soc/esp32h2/system_internal.c | 1 - .../port/soc/esp32h21/reset_reason.c | 1 - .../port/soc/esp32h21/system_internal.c | 1 - .../port/soc/esp32h4/reset_reason.c | 1 - .../port/soc/esp32h4/system_internal.c | 1 - .../port/soc/esp32p4/reset_reason.c | 1 - .../port/soc/esp32p4/system_internal.c | 1 - .../port/soc/esp32s2/reset_reason.c | 1 - .../port/soc/esp32s2/system_internal.c | 1 - .../port/soc/esp32s3/reset_reason.c | 1 - .../port/soc/esp32s3/system_internal.c | 1 - .../esp_system_unity_tests/main/test_sleep.c | 1 - components/espcoredump/src/core_dump_uart.c | 1 - components/hal/CMakeLists.txt | 12 ---- components/hal/linker.lf | 2 - components/soc/CMakeLists.txt | 12 ---- components/soc/esp32/gpio_periph.c | 1 + components/soc/esp32/sdio_slave_periph.c | 1 - components/soc/esp32c2/gpio_periph.c | 1 + components/soc/esp32c3/gpio_periph.c | 1 + components/soc/esp32c5/gpio_periph.c | 1 + components/soc/esp32c6/gpio_periph.c | 1 + components/soc/esp32c61/gpio_periph.c | 1 + components/soc/esp32h2/gpio_periph.c | 1 + components/soc/esp32h21/gpio_periph.c | 1 + components/soc/esp32h4/gpio_periph.c | 1 + components/soc/esp32p4/gpio_periph.c | 1 + components/soc/esp32s2/gpio_periph.c | 1 + components/soc/esp32s3/gpio_periph.c | 1 + components/soc/include/soc/gpio_periph.h | 4 -- components/soc/include/soc/rtc_periph.h | 1 - components/spi_flash/CMakeLists.txt | 4 +- docs/doxygen/Doxyfile | 6 +- .../main/ulp_riscv_ds18b20_example_main.c | 1 - 195 files changed, 367 insertions(+), 369 deletions(-) create mode 100644 components/esp_hal_gpio/CMakeLists.txt create mode 100644 components/esp_hal_gpio/README.md rename components/{hal => esp_hal_gpio}/esp32/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32/include/hal/rtc_io_ll.h (98%) rename components/{hal => esp_hal_gpio}/esp32/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32/rtc_io_periph.c (98%) rename components/{soc/esp32s3 => esp_hal_gpio/esp32}/sdm_periph.c (97%) rename components/{soc => esp_hal_gpio}/esp32c2/dedic_gpio_periph.c (96%) rename components/{hal => esp_hal_gpio}/esp32c2/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c2/include/hal/gpio_ll.h (99%) rename components/{soc/esp32h2 => esp_hal_gpio/esp32c3}/dedic_gpio_periph.c (96%) rename components/{hal => esp_hal_gpio}/esp32c3/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c3/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32c3/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32c3/sdm_periph.c (95%) rename components/{soc => esp_hal_gpio}/esp32c5/dedic_gpio_periph.c (96%) rename components/{hal/esp32c6 => esp_hal_gpio/esp32c5}/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c5/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c5/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c5/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32c5/include/hal/rtc_io_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c5/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32c5/rtc_io_periph.c (92%) rename components/{soc => esp_hal_gpio}/esp32c5/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32c6/dedic_gpio_periph.c (96%) rename components/{hal/esp32c5 => esp_hal_gpio/esp32c6}/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c6/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c6/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c6/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32c6/include/hal/rtc_io_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c6/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32c6/rtc_io_periph.c (92%) rename components/{soc => esp_hal_gpio}/esp32c6/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32c61/dedic_gpio_periph.c (96%) rename components/{hal => esp_hal_gpio}/esp32c61/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c61/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32c61/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32c61/include/hal/rtc_io_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32c61/rtc_io_periph.c (92%) rename components/{soc/esp32c3 => esp_hal_gpio/esp32h2}/dedic_gpio_periph.c (96%) rename components/{hal => esp_hal_gpio}/esp32h2/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h2/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h2/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h2/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32h2/include/hal/rtc_io_ll.h (99%) rename components/{hal/esp32p4 => esp_hal_gpio/esp32h2}/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32h2/rtc_io_periph.c (92%) rename components/{soc => esp_hal_gpio}/esp32h2/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32h21/dedic_gpio_periph.c (96%) rename components/{hal => esp_hal_gpio}/esp32h21/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h21/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h21/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h21/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32h21/include/hal/rtc_io_ll.h (99%) rename components/{hal/esp32h4 => esp_hal_gpio/esp32h21}/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32h21/rtc_io_periph.c (91%) rename components/{soc/esp32h4 => esp_hal_gpio/esp32h21}/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32h4/dedic_gpio_periph.c (98%) rename components/{hal => esp_hal_gpio}/esp32h4/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h4/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h4/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32h4/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32h4/include/hal/rtc_io_ll.h (100%) rename components/{hal/esp32h21 => esp_hal_gpio/esp32h4}/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32h4/rtc_io_periph.c (93%) rename components/{soc/esp32h21 => esp_hal_gpio/esp32h4}/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32p4/dedic_gpio_periph.c (98%) rename components/{hal => esp_hal_gpio}/esp32p4/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32p4/include/hal/gpio_etm_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32p4/include/hal/gpio_glitch_filter_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32p4/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32p4/include/hal/rtc_io_ll.h (100%) rename components/{hal/esp32h2 => esp_hal_gpio/esp32p4}/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32p4/rtc_io_periph.c (95%) rename components/{soc => esp_hal_gpio}/esp32p4/sdm_periph.c (98%) rename components/{soc => esp_hal_gpio}/esp32s2/dedic_gpio_periph.c (97%) rename components/{hal => esp_hal_gpio}/esp32s2/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32s2/include/hal/dedic_gpio_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32s2/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32s2/include/hal/rtc_io_ll.h (98%) rename components/{hal => esp_hal_gpio}/esp32s2/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32s2/rtc_io_periph.c (99%) rename components/{soc/esp32 => esp_hal_gpio/esp32s2}/sdm_periph.c (97%) rename components/{soc => esp_hal_gpio}/esp32s3/dedic_gpio_periph.c (98%) rename components/{hal => esp_hal_gpio}/esp32s3/include/hal/dedic_gpio_cpu_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32s3/include/hal/dedic_gpio_ll.h (100%) rename components/{hal => esp_hal_gpio}/esp32s3/include/hal/gpio_ll.h (99%) rename components/{hal => esp_hal_gpio}/esp32s3/include/hal/rtc_io_ll.h (98%) rename components/{hal => esp_hal_gpio}/esp32s3/include/hal/sdm_ll.h (100%) rename components/{soc => esp_hal_gpio}/esp32s3/rtc_io_periph.c (99%) rename components/{soc/esp32s2 => esp_hal_gpio/esp32s3}/sdm_periph.c (97%) create mode 100644 components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h rename components/{hal => esp_hal_gpio}/esp32s31/include/hal/gpio_ll.h (94%) rename components/{hal => esp_hal_gpio}/gpio_hal.c (99%) rename components/{soc/include/soc => esp_hal_gpio/include/hal}/dedic_gpio_periph.h (100%) rename components/{hal => esp_hal_gpio}/include/hal/gpio_hal.h (99%) rename components/{hal => esp_hal_gpio}/include/hal/gpio_types.h (100%) rename components/{hal => esp_hal_gpio}/include/hal/rtc_io_hal.h (99%) rename components/{soc/include/soc => esp_hal_gpio/include/hal}/rtc_io_periph.h (95%) rename components/{hal => esp_hal_gpio}/include/hal/rtc_io_types.h (92%) rename components/{hal => esp_hal_gpio}/include/hal/sdm_hal.h (100%) rename components/{soc/include/soc => esp_hal_gpio/include/hal}/sdm_periph.h (100%) rename components/{hal => esp_hal_gpio}/include/hal/sdm_types.h (100%) rename components/{hal => esp_hal_gpio}/rtc_io_hal.c (100%) rename components/{hal => esp_hal_gpio}/sdm_hal.c (100%) diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index cbfffd533c6..8fcccfe2489 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -72,7 +72,8 @@ endif() if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM) set(include_dirs "include" "bootloader_flash/include" "private_include") - set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py esp_hal_wdt) + set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py) + list(APPEND priv_requires esp_hal_wdt esp_hal_gpio) list(APPEND srcs "src/bootloader_init.c" "src/bootloader_clock_loader.c" @@ -88,7 +89,8 @@ else() set(include_dirs "include" "bootloader_flash/include") set(priv_include_dirs "private_include") # heap is required for `heap_memory_layout.h` header - set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py esp_hal_wdt) + set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py) + list(APPEND priv_requires esp_hal_wdt esp_hal_gpio) endif() if(BOOTLOADER_BUILD) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index ccfec0a8b03..eefcbfaf3fb 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -13,7 +13,6 @@ #include "esp_rom_efuse.h" #include "esp32/rom/spi_flash.h" #include "esp32/rom/cache.h" -#include "soc/gpio_periph.h" #include "soc/efuse_reg.h" #include "soc/spi_reg.h" #include "soc/dport_reg.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index 374201d6819..38bcb84ebf2 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -11,7 +11,6 @@ #include "esp_log.h" #include "esp_rom_gpio.h" #include "esp32c2/rom/spi_flash.h" -#include "soc/gpio_periph.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index a13f1460e61..98c346f5aa7 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -12,7 +12,6 @@ #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp32c3/rom/spi_flash.h" -#include "soc/gpio_periph.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c index 6563eef671d..f9b711496a9 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c @@ -12,7 +12,6 @@ #include "esp_rom_gpio.h" #include "esp32c5/rom/spi_flash.h" #include "esp32c5/rom/efuse.h" -#include "soc/gpio_periph.h" #include "soc/io_mux_reg.h" #include "esp_rom_efuse.h" #include "soc/efuse_reg.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 5e77f5c05a5..759bac5f9bd 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -11,7 +11,6 @@ #include "esp_log.h" #include "esp_rom_gpio.h" #include "esp32c6/rom/spi_flash.h" -#include "soc/gpio_periph.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index b3e27a338dd..e5331aaae20 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -11,7 +11,6 @@ #include "esp_log.h" #include "esp_rom_gpio.h" #include "esp32c61/rom/spi_flash.h" -#include "soc/gpio_periph.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index c1053d99a2b..f1b79e9b8e1 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -11,7 +11,6 @@ #include "esp_log.h" #include "esp_rom_gpio.h" #include "esp32h2/rom/spi_flash.h" -#include "soc/gpio_periph.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index d410dabeac4..8722ac904bd 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -10,7 +10,7 @@ #include "esp_err.h" #include "esp_log.h" #include "esp_rom_gpio.h" -#include "soc/gpio_periph.h" +#include "soc/spi_pins.h" #include "soc/spi_mem_reg.h" #include "flash_qio_mode.h" #include "bootloader_flash_config.h" diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c index d2101287a98..edf3d5005e2 100644 --- a/components/bootloader_support/src/bootloader_common.c +++ b/components/bootloader_support/src/bootloader_common.c @@ -17,7 +17,7 @@ #include "bootloader_flash_priv.h" #include "bootloader_common.h" #include "bootloader_utility.h" -#include "soc/gpio_periph.h" +#include "soc/soc_caps.h" #include "soc/rtc.h" #include "soc/efuse_reg.h" #include "hal/gpio_ll.h" diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index 1ca7b4c0695..d4cdfab93f9 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -14,12 +14,10 @@ #include "esp_flash_partitions.h" #include "bootloader_flash.h" #include "bootloader_common.h" -#include "soc/gpio_periph.h" #include "soc/rtc.h" #include "soc/efuse_reg.h" #include "soc/chip_revision.h" #include "hal/efuse_hal.h" -#include "hal/gpio_ll.h" #include "esp_image_format.h" #include "bootloader_sha.h" #include "sys/param.h" diff --git a/components/bootloader_support/src/bootloader_random_esp32s2.c b/components/bootloader_support/src/bootloader_random_esp32s2.c index 6adedb7ed1f..b946897188b 100644 --- a/components/bootloader_support/src/bootloader_random_esp32s2.c +++ b/components/bootloader_support/src/bootloader_random_esp32s2.c @@ -10,7 +10,6 @@ #include "soc/dport_reg.h" #include "soc/syscon_reg.h" #include "esp_log.h" -#include "soc/io_mux_reg.h" #include "soc/apb_saradc_reg.h" #include "esp_private/regi2c_ctrl.h" #include "hal/adc_ll.h" diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index 31aea4aa9eb..fef1057ef22 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -21,7 +21,6 @@ #include "esp_cpu.h" #include "soc/dport_reg.h" #include "soc/efuse_reg.h" -#include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" #include "soc/rtc.h" diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index ce82ca7d7ac..9773d971c81 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -8,7 +8,6 @@ #include "sdkconfig.h" #include "bootloader_common.h" #include "soc/efuse_reg.h" -#include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" diff --git a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c index c49b4ef215e..e4e3e9e69ae 100644 --- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c +++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c @@ -8,9 +8,9 @@ #include "esp_log.h" #include "driver/gpio.h" #include "esp_private/gpio.h" -#include "hal/gpio_hal.h" -#include "hal/spi_ll.h" #include "esp_rom_gpio.h" +#include "hal/gpio_ll.h" +#include "hal/spi_ll.h" const char MASTER_TAG[] = "test_master"; const char SLAVE_TAG[] = "test_slave"; diff --git a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c index 6caf72da90f..0f56a9add0b 100644 --- a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c +++ b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c @@ -11,19 +11,19 @@ #include "driver/i2c.h" #include "esp_attr.h" #include "esp_log.h" -#include "soc/gpio_periph.h" #include "hal/i2c_periph.h" #include "esp_system.h" #include "soc/uart_struct.h" #include "esp_private/periph_ctrl.h" #include "esp_private/uart_share_hw_ctrl.h" #include "esp_rom_gpio.h" -#include "hal/gpio_hal.h" +#include "hal/gpio_types.h" #include "hal/uart_ll.h" #include "hal/i2c_types.h" #include "soc/uart_periph.h" #include "test_utils.h" #include "esp_private/gpio.h" +#include "driver/gpio.h" #define DATA_LENGTH 512 /*! 0 depends_components: - esp_driver_gpio + - esp_hal_gpio diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c index 286720482de..706e355bc9c 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c @@ -22,7 +22,6 @@ #include "unity_test_utils.h" #include "driver/gpio.h" #include "hal/gpio_ll.h" -#include "soc/gpio_periph.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c index fd0735b3e88..ebc87b58a03 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c @@ -16,7 +16,7 @@ #include "freertos/queue.h" #include "esp_err.h" #include "esp_log.h" -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" #include "soc/soc_caps.h" #include "hal/rtc_io_ll.h" diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index f0e0d0e1227..097bcd08a02 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -12,7 +12,7 @@ #include "unity_test_utils.h" #include "esp_rom_sys.h" #include "soc/soc_caps_full.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" #include "hal/dedic_gpio_cpu_ll.h" #include "driver/gpio.h" #include "driver/dedic_gpio.h" diff --git a/components/esp_driver_i2c/test_apps/.build-test-rules.yml b/components/esp_driver_i2c/test_apps/.build-test-rules.yml index 5436c0467ea..b078f120eff 100644 --- a/components/esp_driver_i2c/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2c/test_apps/.build-test-rules.yml @@ -5,3 +5,4 @@ components/esp_driver_i2c/test_apps/i2c_test_apps: - if: SOC_I2C_SUPPORTED != 1 depends_components: - esp_driver_i2c + - esp_hal_i2c diff --git a/components/esp_driver_sdio/src/sdio_slave.c b/components/esp_driver_sdio/src/sdio_slave.c index 3f2f8f788ba..d243909dd11 100644 --- a/components/esp_driver_sdio/src/sdio_slave.c +++ b/components/esp_driver_sdio/src/sdio_slave.c @@ -78,7 +78,6 @@ The driver of FIFOs works as below: #include #include "soc/soc_memory_layout.h" -#include "soc/gpio_periph.h" #include "soc/soc_caps.h" #include "soc/sdio_slave_periph.h" #include "esp_cpu.h" diff --git a/components/esp_driver_sdm/CMakeLists.txt b/components/esp_driver_sdm/CMakeLists.txt index 4656678a227..f1778957293 100644 --- a/components/esp_driver_sdm/CMakeLists.txt +++ b/components/esp_driver_sdm/CMakeLists.txt @@ -7,6 +7,7 @@ endif() set(srcs) set(public_include "include") set(priv_requires esp_pm esp_driver_gpio) +set(requires esp_hal_gpio) if(CONFIG_SOC_SDM_SUPPORTED) list(APPEND srcs "src/sdm.c") endif() @@ -14,5 +15,6 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} PRIV_REQUIRES "${priv_requires}" + REQUIRES "${requires}" LDFRAGMENTS "linker.lf" ) diff --git a/components/esp_driver_sdm/src/sdm.c b/components/esp_driver_sdm/src/sdm.c index 1a92e2a85df..0cc91805a43 100644 --- a/components/esp_driver_sdm/src/sdm.c +++ b/components/esp_driver_sdm/src/sdm.c @@ -23,7 +23,7 @@ #include "esp_clk_tree.h" #include "driver/gpio.h" #include "driver/sdm.h" -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "hal/sdm_hal.h" #include "hal/sdm_ll.h" #include "hal/hal_utils.h" diff --git a/components/esp_driver_sdm/test_apps/.build-test-rules.yml b/components/esp_driver_sdm/test_apps/.build-test-rules.yml index 77a14a95759..851804067c0 100644 --- a/components/esp_driver_sdm/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdm/test_apps/.build-test-rules.yml @@ -6,3 +6,4 @@ components/esp_driver_sdm/test_apps/sigma_delta: depends_components: - esp_driver_gpio - esp_driver_sdm + - esp_hal_gpio diff --git a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp index c10468a61e5..4940c0c218e 100644 --- a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp +++ b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp @@ -10,7 +10,7 @@ #include "freertos/task.h" #include "unity.h" #include "driver/sdm.h" -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "esp_attr.h" TEST_CASE("sdm_channel_install_uninstall", "[sdm]") diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index f3a4daedf88..5351de74cdc 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -13,7 +13,6 @@ #include "sys/param.h" #include "driver/gpio.h" #include "hal/spi_ll.h" // for SPI_LL_SUPPORT_CLK_SRC_PRE_DIV -#include "soc/gpio_periph.h" #include "soc/spi_periph.h" #include "soc/soc_memory_layout.h" #include "esp_private/cache_utils.h" diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c b/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c index 8df60daa135..07c5111995a 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c @@ -23,9 +23,9 @@ #include "esp_heap_caps.h" #include "esp_log.h" #include "soc/spi_periph.h" +#include "soc/gpio_struct.h" #include "test_utils.h" #include "test_spi_utils.h" -#include "soc/gpio_periph.h" #include "hal/spi_ll.h" diff --git a/components/esp_eth/src/mac/esp_eth_mac_esp_gpio.c b/components/esp_eth/src/mac/esp_eth_mac_esp_gpio.c index be0a1c2dc49..0bc44ef5880 100644 --- a/components/esp_eth/src/mac/esp_eth_mac_esp_gpio.c +++ b/components/esp_eth/src/mac/esp_eth_mac_esp_gpio.c @@ -12,7 +12,6 @@ #include "soc/soc_caps.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" -#include "soc/gpio_periph.h" #include "hal/emac_periph.h" #include "esp_private/gpio.h" #include "esp_private/eth_mac_esp_gpio.h" diff --git a/components/esp_hal_gpio/CMakeLists.txt b/components/esp_hal_gpio/CMakeLists.txt new file mode 100644 index 00000000000..3f0a2bac812 --- /dev/null +++ b/components/esp_hal_gpio/CMakeLists.txt @@ -0,0 +1,24 @@ +idf_build_get_property(target IDF_TARGET) + +set(srcs) +set(includes "include" "${target}/include") + +if(CONFIG_SOC_GPIO_PORT GREATER 0) + list(APPEND srcs "gpio_hal.c") +endif() + +if(CONFIG_SOC_RTCIO_PIN_COUNT GREATER 0) + list(APPEND srcs "rtc_io_hal.c" "${target}/rtc_io_periph.c") +endif() + +if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED) + list(APPEND srcs "${target}/dedic_gpio_periph.c") +endif() + +if(CONFIG_SOC_SDM_SUPPORTED) + list(APPEND srcs "sdm_hal.c" "${target}/sdm_periph.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${includes} + REQUIRES soc hal) diff --git a/components/esp_hal_gpio/README.md b/components/esp_hal_gpio/README.md new file mode 100644 index 00000000000..84b11039ab1 --- /dev/null +++ b/components/esp_hal_gpio/README.md @@ -0,0 +1,9 @@ +# `esp_hal_gpio` + +⚠️ This HAL component is still under heavy development at the moment, so we don't guarantee the stability and backward-compatibility among versions. + +The `esp_hal_gpio` component provides a **Hardware Abstraction Layer** of GPIO for all targets supported by ESP-IDF. + +In a broad sense, the HAL layer consists of two sub-layers: HAL (upper) and Low-Level(bottom). The HAL layer defines the steps and data that is required to operate a peripheral (e.g. initialization, start and stop). The low-level is a translation layer above the register files under the `soc` component, it only covers general conceptions to register configurations. + +The functions in this file mainly provide hardware abstraction for IDF peripheral drivers. For advanced developers, the HAL layer functions can also be directly used to assist in implementing their own drivers. However, it needs to be mentioned again that the interfaces here do not guarantee stability. diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32/include/hal/gpio_ll.h index 321ba696ec4..7a94f87366a 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h @@ -16,20 +16,15 @@ #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" +#include "soc/io_mux_reg.h" #include "soc/rtc_cntl_reg.h" #include "soc/rtc_io_reg.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/misc.h" -#ifdef __cplusplus -extern "C" { -#endif - -// the address of esp32's IO_MUX_GPIOx_REGs are not incremented as the gpio number increments(address are out of order) -extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -44,6 +39,13 @@ extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + +// the address of esp32's IO_MUX_GPIOx_REGs are not incremented as the gpio number increments(address are out of order) +extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; + /** * @brief Get the configuration for an IO * diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h similarity index 98% rename from components/hal/esp32/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h index 7b0fef6b1c1..6c4863ea3ac 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/rtc_io_ll.h @@ -18,7 +18,8 @@ #include "hal/assert.h" #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_cntl_reg.h" #define RTCIO_LL_PIN_FUNC 0 @@ -403,8 +404,7 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) { REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num); // Set level which will trigger wakeup - SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, - level , RTC_CNTL_EXT_WAKEUP0_LV_S); + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } #ifdef __cplusplus diff --git a/components/hal/esp32/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32/include/hal/sdm_ll.h index 1f76b3a40bd..502d49d4a1c 100644 --- a/components/hal/esp32/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h @@ -12,10 +12,6 @@ #include "soc/gpio_sd_struct.h" #include "soc/gpio_sd_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) @@ -24,6 +20,10 @@ extern "C" { // Support APB as function clock #define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32/rtc_io_periph.c b/components/esp_hal_gpio/esp32/rtc_io_periph.c similarity index 98% rename from components/soc/esp32/rtc_io_periph.c rename to components/esp_hal_gpio/esp32/rtc_io_periph.c index 73e7651af96..4e0be1fdc96 100644 --- a/components/soc/esp32/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32/rtc_io_periph.c @@ -4,8 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" #include "soc/rtc_io_reg.h" +#include "soc/rtc_cntl_reg.h" #include "esp_attr.h" const int8_t DRAM_ATTR rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { diff --git a/components/soc/esp32s3/sdm_periph.c b/components/esp_hal_gpio/esp32/sdm_periph.c similarity index 97% rename from components/soc/esp32s3/sdm_periph.c rename to components/esp_hal_gpio/esp32/sdm_periph.c index 41072082055..a9646d68204 100644 --- a/components/soc/esp32s3/sdm_periph.c +++ b/components/esp_hal_gpio/esp32/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" const soc_sdm_signal_desc_t soc_sdm_signals[1] = { diff --git a/components/soc/esp32c2/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32c2/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32c2/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32c2/dedic_gpio_periph.c index 4c3f6b93e0e..1f4cfc4fad3 100644 --- a/components/soc/esp32c2/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32c2/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h index cd03b348d6c..74eec52ce92 100644 --- a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32c2/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32c2/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32c2/include/hal/gpio_ll.h index 4368a7f9c45..c61430f72c3 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32c2/include/hal/gpio_ll.h @@ -17,16 +17,15 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" +#include "soc/gpio_struct.h" +#include "soc/io_mux_reg.h" #include "soc/rtc_cntl_reg.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" #include "hal/misc.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -35,6 +34,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -178,7 +181,7 @@ __attribute__((always_inline)) static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) { HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); - GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr + hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr } /** diff --git a/components/soc/esp32h2/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32c3/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32h2/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32c3/dedic_gpio_periph.c index 45e0fd7a23e..7890b266d60 100644 --- a/components/soc/esp32h2/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32c3/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h index 12d6ba3bac6..049b212ee31 100644 --- a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32c3/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32c3/include/hal/gpio_ll.h index 3e864a88746..f96b68eb1d0 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/gpio_ll.h @@ -17,18 +17,16 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" +#include "soc/io_mux_reg.h" #include "soc/rtc_cntl_reg.h" #include "soc/usb_serial_jtag_reg.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" #include "hal/misc.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -37,6 +35,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Enable pull-up on GPIO. * diff --git a/components/hal/esp32c3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32c3/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h index 8b981c134ba..63a4d75b446 100644 --- a/components/hal/esp32c3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h @@ -12,10 +12,6 @@ #include "soc/gpio_sd_struct.h" #include "soc/gpio_sd_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) @@ -24,6 +20,10 @@ extern "C" { // Support APB as function clock #define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32c3/sdm_periph.c b/components/esp_hal_gpio/esp32c3/sdm_periph.c similarity index 95% rename from components/soc/esp32c3/sdm_periph.c rename to components/esp_hal_gpio/esp32c3/sdm_periph.c index 50051ba117c..f9059af45cc 100644 --- a/components/soc/esp32c3/sdm_periph.c +++ b/components/esp_hal_gpio/esp32c3/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" const soc_sdm_signal_desc_t soc_sdm_signals[1] = { diff --git a/components/soc/esp32c5/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32c5/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32c5/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32c5/dedic_gpio_periph.c index ef5fc640824..ac0b980e501 100644 --- a/components/soc/esp32c5/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32c5/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h index 7c929195cfe..fd955da5656 100644 --- a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32c5/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32c5/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32c5/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/gpio_ll.h index 17de501b596..d57ecba7a45 100644 --- a/components/hal/esp32c5/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_ll.h @@ -18,23 +18,21 @@ #include #include "soc/soc.h" #include "soc/gpio_ext_reg.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" #include "soc/io_mux_struct.h" +#include "soc/io_mux_reg.h" #include "soc/clk_tree_defs.h" #include "soc/pcr_struct.h" #include "soc/usb_serial_jtag_struct.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" #include "hal/config.h" #include "rom/gpio.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -42,6 +40,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -561,7 +563,7 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) { switch (src) { - case SOC_MOD_CLK_XTAL: + case SOC_MOD_CLK_XTAL: PCR.iomux_clk_conf.iomux_func_clk_sel = 0; break; case SOC_MOD_CLK_RC_FAST: diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h similarity index 100% rename from components/hal/esp32c5/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h index a6511fa190f..43bdc5fb9c3 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h @@ -25,12 +25,12 @@ #include "hal/misc.h" #include "hal/assert.h" +#define RTCIO_LL_PIN_FUNC 1 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 1 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ diff --git a/components/hal/esp32c5/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32c5/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32c5/include/hal/sdm_ll.h index 828c3207ba0..3897b856326 100644 --- a/components/hal/esp32c5/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32c5/rtc_io_periph.c b/components/esp_hal_gpio/esp32c5/rtc_io_periph.c similarity index 92% rename from components/soc/esp32c5/rtc_io_periph.c rename to components/esp_hal_gpio/esp32c5/rtc_io_periph.c index c680c6a34d7..c3e037bc824 100644 --- a/components/soc/esp32c5/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32c5/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32c5/sdm_periph.c b/components/esp_hal_gpio/esp32c5/sdm_periph.c similarity index 98% rename from components/soc/esp32c5/sdm_periph.c rename to components/esp_hal_gpio/esp32c5/sdm_periph.c index ef1b0c1ded9..315a4c5d79f 100644 --- a/components/soc/esp32c5/sdm_periph.c +++ b/components/esp_hal_gpio/esp32c5/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" diff --git a/components/soc/esp32c6/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32c6/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32c6/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32c6/dedic_gpio_periph.c index 58fc3671a71..b835adc00d3 100644 --- a/components/soc/esp32c6/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32c6/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h index 7c929195cfe..fd955da5656 100644 --- a/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32c6/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32c6/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32c6/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32c6/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32c6/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/gpio_ll.h index c374bf541ac..fb76fe0940d 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_ll.h @@ -17,21 +17,19 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" +#include "soc/io_mux_reg.h" #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/pcr_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" #include "hal/misc.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -40,6 +38,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/rtc_io_ll.h similarity index 100% rename from components/hal/esp32c6/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/rtc_io_ll.h index 970bbdd66b1..f5c536db84c 100644 --- a/components/hal/esp32c6/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/rtc_io_ll.h @@ -24,12 +24,12 @@ #include "hal/misc.h" #include "hal/assert.h" +#define RTCIO_LL_PIN_FUNC 0 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 0 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ diff --git a/components/hal/esp32c6/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32c6/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32c6/include/hal/sdm_ll.h index 089cdc7f92c..caad837a058 100644 --- a/components/hal/esp32c6/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32c6/rtc_io_periph.c b/components/esp_hal_gpio/esp32c6/rtc_io_periph.c similarity index 92% rename from components/soc/esp32c6/rtc_io_periph.c rename to components/esp_hal_gpio/esp32c6/rtc_io_periph.c index bb0ac718f8b..a78215f4207 100644 --- a/components/soc/esp32c6/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32c6/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32c6/sdm_periph.c b/components/esp_hal_gpio/esp32c6/sdm_periph.c similarity index 98% rename from components/soc/esp32c6/sdm_periph.c rename to components/esp_hal_gpio/esp32c6/sdm_periph.c index c4c43194117..9356660742a 100644 --- a/components/soc/esp32c6/sdm_periph.c +++ b/components/esp_hal_gpio/esp32c6/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" diff --git a/components/soc/esp32c61/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32c61/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32c61/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32c61/dedic_gpio_periph.c index ef5fc640824..ac0b980e501 100644 --- a/components/soc/esp32c61/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32c61/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h index 7c929195cfe..fd955da5656 100644 --- a/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32c61/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32c61/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32c61/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32c61/include/hal/gpio_ll.h index 1a2aa19a659..b419a8ec94c 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/gpio_ll.h @@ -17,7 +17,6 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_ext_reg.h" #include "soc/gpio_struct.h" #include "soc/lp_aon_struct.h" @@ -26,15 +25,14 @@ #include "soc/clk_tree_defs.h" #include "soc/usb_serial_jtag_struct.h" #include "soc/io_mux_struct.h" +#include "soc/io_mux_reg.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" #include "hal/config.h" #include "rom/gpio.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -43,6 +41,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * diff --git a/components/hal/esp32c61/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h similarity index 100% rename from components/hal/esp32c61/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h index a11e86fae94..196ddbab7be 100644 --- a/components/hal/esp32c61/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h @@ -25,12 +25,12 @@ #include "hal/misc.h" #include "hal/assert.h" +#define RTCIO_LL_PIN_FUNC 1 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 1 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ diff --git a/components/soc/esp32c61/rtc_io_periph.c b/components/esp_hal_gpio/esp32c61/rtc_io_periph.c similarity index 92% rename from components/soc/esp32c61/rtc_io_periph.c rename to components/esp_hal_gpio/esp32c61/rtc_io_periph.c index 00068fc48c1..5afb6fe3713 100644 --- a/components/soc/esp32c61/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32c61/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32c3/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32h2/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32c3/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32h2/dedic_gpio_periph.c index 45e0fd7a23e..7890b266d60 100644 --- a/components/soc/esp32c3/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32h2/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h index db955ea2b96..014605bae91 100644 --- a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32h2/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32h2/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32h2/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32h2/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32h2/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/gpio_ll.h index 0c3511660da..a7f1f09f8db 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_ll.h @@ -17,21 +17,19 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" +#include "soc/io_mux_reg.h" #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/pcr_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -40,6 +38,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * diff --git a/components/hal/esp32h2/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/rtc_io_ll.h similarity index 99% rename from components/hal/esp32h2/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/rtc_io_ll.h index 04863e01d12..28d70f270c7 100644 --- a/components/hal/esp32h2/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/rtc_io_ll.h @@ -13,24 +13,22 @@ #pragma once #include -#include "soc/soc_caps.h" #include "soc/lp_aon_struct.h" #include "soc/lpperi_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" +#define RTCIO_LL_GPIO_NUM_OFFSET 7 // rtcio 0-7 correspond to gpio 7-14 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_GPIO_NUM_OFFSET 7 // rtcio 0-7 correspond to gpio 7-14 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ } rtcio_ll_func_t; - /** * @brief Enable/Disable LP_IO peripheral clock. * diff --git a/components/hal/esp32p4/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32h2/include/hal/sdm_ll.h index 089cdc7f92c..caad837a058 100644 --- a/components/hal/esp32p4/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32h2/rtc_io_periph.c b/components/esp_hal_gpio/esp32h2/rtc_io_periph.c similarity index 92% rename from components/soc/esp32h2/rtc_io_periph.c rename to components/esp_hal_gpio/esp32h2/rtc_io_periph.c index 58184cc5853..5fec1ee0cec 100644 --- a/components/soc/esp32h2/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32h2/rtc_io_periph.c @@ -3,7 +3,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { -1,//GPIO0 diff --git a/components/soc/esp32h2/sdm_periph.c b/components/esp_hal_gpio/esp32h2/sdm_periph.c similarity index 98% rename from components/soc/esp32h2/sdm_periph.c rename to components/esp_hal_gpio/esp32h2/sdm_periph.c index c4c43194117..9356660742a 100644 --- a/components/soc/esp32h2/sdm_periph.c +++ b/components/esp_hal_gpio/esp32h2/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" diff --git a/components/soc/esp32h21/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32h21/dedic_gpio_periph.c similarity index 96% rename from components/soc/esp32h21/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32h21/dedic_gpio_periph.c index d8a317ad1dc..66eb7d1bede 100644 --- a/components/soc/esp32h21/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32h21/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32h21/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32h21/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h index 281fbb4704d..c982d3e2b60 100644 --- a/components/hal/esp32h21/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32h21/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32h21/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32h21/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32h21/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32h21/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32h21/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/gpio_ll.h index 536ed85d1b0..32d7a2a5411 100644 --- a/components/hal/esp32h21/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_ll.h @@ -16,7 +16,6 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" @@ -24,14 +23,13 @@ #include "soc/clk_tree_defs.h" #include "soc/usb_serial_jtag_struct.h" #include "soc/io_mux_struct.h" +#include "soc/io_mux_reg.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -40,6 +38,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * diff --git a/components/hal/esp32h21/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/rtc_io_ll.h similarity index 99% rename from components/hal/esp32h21/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/rtc_io_ll.h index ea5976d9f3c..7e3756b524e 100644 --- a/components/hal/esp32h21/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/rtc_io_ll.h @@ -13,24 +13,22 @@ #pragma once #include -#include "soc/soc_caps.h" #include "soc/lp_aon_struct.h" #include "soc/lpperi_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" +#define RTCIO_LL_GPIO_NUM_OFFSET 5 // rtcio 0-6 correspond to gpio 5-11 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_GPIO_NUM_OFFSET 5 // rtcio 0-6 correspond to gpio 5-11 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ } rtcio_ll_func_t; - /** * @brief Enable/Disable LP_IO peripheral clock. * diff --git a/components/hal/esp32h4/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32h4/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32h21/include/hal/sdm_ll.h index 2c646fc4b59..f290291d968 100644 --- a/components/hal/esp32h4/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32h21/rtc_io_periph.c b/components/esp_hal_gpio/esp32h21/rtc_io_periph.c similarity index 91% rename from components/soc/esp32h21/rtc_io_periph.c rename to components/esp_hal_gpio/esp32h21/rtc_io_periph.c index 10cb7c83c61..0f05a79e22a 100644 --- a/components/soc/esp32h21/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32h21/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { -1,//GPIO0 diff --git a/components/soc/esp32h4/sdm_periph.c b/components/esp_hal_gpio/esp32h21/sdm_periph.c similarity index 98% rename from components/soc/esp32h4/sdm_periph.c rename to components/esp_hal_gpio/esp32h21/sdm_periph.c index 6fd08e451b4..8b6bb9bdcad 100644 --- a/components/soc/esp32h4/sdm_periph.c +++ b/components/esp_hal_gpio/esp32h21/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" @@ -30,8 +30,8 @@ const soc_sdm_signal_desc_t soc_sdm_signals[1] = { /** * @brief Registers in retention context: - * GPIO_EXT_SIGMADELTA[x]_REG * GPIO_EXT_SIGMADELTA_MISC_REG + * GPIO_EXT_SIGMADELTA[x]_REG */ #define GPIO_EXT_RETENTION_REGS_CNT 5 #define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x4) diff --git a/components/soc/esp32h4/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32h4/dedic_gpio_periph.c similarity index 98% rename from components/soc/esp32h4/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32h4/dedic_gpio_periph.c index f4c3768739e..5b78bd718a8 100644 --- a/components/soc/esp32h4/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32h4/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h index 281fbb4704d..c982d3e2b60 100644 --- a/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32h4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32h4/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32h4/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32h4/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h index fc980351fc9..60e843ae52e 100644 --- a/components/hal/esp32h4/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h @@ -15,7 +15,6 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" @@ -25,16 +24,14 @@ #include "soc/usb_wrap_struct.h" #include "soc/pcr_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/interrupts.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" #include "hal/config.h" #include "rom/gpio.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -42,6 +39,10 @@ extern "C" { #define GPIO_LL_PRO_CPU_2_INTR_ENA (BIT(1)) #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -618,7 +619,7 @@ static inline void gpio_ll_force_unhold_all(void) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ - __attribute__((always_inline)) +__attribute__((always_inline)) static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) { IO_MUX.gpio[gpio_num].slp_sel = 1; diff --git a/components/hal/esp32h4/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h similarity index 100% rename from components/hal/esp32h4/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h index 3845bed3b4b..c05f6b3ea0e 100644 --- a/components/hal/esp32h4/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h @@ -25,12 +25,12 @@ #include "hal/misc.h" #include "hal/assert.h" +#define RTCIO_LL_PIN_FUNC 1 + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 1 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ diff --git a/components/hal/esp32h21/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32h21/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32h4/include/hal/sdm_ll.h index 2c646fc4b59..f290291d968 100644 --- a/components/hal/esp32h21/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32h4/rtc_io_periph.c b/components/esp_hal_gpio/esp32h4/rtc_io_periph.c similarity index 93% rename from components/soc/esp32h4/rtc_io_periph.c rename to components/esp_hal_gpio/esp32h4/rtc_io_periph.c index 2eb045373f8..fae0fbe03e3 100644 --- a/components/soc/esp32h4/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32h4/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32h21/sdm_periph.c b/components/esp_hal_gpio/esp32h4/sdm_periph.c similarity index 98% rename from components/soc/esp32h21/sdm_periph.c rename to components/esp_hal_gpio/esp32h4/sdm_periph.c index 19f5b6bfe89..e2a876388f4 100644 --- a/components/soc/esp32h21/sdm_periph.c +++ b/components/esp_hal_gpio/esp32h4/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" @@ -30,8 +30,8 @@ const soc_sdm_signal_desc_t soc_sdm_signals[1] = { /** * @brief Registers in retention context: - * GPIO_EXT_SIGMADELTA_MISC_REG * GPIO_EXT_SIGMADELTA[x]_REG + * GPIO_EXT_SIGMADELTA_MISC_REG */ #define GPIO_EXT_RETENTION_REGS_CNT 5 #define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x4) diff --git a/components/soc/esp32p4/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32p4/dedic_gpio_periph.c similarity index 98% rename from components/soc/esp32p4/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32p4/dedic_gpio_periph.c index c105ab07a16..c1977e38050 100644 --- a/components/soc/esp32p4/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32p4/dedic_gpio_periph.c @@ -5,7 +5,7 @@ */ #include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { .irq = -1, diff --git a/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h index 347d2473754..0abb50c15d2 100644 --- a/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h @@ -9,10 +9,6 @@ #include #include "riscv/csr.h" -#ifdef __cplusplus -extern "C" { -#endif - /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 @@ -21,6 +17,10 @@ extern "C" { /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ #define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) { diff --git a/components/hal/esp32p4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/gpio_etm_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h diff --git a/components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32p4/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/gpio_ll.h index 1344e487c1c..33fe754eb7d 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_ll.h @@ -17,7 +17,6 @@ #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/io_mux_reg.h" #include "soc/io_mux_struct.h" @@ -29,16 +28,13 @@ #include "soc/usb_serial_jtag_struct.h" #include "soc/usb_wrap_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/interrupts.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" #include "hal/config.h" #include "rom/gpio.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -49,6 +45,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR0_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -852,7 +852,6 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num IO_MUX.gpio[gpio_num].mcu_oe = 1; } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h index 2424fe20e77..14705bd2fd5 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h @@ -25,12 +25,12 @@ #include "hal/assert.h" #include "hal/config.h" +#define RTCIO_LL_PIN_FUNC 1 // LP_GPIO function + #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 1 // LP_GPIO function - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ diff --git a/components/hal/esp32h2/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32h2/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32p4/include/hal/sdm_ll.h index 089cdc7f92c..caad837a058 100644 --- a/components/hal/esp32h2/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/sdm_ll.h @@ -12,15 +12,15 @@ #include "soc/gpio_ext_struct.h" #include "soc/gpio_ext_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) #define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1) +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/esp_hal_gpio/esp32p4/rtc_io_periph.c similarity index 95% rename from components/soc/esp32p4/rtc_io_periph.c rename to components/esp_hal_gpio/esp32p4/rtc_io_periph.c index db6827ea574..8d538baa1d3 100644 --- a/components/soc/esp32p4/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32p4/rtc_io_periph.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32p4/sdm_periph.c b/components/esp_hal_gpio/esp32p4/sdm_periph.c similarity index 98% rename from components/soc/esp32p4/sdm_periph.c rename to components/esp_hal_gpio/esp32p4/sdm_periph.c index 4b89dce5a3f..b1225194963 100644 --- a/components/soc/esp32p4/sdm_periph.c +++ b/components/esp_hal_gpio/esp32p4/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_ext_reg.h" diff --git a/components/soc/esp32s2/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32s2/dedic_gpio_periph.c similarity index 97% rename from components/soc/esp32s2/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32s2/dedic_gpio_periph.c index 8ebcb4cfd53..e1b812c03c7 100644 --- a/components/soc/esp32s2/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32s2/dedic_gpio_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" #include "soc/gpio_sig_map.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_cpu_ll.h diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h similarity index 100% rename from components/hal/esp32s2/include/hal/dedic_gpio_ll.h rename to components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h index 6c6d9967b64..d377896cf8e 100644 --- a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h @@ -11,12 +11,12 @@ #include "soc/dedic_gpio_struct.h" #include "soc/system_reg.h" +#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ + #ifdef __cplusplus extern "C" { #endif -#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ - static inline void _dedic_gpio_ll_enable_bus_clock(bool enable) { uint32_t reg_val = READ_PERI_REG(DPORT_CPU_PERI_CLK_EN_REG); diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32s2/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32s2/include/hal/gpio_ll.h index b1d82130fdf..1c372372438 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/gpio_ll.h @@ -16,16 +16,13 @@ #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" +#include "soc/io_mux_reg.h" #include "soc/gpio_struct.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -34,6 +31,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -706,7 +707,6 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h similarity index 98% rename from components/hal/esp32s2/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h index 3a0ef83d0fc..6f26a35b3f5 100644 --- a/components/hal/esp32s2/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h @@ -18,7 +18,8 @@ #include "hal/gpio_types.h" #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_cntl_reg.h" #include "soc/sens_struct.h" #define RTCIO_LL_PIN_FUNC 0 @@ -406,8 +407,7 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) { REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num); // Set level which will trigger wakeup - SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, - level , RTC_CNTL_EXT_WAKEUP0_LV_S); + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32s2/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h index 0f3e354d3a4..d4cb9a1ae23 100644 --- a/components/hal/esp32s2/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h @@ -12,10 +12,6 @@ #include "soc/gpio_sd_struct.h" #include "soc/gpio_sd_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) @@ -24,6 +20,10 @@ extern "C" { // Support APB as function clock #define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32s2/rtc_io_periph.c b/components/esp_hal_gpio/esp32s2/rtc_io_periph.c similarity index 99% rename from components/soc/esp32s2/rtc_io_periph.c rename to components/esp_hal_gpio/esp32s2/rtc_io_periph.c index 6980852b658..79c85483c3d 100644 --- a/components/soc/esp32s2/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32s2/rtc_io_periph.c @@ -4,8 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" #include "soc/rtc_io_reg.h" +#include "soc/rtc_cntl_reg.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32/sdm_periph.c b/components/esp_hal_gpio/esp32s2/sdm_periph.c similarity index 97% rename from components/soc/esp32/sdm_periph.c rename to components/esp_hal_gpio/esp32s2/sdm_periph.c index 41072082055..a9646d68204 100644 --- a/components/soc/esp32/sdm_periph.c +++ b/components/esp_hal_gpio/esp32s2/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" const soc_sdm_signal_desc_t soc_sdm_signals[1] = { diff --git a/components/soc/esp32s3/dedic_gpio_periph.c b/components/esp_hal_gpio/esp32s3/dedic_gpio_periph.c similarity index 98% rename from components/soc/esp32s3/dedic_gpio_periph.c rename to components/esp_hal_gpio/esp32s3/dedic_gpio_periph.c index e4f4166785c..08c3c3b8ec2 100644 --- a/components/soc/esp32s3/dedic_gpio_periph.c +++ b/components/esp_hal_gpio/esp32s3/dedic_gpio_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" #include "soc/gpio_sig_map.h" const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_cpu_ll.h similarity index 100% rename from components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h rename to components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_cpu_ll.h diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_ll.h similarity index 100% rename from components/hal/esp32s3/include/hal/dedic_gpio_ll.h rename to components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_ll.h diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/gpio_ll.h similarity index 99% rename from components/hal/esp32s3/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32s3/include/hal/gpio_ll.h index 73f38b53fbc..1f75f648367 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/gpio_ll.h @@ -16,15 +16,12 @@ #include #include "soc/soc.h" -#include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_struct.h" #include "soc/rtc_cntl_reg.h" #include "soc/usb_serial_jtag_reg.h" +#include "soc/gpio_periph.h" #include "hal/gpio_types.h" -#include "soc/gpio_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -35,6 +32,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Enable pull-up on GPIO. * diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h similarity index 98% rename from components/hal/esp32s3/include/hal/rtc_io_ll.h rename to components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h index cdfa100aa03..c60be499614 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h @@ -18,18 +18,20 @@ #include "hal/assert.h" #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" #include "soc/io_mux_reg.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" #include "soc/sens_struct.h" +#include "soc/rtc_cntl_reg.h" + +#define RTCIO_LL_PIN_FUNC 0 #ifdef __cplusplus extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 0 - typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ @@ -433,8 +435,7 @@ static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) { REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num); // Set level which will trigger wakeup - SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, - level , RTC_CNTL_EXT_WAKEUP0_LV_S); + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, level, RTC_CNTL_EXT_WAKEUP0_LV_S); } #ifdef __cplusplus diff --git a/components/hal/esp32s3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h similarity index 100% rename from components/hal/esp32s3/include/hal/sdm_ll.h rename to components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h index d83aaf2ba5e..9965358f632 100644 --- a/components/hal/esp32s3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h @@ -12,10 +12,6 @@ #include "soc/gpio_sd_struct.h" #include "soc/gpio_sd_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get SDM register base address with giving group number #define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL) @@ -24,6 +20,10 @@ extern "C" { // Support APB as function clock #define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Set Sigma-delta enable * diff --git a/components/soc/esp32s3/rtc_io_periph.c b/components/esp_hal_gpio/esp32s3/rtc_io_periph.c similarity index 99% rename from components/soc/esp32s3/rtc_io_periph.c rename to components/esp_hal_gpio/esp32s3/rtc_io_periph.c index 7523759f1f6..dd3654e08b8 100644 --- a/components/soc/esp32s3/rtc_io_periph.c +++ b/components/esp_hal_gpio/esp32s3/rtc_io_periph.c @@ -4,8 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_periph.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" #include "soc/rtc_io_reg.h" +#include "soc/rtc_cntl_reg.h" const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32s2/sdm_periph.c b/components/esp_hal_gpio/esp32s3/sdm_periph.c similarity index 97% rename from components/soc/esp32s2/sdm_periph.c rename to components/esp_hal_gpio/esp32s3/sdm_periph.c index 41072082055..a9646d68204 100644 --- a/components/soc/esp32s2/sdm_periph.c +++ b/components/esp_hal_gpio/esp32s3/sdm_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" #include "soc/gpio_sig_map.h" const soc_sdm_signal_desc_t soc_sdm_signals[1] = { diff --git a/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h new file mode 100644 index 00000000000..f475559875f --- /dev/null +++ b/components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr diff --git a/components/hal/esp32s31/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h similarity index 94% rename from components/hal/esp32s31/include/hal/gpio_ll.h rename to components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h index 23730ab2129..4c8ad117826 100644 --- a/components/hal/esp32s31/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h @@ -10,14 +10,15 @@ * See readme.md in hal/include/hal/readme.md ******************************************************************************/ -// The LL layer for ESP32-P4 GPIO register operations +// The LL layer for ESP32-S31 GPIO register operations + +// TODO: This GPIO LL is not very update to date!!! Needs to check every function carefully! #pragma once #include #include #include "soc/soc.h" -#include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/io_mux_reg.h" #include "soc/io_mux_struct.h" @@ -30,14 +31,11 @@ #include "soc/pmu_struct.h" #include "soc/usb_serial_jtag_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/interrupts.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" -#ifdef __cplusplus -extern "C" { -#endif - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -48,6 +46,10 @@ extern "C" { #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR0_SOURCE +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Get the configuration for an IO * @@ -323,21 +325,6 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } -/** - * @brief Disconnect any peripheral output signal routed via GPIO matrix to the pin - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -__attribute__((always_inline)) -static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num) -{ - gpio_func_out_sel_cfg_reg_t reg = { - .out_sel = SIG_GPIO_OUT_IDX, - }; - hw->func_out_sel_cfg[gpio_num].val = reg.val; -} - /** * @brief GPIO set output level * @@ -445,15 +432,13 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu __attribute__((always_inline)) static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { - if(gpio_num < 8){ - REG_SET_BIT(LP_SYSTEM_REG_PADCTRL_REG, (0x1 << (gpio_num + 8))); - } - else if(gpio_num < 40){ - REG_SET_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL0_REG, (0x1 << (gpio_num - 8))); - } - else{ - REG_SET_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL1_REG, (0x1 << (gpio_num - 40))); - } + if (gpio_num < 8) { + REG_SET_BIT(LP_SYSTEM_REG_PADCTRL_REG, (0x1 << (gpio_num + 8))); + } else if (gpio_num < 40) { + REG_SET_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL0_REG, (0x1 << (gpio_num - 8))); + } else { + REG_SET_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL1_REG, (0x1 << (gpio_num - 40))); + } } /** @@ -465,15 +450,13 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { - if(gpio_num < 8){ - REG_CLR_BIT(LP_SYSTEM_REG_PADCTRL_REG, (0x1 << (gpio_num + 8))); - } - else if(gpio_num < 40){ - REG_CLR_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL0_REG, (0x1 << (gpio_num - 8))); - } - else{ - REG_CLR_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL1_REG, (0x1 << (gpio_num - 40))); - } + if (gpio_num < 8) { + REG_CLR_BIT(LP_SYSTEM_REG_PADCTRL_REG, (0x1 << (gpio_num + 8))); + } else if (gpio_num < 40) { + REG_CLR_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL0_REG, (0x1 << (gpio_num - 8))); + } else { + REG_CLR_BIT(LP_SYSTEM_REG_HP_GPIO_O_HOLD_CTRL1_REG, (0x1 << (gpio_num - 40))); + } } /** @@ -517,7 +500,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. @@ -563,7 +546,6 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) } } - /** * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix. * @@ -722,7 +704,6 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num // TODO: [ESP32S31] IDF-14780 } - #ifdef __cplusplus } #endif diff --git a/components/hal/gpio_hal.c b/components/esp_hal_gpio/gpio_hal.c similarity index 99% rename from components/hal/gpio_hal.c rename to components/esp_hal_gpio/gpio_hal.c index 2d4e22bb36b..43eacf30379 100644 --- a/components/hal/gpio_hal.c +++ b/components/esp_hal_gpio/gpio_hal.c @@ -8,7 +8,6 @@ #include "soc/soc.h" #include "esp_attr.h" -#include "soc/gpio_periph.h" #include "hal/gpio_hal.h" #include "esp_rom_gpio.h" #include "hal/config.h" diff --git a/components/soc/include/soc/dedic_gpio_periph.h b/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h similarity index 100% rename from components/soc/include/soc/dedic_gpio_periph.h rename to components/esp_hal_gpio/include/hal/dedic_gpio_periph.h diff --git a/components/hal/include/hal/gpio_hal.h b/components/esp_hal_gpio/include/hal/gpio_hal.h similarity index 99% rename from components/hal/include/hal/gpio_hal.h rename to components/esp_hal_gpio/include/hal/gpio_hal.h index 1bd0d47f32f..b878f81dc63 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/esp_hal_gpio/include/hal/gpio_hal.h @@ -14,10 +14,10 @@ #pragma once -#include "soc/gpio_periph.h" #include "soc/soc_caps.h" #include "hal/gpio_ll.h" #include "hal/gpio_types.h" +#include "soc/gpio_sig_map.h" #ifdef __cplusplus extern "C" { @@ -375,7 +375,7 @@ void gpio_hal_iomux_in(gpio_hal_context_t *hal, uint32_t gpio_num, int func, uin * @param func The index number of the IOMUX function to be selected for the pin. * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. */ - void gpio_hal_iomux_out(gpio_hal_context_t *hal, uint32_t gpio_num, int func); +void gpio_hal_iomux_out(gpio_hal_context_t *hal, uint32_t gpio_num, int func); /** * @brief Set pad input to a peripheral signal through the GPIO matrix. diff --git a/components/hal/include/hal/gpio_types.h b/components/esp_hal_gpio/include/hal/gpio_types.h similarity index 100% rename from components/hal/include/hal/gpio_types.h rename to components/esp_hal_gpio/include/hal/gpio_types.h diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/esp_hal_gpio/include/hal/rtc_io_hal.h similarity index 99% rename from components/hal/include/hal/rtc_io_hal.h rename to components/esp_hal_gpio/include/hal/rtc_io_hal.h index b55c45a6f03..a0d94d573f0 100644 --- a/components/hal/include/hal/rtc_io_hal.h +++ b/components/esp_hal_gpio/include/hal/rtc_io_hal.h @@ -18,7 +18,7 @@ #include "soc/soc_caps.h" #if SOC_RTCIO_PIN_COUNT > 0 -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" #include "hal/rtc_io_ll.h" #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "hal/rtc_io_types.h" diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/esp_hal_gpio/include/hal/rtc_io_periph.h similarity index 95% rename from components/soc/include/soc/rtc_io_periph.h rename to components/esp_hal_gpio/include/hal/rtc_io_periph.h index 49ddd10ffce..e503c951182 100644 --- a/components/soc/include/soc/rtc_io_periph.h +++ b/components/esp_hal_gpio/include/hal/rtc_io_periph.h @@ -10,12 +10,6 @@ //include soc related (generated) definitions #include "soc/soc_caps.h" -#if SOC_RTCIO_PIN_COUNT > 0 -#include "soc/rtc_io_channel.h" -#endif - -#include "soc/io_mux_reg.h" - #ifdef __cplusplus extern "C" { diff --git a/components/hal/include/hal/rtc_io_types.h b/components/esp_hal_gpio/include/hal/rtc_io_types.h similarity index 92% rename from components/hal/include/hal/rtc_io_types.h rename to components/esp_hal_gpio/include/hal/rtc_io_types.h index 6480f23708f..84b45792707 100644 --- a/components/hal/include/hal/rtc_io_types.h +++ b/components/esp_hal_gpio/include/hal/rtc_io_types.h @@ -12,7 +12,7 @@ extern "C" { /** RTCIO output/input mode type. */ typedef enum { - RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */ + RTC_GPIO_MODE_INPUT_ONLY, /*!< Pad input */ RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */ RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad input + output */ RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable */ diff --git a/components/hal/include/hal/sdm_hal.h b/components/esp_hal_gpio/include/hal/sdm_hal.h similarity index 100% rename from components/hal/include/hal/sdm_hal.h rename to components/esp_hal_gpio/include/hal/sdm_hal.h diff --git a/components/soc/include/soc/sdm_periph.h b/components/esp_hal_gpio/include/hal/sdm_periph.h similarity index 100% rename from components/soc/include/soc/sdm_periph.h rename to components/esp_hal_gpio/include/hal/sdm_periph.h diff --git a/components/hal/include/hal/sdm_types.h b/components/esp_hal_gpio/include/hal/sdm_types.h similarity index 100% rename from components/hal/include/hal/sdm_types.h rename to components/esp_hal_gpio/include/hal/sdm_types.h diff --git a/components/hal/rtc_io_hal.c b/components/esp_hal_gpio/rtc_io_hal.c similarity index 100% rename from components/hal/rtc_io_hal.c rename to components/esp_hal_gpio/rtc_io_hal.c diff --git a/components/hal/sdm_hal.c b/components/esp_hal_gpio/sdm_hal.c similarity index 100% rename from components/hal/sdm_hal.c rename to components/esp_hal_gpio/sdm_hal.c diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 10aa6b69412..7944e3c0d79 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -9,7 +9,7 @@ if(${target} STREQUAL "linux") return() endif() -set(requires esp_hal_dma esp_hal_usb) +set(requires esp_hal_dma esp_hal_gpio esp_hal_usb) # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt) diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 6a0de4b82d6..6fb67bbb747 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -86,6 +86,11 @@ entries: sleep_modes: esp_sleep_sub_mode_config (noflash) sleep_modes: esp_sleep_sub_mode_force_disable (noflash) +[mapping:hal_gpio_pm] +archive: libesp_hal_gpio.a +entries: + gpio_hal: gpio_hal_isolate_in_sleep (noflash) + [mapping:soc_pm] archive: libsoc.a entries: diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index ae891b2c50a..64ea1033b92 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -11,7 +11,7 @@ #include "soc/rtc.h" #include "esp_private/rtc_clk.h" #include "esp_private/esp_sleep_internal.h" -#include "soc/rtc_periph.h" +#include "soc/rtc_io_reg.h" #include "soc/sens_reg.h" #include "soc/soc_caps.h" #include "soc/chip_revision.h" diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c index 087824c279b..d11d2b776b4 100644 --- a/components/esp_hw_support/port/esp32/rtc_init.c +++ b/components/esp_hw_support/port/esp32/rtc_init.c @@ -11,7 +11,7 @@ #include "soc/rtc_periph.h" #include "soc/dport_reg.h" #include "hal/efuse_ll.h" -#include "soc/gpio_periph.h" +#include "soc/gpio_reg.h" #ifndef BOOTLOADER_BUILD #include "esp_private/sar_periph_ctrl.h" #endif diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 0ac1dd67cfe..deebc5262e5 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -21,7 +21,7 @@ #include "driver/gpio.h" #include "hal/gpio_hal.h" #include "hal/rtc_io_hal.h" -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" #include "soc/uart_pins.h" #include "hal/rtc_hal.h" diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c index 71700dccd9b..2f081f770b5 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c +++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c @@ -10,8 +10,6 @@ #include "esp_attr.h" #include "soc/soc_caps.h" #include "soc/rtc.h" -#include "soc/rtc_periph.h" -#include "soc/gpio_periph.h" #include "hal/gpio_ll.h" #include "soc/io_mux_reg.h" #include "driver/rtc_io.h" @@ -448,7 +446,7 @@ TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sle * output either 150k, 32k, 8M clock to GPIO25. */ #if CONFIG_IDF_TARGET_ESP32 - +#include "soc/rtc_io_reg.h" #include "soc/sens_reg.h" static void pull_out_clk(int sel) diff --git a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt index 9326fcbd3bb..e7a900b8cb2 100644 --- a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt +++ b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt @@ -5,5 +5,5 @@ set(sources "test_app_main.c" # the component must be registered as a WHOLE_ARCHIVE idf_component_register(SRCS ${sources} INCLUDE_DIRS "." - PRIV_REQUIRES unity esp_pm ulp esp_timer esp_psram esp_driver_gptimer vfs + PRIV_REQUIRES unity esp_pm ulp esp_timer esp_psram esp_driver_gptimer vfs esp_hal_gpio WHOLE_ARCHIVE) diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c index c9ad0e3e9c1..cdceb1d1645 100644 --- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c +++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c @@ -23,7 +23,6 @@ #include "driver/rtc_io.h" #include "soc/rtc.h" #include "esp_private/gptimer.h" -#include "soc/rtc_periph.h" #include "esp_rom_sys.h" #include "esp_private/esp_clk.h" @@ -32,6 +31,10 @@ #if CONFIG_ULP_COPROC_TYPE_FSM #if CONFIG_IDF_TARGET_ESP32 #include "esp32/ulp.h" +#include "soc/rtc_io_reg.h" +#include "hal/rtc_io_periph.h" +#include "soc/rtc_io_channel.h" +#include "soc/rtc_cntl_reg.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/ulp.h" #elif CONFIG_IDF_TARGET_ESP32S3 diff --git a/components/esp_psram/CMakeLists.txt b/components/esp_psram/CMakeLists.txt index 72e42a0977b..b2118716d0e 100644 --- a/components/esp_psram/CMakeLists.txt +++ b/components/esp_psram/CMakeLists.txt @@ -10,7 +10,7 @@ if(CONFIG_SOC_SPIRAM_XIP_SUPPORTED) list(APPEND includes xip_impl/include) endif() -set(priv_requires heap spi_flash esp_mm esp_hal_mspi) +set(priv_requires heap spi_flash esp_mm esp_hal_mspi esp_hal_gpio) if(${target} STREQUAL "esp32") list(APPEND priv_requires bootloader_support esp_driver_spi esp_driver_gpio) endif() diff --git a/components/esp_system/port/soc/esp32/reset_reason.c b/components/esp_system/port/soc/esp32/reset_reason.c index ea432f0a2f9..01096566a5e 100644 --- a/components/esp_system/port/soc/esp32/reset_reason.c +++ b/components/esp_system/port/soc/esp32/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index be4dcc563cf..b33ce829f1c 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -14,9 +14,8 @@ #include "sdkconfig.h" #include "esp_rom_serial_output.h" #include "soc/dport_reg.h" -#include "soc/gpio_periph.h" +#include "soc/gpio_reg.h" #include "soc/efuse_periph.h" -#include "soc/rtc_periph.h" #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" diff --git a/components/esp_system/port/soc/esp32c2/reset_reason.c b/components/esp_system/port/soc/esp32c2/reset_reason.c index 1492db01279..1d96e3c7b04 100644 --- a/components/esp_system/port/soc/esp32c2/reset_reason.c +++ b/components/esp_system/port/soc/esp32c2/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32c2/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c index 46674fb2215..042d5ccadb2 100644 --- a/components/esp_system/port/soc/esp32c2/system_internal.c +++ b/components/esp_system/port/soc/esp32c2/system_internal.c @@ -18,7 +18,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/syscon_reg.h" #include "soc/system_reg.h" #include "hal/wdt_hal.h" diff --git a/components/esp_system/port/soc/esp32c3/reset_reason.c b/components/esp_system/port/soc/esp32c3/reset_reason.c index c4f536bafb5..a2a024c8e05 100644 --- a/components/esp_system/port/soc/esp32c3/reset_reason.c +++ b/components/esp_system/port/soc/esp32c3/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32c3/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c index 2edbf81732f..304018ada37 100644 --- a/components/esp_system/port/soc/esp32c3/system_internal.c +++ b/components/esp_system/port/soc/esp32c3/system_internal.c @@ -18,7 +18,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/syscon_reg.h" #include "soc/system_reg.h" #include "soc/uart_reg.h" diff --git a/components/esp_system/port/soc/esp32c5/reset_reason.c b/components/esp_system/port/soc/esp32c5/reset_reason.c index 2b1738cd7bd..331d2e4c60f 100644 --- a/components/esp_system/port/soc/esp32c5/reset_reason.c +++ b/components/esp_system/port/soc/esp32c5/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32c5/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index 95365b19b4d..7a159981930 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -19,7 +19,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "hal/uart_ll.h" diff --git a/components/esp_system/port/soc/esp32c6/reset_reason.c b/components/esp_system/port/soc/esp32c6/reset_reason.c index 7bb04e50356..16bc1add94e 100644 --- a/components/esp_system/port/soc/esp32c6/reset_reason.c +++ b/components/esp_system/port/soc/esp32c6/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32c6/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 995c738217c..62ee75d7de5 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -18,7 +18,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/uart_ll.h" #include "hal/wdt_hal.h" diff --git a/components/esp_system/port/soc/esp32c61/reset_reason.c b/components/esp_system/port/soc/esp32c61/reset_reason.c index 211ec04d7b9..a775bce2b4a 100644 --- a/components/esp_system/port/soc/esp32c61/reset_reason.c +++ b/components/esp_system/port/soc/esp32c61/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32c61/rom/rtc.h" // TODO: [ESP32C61] IDF-9267 diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index 8fb2088d5ea..384d7dbcadf 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -18,7 +18,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/uart_ll.h" #include "hal/wdt_hal.h" diff --git a/components/esp_system/port/soc/esp32h2/reset_reason.c b/components/esp_system/port/soc/esp32h2/reset_reason.c index 4c01941ab06..2f29fd2e060 100644 --- a/components/esp_system/port/soc/esp32h2/reset_reason.c +++ b/components/esp_system/port/soc/esp32h2/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32h2/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index b0e5750659a..71278ecc54f 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -19,7 +19,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "hal/uart_ll.h" diff --git a/components/esp_system/port/soc/esp32h21/reset_reason.c b/components/esp_system/port/soc/esp32h21/reset_reason.c index 4d8385c7ebf..764c277e574 100644 --- a/components/esp_system/port/soc/esp32h21/reset_reason.c +++ b/components/esp_system/port/soc/esp32h21/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32h21/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c index 4e6cfcd1742..3c1c4e83d8d 100644 --- a/components/esp_system/port/soc/esp32h21/system_internal.c +++ b/components/esp_system/port/soc/esp32h21/system_internal.c @@ -19,7 +19,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/uart_ll.h" #include "hal/wdt_hal.h" diff --git a/components/esp_system/port/soc/esp32h4/reset_reason.c b/components/esp_system/port/soc/esp32h4/reset_reason.c index 9e1589c60a5..a3c0d690599 100644 --- a/components/esp_system/port/soc/esp32h4/reset_reason.c +++ b/components/esp_system/port/soc/esp32h4/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32h4/rom/rtc.h" // IDF-11910 need refactor diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c index ff9e47ed039..111d2dc0469 100644 --- a/components/esp_system/port/soc/esp32h4/system_internal.c +++ b/components/esp_system/port/soc/esp32h4/system_internal.c @@ -19,7 +19,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "hal/uart_ll.h" diff --git a/components/esp_system/port/soc/esp32p4/reset_reason.c b/components/esp_system/port/soc/esp32p4/reset_reason.c index 2407cc118d1..b354d978a36 100644 --- a/components/esp_system/port/soc/esp32p4/reset_reason.c +++ b/components/esp_system/port/soc/esp32p4/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "soc/chip_revision.h" #include "hal/efuse_hal.h" #include "esp32p4/rom/rtc.h" diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index 81146051afa..7df55e90b7a 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -18,7 +18,6 @@ #include "esp_cpu.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "esp_private/cache_err_int.h" diff --git a/components/esp_system/port/soc/esp32s2/reset_reason.c b/components/esp_system/port/soc/esp32s2/reset_reason.c index 02714107f8d..1a6cc6e776c 100644 --- a/components/esp_system/port/soc/esp32s2/reset_reason.c +++ b/components/esp_system/port/soc/esp32s2/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32s2/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index a60add4b7f9..d7ca06c5e6c 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -20,7 +20,6 @@ #include "soc/rtc.h" #include "esp_private/rtc_clk.h" #include "soc/syscon_reg.h" -#include "soc/rtc_periph.h" #include "hal/wdt_hal.h" #include "hal/uart_ll.h" #include "soc/soc_memory_layout.h" diff --git a/components/esp_system/port/soc/esp32s3/reset_reason.c b/components/esp_system/port/soc/esp32s3/reset_reason.c index 1a050b9b9e2..771abd91391 100644 --- a/components/esp_system/port/soc/esp32s3/reset_reason.c +++ b/components/esp_system/port/soc/esp32s3/reset_reason.c @@ -7,7 +7,6 @@ #include "esp_system.h" #include "esp_rom_sys.h" #include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" #include "esp32s3/rom/rtc.h" static void esp_reset_reason_clear_hint(void); diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 3a08a82e06f..0d1e072d994 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -21,7 +21,6 @@ #include "soc/rtc.h" #include "esp_private/rtc_clk.h" #include "soc/syscon_reg.h" -#include "soc/rtc_periph.h" #include "hal/wdt_hal.h" #include "hal/uart_ll.h" #include "soc/soc_memory_layout.h" diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c index 96a5f84c66d..54059939c7e 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c @@ -12,7 +12,6 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" -#include "soc/gpio_periph.h" #include "hal/uart_types.h" #include "hal/uart_ll.h" #include "driver/uart.h" diff --git a/components/espcoredump/src/core_dump_uart.c b/components/espcoredump/src/core_dump_uart.c index 94af38761ea..4a481e5ec70 100644 --- a/components/espcoredump/src/core_dump_uart.c +++ b/components/espcoredump/src/core_dump_uart.c @@ -7,7 +7,6 @@ #include #include "soc/uart_reg.h" -#include "soc/gpio_periph.h" #include "soc/uart_pins.h" #include "driver/gpio.h" #include "hal/gpio_hal.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 6e44224f909..6e0dba99eae 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -89,14 +89,6 @@ elseif(NOT BOOTLOADER_BUILD) list(APPEND srcs "uart_hal.c" "uart_hal_iram.c") endif() - if(CONFIG_SOC_GPIO_PORT) - list(APPEND srcs "gpio_hal.c") - endif() - - if(CONFIG_SOC_RTCIO_PIN_COUNT) - list(APPEND srcs "rtc_io_hal.c") - endif() - if(CONFIG_SOC_LEDC_SUPPORTED) list(APPEND srcs "ledc_hal.c" "ledc_hal_iram.c") endif() @@ -121,10 +113,6 @@ elseif(NOT BOOTLOADER_BUILD) endif() endif() - if(CONFIG_SOC_SDM_SUPPORTED) - list(APPEND srcs "sdm_hal.c") - endif() - if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) list(APPEND srcs "sdmmc_hal.c") endif() diff --git a/components/hal/linker.lf b/components/hal/linker.lf index c01d32753ae..c9116c144ce 100644 --- a/components/hal/linker.lf +++ b/components/hal/linker.lf @@ -11,5 +11,3 @@ entries: systimer_hal (noflash) if SOC_PMU_SUPPORTED = y: pmu_hal (noflash) - if SOC_GPIO_PORT != 0: - gpio_hal: gpio_hal_isolate_in_sleep (noflash) diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 7781f440eb6..c973922fe9f 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -72,10 +72,6 @@ if(CONFIG_SOC_ANA_CMPR_SUPPORTED) list(APPEND srcs "${target_folder}/ana_cmpr_periph.c") endif() -if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED) - list(APPEND srcs "${target_folder}/dedic_gpio_periph.c") -endif() - if(CONFIG_SOC_DEBUG_PROBE_SUPPORTED) list(APPEND srcs "${target_folder}/debug_probe_periph.c") endif() @@ -89,10 +85,6 @@ if(CONFIG_SOC_LEDC_SUPPORTED) list(APPEND srcs "${target_folder}/ledc_periph.c") endif() -if(CONFIG_SOC_SDM_SUPPORTED) - list(APPEND srcs "${target_folder}/sdm_periph.c") -endif() - if(CONFIG_SOC_ISP_SUPPORTED) list(APPEND srcs "${target}/isp_periph.c") endif() @@ -129,10 +121,6 @@ if(CONFIG_SOC_DAC_SUPPORTED) list(APPEND srcs "${target_folder}/dac_periph.c") endif() -if(CONFIG_SOC_RTCIO_PIN_COUNT GREATER 0) - list(APPEND srcs "${target_folder}/rtc_io_periph.c") -endif() - if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED) list(APPEND srcs "${target_folder}/sdio_slave_periph.c") endif() diff --git a/components/soc/esp32/gpio_periph.c b/components/soc/esp32/gpio_periph.c index b2940e378ff..7d4e081f48f 100644 --- a/components/soc/esp32/gpio_periph.c +++ b/components/soc/esp32/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" #include "esp_attr.h" const uint32_t GPIO_PIN_MUX_REG[] = { diff --git a/components/soc/esp32/sdio_slave_periph.c b/components/soc/esp32/sdio_slave_periph.c index d8a7982ea29..3fa3e3840ed 100644 --- a/components/soc/esp32/sdio_slave_periph.c +++ b/components/soc/esp32/sdio_slave_periph.c @@ -6,7 +6,6 @@ #include #include "soc/sdio_slave_periph.h" -#include "soc/gpio_periph.h" /** * I/O slot of sdio slave: diff --git a/components/soc/esp32c2/gpio_periph.c b/components/soc/esp32c2/gpio_periph.c index 00e258d0874..047565d72a2 100644 --- a/components/soc/esp32c2/gpio_periph.c +++ b/components/soc/esp32c2/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/esp32c3/gpio_periph.c b/components/soc/esp32c3/gpio_periph.c index 29ae01e2297..532ffe9c86c 100644 --- a/components/soc/esp32c3/gpio_periph.c +++ b/components/soc/esp32c3/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/esp32c5/gpio_periph.c b/components/soc/esp32c5/gpio_periph.c index 37c07f1cbcd..85b9cf3e6e0 100644 --- a/components/soc/esp32c5/gpio_periph.c +++ b/components/soc/esp32c5/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "esp_bit_defs.h" const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG diff --git a/components/soc/esp32c6/gpio_periph.c b/components/soc/esp32c6/gpio_periph.c index d04df9fc977..ff7a6a0d1fa 100644 --- a/components/soc/esp32c6/gpio_periph.c +++ b/components/soc/esp32c6/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/esp32c61/gpio_periph.c b/components/soc/esp32c61/gpio_periph.c index 7f34e53bf6e..5acb56a1903 100644 --- a/components/soc/esp32c61/gpio_periph.c +++ b/components/soc/esp32c61/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "esp_bit_defs.h" const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c index c52611c37d5..130fb874623 100644 --- a/components/soc/esp32h2/gpio_periph.c +++ b/components/soc/esp32h2/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/esp32h21/gpio_periph.c b/components/soc/esp32h21/gpio_periph.c index d45fe4fe42c..6b5c7ffe88e 100644 --- a/components/soc/esp32h21/gpio_periph.c +++ b/components/soc/esp32h21/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "esp_bit_defs.h" const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG diff --git a/components/soc/esp32h4/gpio_periph.c b/components/soc/esp32h4/gpio_periph.c index 29ad93e5993..5e47764c05f 100644 --- a/components/soc/esp32h4/gpio_periph.c +++ b/components/soc/esp32h4/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "esp_bit_defs.h" const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 //LP_AON_GPIO_HOLD0_REG diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c index 1fa61c8dc97..e0da06cdb86 100644 --- a/components/soc/esp32p4/gpio_periph.c +++ b/components/soc/esp32p4/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" #include "esp_assert.h" const uint32_t GPIO_PIN_MUX_REG[] = { diff --git a/components/soc/esp32s2/gpio_periph.c b/components/soc/esp32s2/gpio_periph.c index 25a453915a0..e1aa8e8adf4 100644 --- a/components/soc/esp32s2/gpio_periph.c +++ b/components/soc/esp32s2/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/esp32s3/gpio_periph.c b/components/soc/esp32s3/gpio_periph.c index 770e50cea82..d6f2864f2f1 100644 --- a/components/soc/esp32s3/gpio_periph.c +++ b/components/soc/esp32s3/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "soc/io_mux_reg.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, diff --git a/components/soc/include/soc/gpio_periph.h b/components/soc/include/soc/gpio_periph.h index c9a88a50d87..994380e76c0 100644 --- a/components/soc/include/soc/gpio_periph.h +++ b/components/soc/include/soc/gpio_periph.h @@ -6,11 +6,7 @@ #pragma once #include -#include "soc/io_mux_reg.h" -#include "soc/gpio_struct.h" -#include "soc/gpio_reg.h" #include "soc/soc_caps.h" -#include "soc/gpio_sig_map.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/include/soc/rtc_periph.h b/components/soc/include/soc/rtc_periph.h index 15dc77846c7..028e11f5cc8 100644 --- a/components/soc/include/soc/rtc_periph.h +++ b/components/soc/include/soc/rtc_periph.h @@ -7,7 +7,6 @@ #pragma once #include -#include "rtc_io_periph.h" #include "rtc_cntl_periph.h" #include "soc/soc_caps.h" diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 08a2b3bb56c..234e8ef966a 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -13,7 +13,7 @@ endif() if(non_os_build OR CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) set(srcs "spi_flash_wrap.c") - set(priv_requires bootloader_support soc) + set(priv_requires bootloader_support soc esp_hal_gpio) else() set(srcs "flash_brownout_hook.c") @@ -53,7 +53,7 @@ else() "spi_flash_os_func_noos.c") list(APPEND srcs ${cache_srcs}) - set(priv_requires bootloader_support soc esp_mm) + set(priv_requires bootloader_support soc esp_hal_gpio esp_mm) if(${target} STREQUAL "esp32s2") list(APPEND priv_requires esp_security) diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index cd541d66739..2d7a436f0de 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -163,6 +163,9 @@ INPUT = \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth.h \ $(PROJECT_PATH)/components/esp_event/include/esp_event_base.h \ $(PROJECT_PATH)/components/esp_event/include/esp_event.h \ + $(PROJECT_PATH)/components/esp_hal_gpio/include/hal/gpio_types.h \ + $(PROJECT_PATH)/components/esp_hal_gpio/include/hal/rtc_io_types.h \ + $(PROJECT_PATH)/components/esp_hal_gpio/include/hal/sdm_types.h \ $(PROJECT_PATH)/components/esp_hal_timg/include/hal/timer_types.h \ $(PROJECT_PATH)/components/esp_hal_i2c/include/hal/i2c_types.h \ $(PROJECT_PATH)/components/esp_hal_i2s/include/hal/i2s_types.h \ @@ -260,12 +263,9 @@ INPUT = \ $(PROJECT_PATH)/components/hal/include/hal/adc_types.h \ $(PROJECT_PATH)/components/hal/include/hal/color_types.h \ $(PROJECT_PATH)/components/hal/include/hal/dac_types.h \ - $(PROJECT_PATH)/components/hal/include/hal/gpio_types.h \ $(PROJECT_PATH)/components/hal/include/hal/ledc_types.h \ $(PROJECT_PATH)/components/hal/include/hal/mcpwm_types.h \ - $(PROJECT_PATH)/components/hal/include/hal/rtc_io_types.h \ $(PROJECT_PATH)/components/hal/include/hal/sdio_slave_types.h \ - $(PROJECT_PATH)/components/hal/include/hal/sdm_types.h \ $(PROJECT_PATH)/components/hal/include/hal/spi_types.h \ $(PROJECT_PATH)/components/hal/include/hal/temperature_sensor_types.h \ $(PROJECT_PATH)/components/hal/include/hal/twai_types.h \ diff --git a/examples/system/ulp/ulp_riscv/ds18b20_onewire/main/ulp_riscv_ds18b20_example_main.c b/examples/system/ulp/ulp_riscv/ds18b20_onewire/main/ulp_riscv_ds18b20_example_main.c index 4d95abc450c..7dee1033e56 100644 --- a/examples/system/ulp/ulp_riscv/ds18b20_onewire/main/ulp_riscv_ds18b20_example_main.c +++ b/examples/system/ulp/ulp_riscv/ds18b20_onewire/main/ulp_riscv_ds18b20_example_main.c @@ -17,7 +17,6 @@ #include "soc/rtc_cntl_reg.h" #include "soc/sens_reg.h" #include "soc/rtc_periph.h" -#include "hal/rtc_io_ll.h" #include "driver/gpio.h" #include "driver/rtc_io.h" #include "ulp_riscv.h" From 06970a5284fc55d11bef3b2b9d56774505735daf Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 10 Nov 2025 19:07:16 +0800 Subject: [PATCH 2/2] refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio --- components/esp_driver_gpio/src/dedic_gpio.c | 47 ++++++++++--------- components/esp_driver_gpio/src/gpio.c | 23 +++++---- components/esp_driver_gpio/src/gpio_etm.c | 13 ++--- .../src/gpio_pin_glitch_filter.c | 5 +- components/esp_driver_gpio/src/rtc_io.c | 7 ++- .../main/test_dedicated_gpio.c | 9 ++-- components/esp_driver_sdm/src/sdm.c | 15 +++--- .../test_apps/sigma_delta/main/test_sdm.cpp | 11 +++-- .../esp32/include/hal/gpio_caps.h | 11 +++++ .../esp_hal_gpio/esp32/include/hal/gpio_ll.h | 3 -- .../esp32/include/hal/rtc_gpio_caps.h | 9 ++++ .../esp_hal_gpio/esp32/include/hal/sdm_caps.h | 13 +++++ .../esp_hal_gpio/esp32/include/hal/sdm_ll.h | 3 -- .../esp32c2/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32c2/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32c2/include/hal/gpio_caps.h | 11 +++++ .../esp32c3/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32c3/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32c3/include/hal/gpio_caps.h | 11 +++++ .../esp32c3/include/hal/sdm_caps.h | 13 +++++ .../esp_hal_gpio/esp32c3/include/hal/sdm_ll.h | 3 -- .../esp32c5/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32c5/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32c5/include/hal/gpio_caps.h | 12 +++++ .../esp32c5/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32c5/include/hal/rtc_gpio_caps.h | 11 +++++ .../esp32c5/include/hal/sdm_caps.h | 12 +++++ .../esp32c6/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32c6/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32c6/include/hal/gpio_caps.h | 12 +++++ .../esp32c6/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32c6/include/hal/rtc_gpio_caps.h | 11 +++++ .../esp32c6/include/hal/sdm_caps.h | 12 +++++ .../esp32c61/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32c61/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32c61/include/hal/gpio_caps.h | 12 +++++ .../esp32c61/include/hal/gpio_etm_ll.h | 3 -- .../esp32c61/include/hal/rtc_gpio_caps.h | 11 +++++ .../esp32h2/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32h2/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32h2/include/hal/gpio_caps.h | 12 +++++ .../esp32h2/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32h2/include/hal/rtc_gpio_caps.h | 9 ++++ .../esp32h2/include/hal/sdm_caps.h | 12 +++++ .../esp32h21/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32h21/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32h21/include/hal/gpio_caps.h | 12 +++++ .../esp32h21/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32h21/include/hal/rtc_gpio_caps.h | 9 ++++ .../esp32h21/include/hal/sdm_caps.h | 12 +++++ .../esp32h4/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32h4/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32h4/include/hal/gpio_caps.h | 12 +++++ .../esp32h4/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32h4/include/hal/rtc_gpio_caps.h | 11 +++++ .../esp32h4/include/hal/sdm_caps.h | 12 +++++ .../esp32p4/include/hal/dedic_gpio_caps.h | 14 ++++++ .../esp32p4/include/hal/dedic_gpio_cpu_ll.h | 3 -- .../esp32p4/include/hal/gpio_caps.h | 12 +++++ .../esp32p4/include/hal/gpio_etm_ll.h | 3 -- .../include/hal/gpio_glitch_filter_ll.h | 3 +- .../esp32p4/include/hal/rtc_gpio_caps.h | 11 +++++ .../esp32p4/include/hal/sdm_caps.h | 12 +++++ .../esp32s2/include/hal/dedic_gpio_caps.h | 13 +++++ .../esp32s2/include/hal/dedic_gpio_ll.h | 2 - .../esp32s2/include/hal/gpio_caps.h | 11 +++++ .../esp32s2/include/hal/rtc_gpio_caps.h | 9 ++++ .../esp32s2/include/hal/sdm_caps.h | 13 +++++ .../esp_hal_gpio/esp32s2/include/hal/sdm_ll.h | 3 -- .../esp32s3/include/hal/dedic_gpio_caps.h | 12 +++++ .../esp32s3/include/hal/gpio_caps.h | 11 +++++ .../esp32s3/include/hal/rtc_gpio_caps.h | 9 ++++ .../esp32s3/include/hal/sdm_caps.h | 13 +++++ .../esp_hal_gpio/esp32s3/include/hal/sdm_ll.h | 3 -- .../include/hal/dedic_gpio_periph.h | 7 ++- .../esp_hal_gpio/include/hal/sdm_periph.h | 10 ++-- components/esp_hal_mspi/CMakeLists.txt | 8 +++- components/esp_hal_mspi/spi_flash_hal.c | 6 +-- components/hal/CMakeLists.txt | 1 + components/hal/spi_hal_iram.c | 12 ++--- components/soc/esp32/include/soc/soc_caps.h | 4 -- .../soc/esp32/include/soc/soc_caps_full.h | 4 -- .../esp32c2/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c2/include/soc/soc_caps.h | 1 - .../soc/esp32c2/include/soc/soc_caps_full.h | 4 -- .../esp32c3/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c3/include/soc/soc_caps.h | 1 - .../soc/esp32c3/include/soc/soc_caps_full.h | 8 ---- .../esp32c5/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32c5/include/soc/soc_caps.h | 3 -- .../soc/esp32c5/include/soc/soc_caps_full.h | 8 ---- .../esp32c6/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32c6/include/soc/soc_caps.h | 3 -- .../soc/esp32c6/include/soc/soc_caps_full.h | 8 ---- .../esp32c61/include/soc/Kconfig.soc_caps.in | 8 ---- .../soc/esp32c61/include/soc/soc_caps.h | 3 -- .../soc/esp32c61/include/soc/soc_caps_full.h | 4 -- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32h2/include/soc/soc_caps.h | 3 -- .../soc/esp32h2/include/soc/soc_caps_full.h | 8 ---- .../esp32h21/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32h21/include/soc/soc_caps.h | 3 -- .../soc/esp32h21/include/soc/soc_caps_full.h | 8 ---- .../esp32h4/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32h4/include/soc/soc_caps.h | 3 -- .../soc/esp32h4/include/soc/soc_caps_full.h | 8 ---- .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32p4/include/soc/soc_caps.h | 4 +- .../soc/esp32p4/include/soc/soc_caps_full.h | 8 ---- .../esp32s2/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32s2/include/soc/soc_caps.h | 4 -- .../soc/esp32s2/include/soc/soc_caps_full.h | 8 ---- .../esp32s3/include/soc/Kconfig.soc_caps.in | 8 ---- components/soc/esp32s3/include/soc/soc_caps.h | 3 -- .../soc/esp32s3/include/soc/soc_caps_full.h | 8 ---- 120 files changed, 622 insertions(+), 340 deletions(-) create mode 100644 components/esp_hal_gpio/esp32/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h create mode 100644 components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h create mode 100644 components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c index 3d9b99bd599..64cd1234286 100644 --- a/components/esp_driver_gpio/src/dedic_gpio.c +++ b/components/esp_driver_gpio/src/dedic_gpio.c @@ -17,6 +17,7 @@ #include "esp_cpu.h" #include "soc/soc_caps_full.h" #include "soc/io_mux_reg.h" +#include "hal/dedic_gpio_caps.h" #include "hal/dedic_gpio_cpu_ll.h" #include "esp_private/gpio.h" #include "esp_private/periph_ctrl.h" @@ -25,10 +26,10 @@ #include "driver/dedic_gpio.h" #include "hal/dedic_gpio_periph.h" -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) #include "soc/dedic_gpio_struct.h" #endif -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) #include "hal/dedic_gpio_ll.h" #endif @@ -50,11 +51,11 @@ struct dedic_gpio_platform_t { uint32_t in_occupied_mask; // mask of input channels that already occupied #if SOC_DEDIC_GPIO_HAS_INTERRUPT intr_handle_t intr_hdl; // interrupt handle - dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback function for input channel - void *cb_args[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback arguments for input channel - dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel + dedic_gpio_isr_callback_t cbs[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // array of callback function for input channel + void *cb_args[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // array of callback arguments for input channel + dedic_gpio_bundle_t *in_bundles[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel #endif -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) dedic_dev_t *dev; #endif }; @@ -81,18 +82,18 @@ static esp_err_t dedic_gpio_build_platform(int core_id) // initialize platform members s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; // initial occupy_mask: 1111...100...0 - s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1); - s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1); -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS + s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1); + s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1); +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) s_platform[core_id]->dev = &DEDIC_GPIO; -#endif // DEDIC_GPIO_LL_ALLOW_REG_ACCESS -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) // enable dedicated GPIO register clock PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(true); dedic_gpio_ll_reset_register(); } -#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) } } _lock_release(&s_platform_mutexlock[core_id]); @@ -113,12 +114,12 @@ static void dedic_gpio_break_platform(int core_id) if (s_platform[core_id]) { free(s_platform[core_id]); s_platform[core_id] = NULL; -#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) // disable the register clock if no GPIO channel is in use PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(false); } -#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CAPS_GET(CPU_PERIPH_ALWAYS_ENABLE) } _lock_release(&s_platform_mutexlock[core_id]); } @@ -222,11 +223,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure outwards channels uint32_t out_offset = 0; if (config->flags.out_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)); + ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) - config->array_size; i++) { + for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) { out_mask = pattern << i; out_offset = i; @@ -235,7 +236,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ } if (out_mask) { s_platform[core_id]->out_occupied_mask |= out_mask; -#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if DEDIC_GPIO_CAPS_GET(ALLOW_REG_ACCESS) // always enable instruction to access output GPIO, which has better performance than register access dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true); #endif @@ -248,11 +249,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure inwards channels uint32_t in_offset = 0; if (config->flags.in_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)); + ESP_GOTO_ON_FALSE(config->array_size <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU) - config->array_size; i++) { + for (size_t i = 0; i <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) { in_mask = pattern << i; in_offset = i; @@ -320,8 +321,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle) portENTER_CRITICAL(&s_platform[core_id]->spinlock); s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask); s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask); - if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1)) && - s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1))) { + if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1)) && + s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1))) { recycle_all = true; } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 0f0b32cb1d8..fe078d4baed 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -32,9 +32,12 @@ static const char *GPIO_TAG = "gpio"; #define GPIO_ISR_CORE_ID_UNINIT (3) -//default value for SOC_GPIO_SUPPORT_RTC_INDEPENDENT is 0 -#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0 +// On ESP32, those PADs which have RTC functions must set pullup/down/drv capability via RTC register. +// On other targets, digital IOs have their own registers to control pullup/down/drv capability, independent with RTC_IO (LP_IOMUX) registers. +#if CONFIG_IDF_TARGET_ESP32 +#define GPIO_RTCIO_ARE_INDEPENDENT 0 +#else // for any other target has RTC_IO (LP_IOMUX) registers +#define GPIO_RTCIO_ARE_INDEPENDENT 1 #endif typedef struct { @@ -77,7 +80,7 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -96,7 +99,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -115,7 +118,7 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -134,7 +137,7 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -701,7 +704,7 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -722,7 +725,7 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; - if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { + if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_RTCIO_ARE_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); @@ -1062,7 +1065,7 @@ esp_err_t gpio_get_io_config(gpio_num_t gpio_num, gpio_io_config_t *out_io_confi ESP_RETURN_ON_FALSE(out_io_config, ESP_ERR_INVALID_ARG, GPIO_TAG, "out_io_config is a null pointer"); gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, out_io_config); -#if !SOC_GPIO_SUPPORT_RTC_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0 +#if !GPIO_RTCIO_ARE_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0 if (rtc_gpio_is_valid_gpio(gpio_num)) { int rtcio_num = rtc_io_number_get(gpio_num); out_io_config->pu = rtcio_hal_is_pullup_enabled(rtcio_num); diff --git a/components/esp_driver_gpio/src/gpio_etm.c b/components/esp_driver_gpio/src/gpio_etm.c index d521a64e72d..ad4f117bb0b 100644 --- a/components/esp_driver_gpio/src/gpio_etm.c +++ b/components/esp_driver_gpio/src/gpio_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,7 @@ #include "esp_log.h" #include "esp_check.h" #include "soc/soc_caps.h" +#include "hal/gpio_caps.h" #include "hal/gpio_ll.h" #include "hal/gpio_etm_ll.h" #include "esp_private/etm_interface.h" @@ -29,10 +30,10 @@ typedef struct gpio_etm_event_t gpio_etm_event_t; typedef struct gpio_etm_group_t { portMUX_TYPE spinlock; gpio_etm_dev_t *dev; - uint8_t tasks[GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP]; // Array of the acquired action masks in each GPIO ETM task channel - uint8_t events[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP]; // Array of the acquired event masks in each GPIO ETM event channel + uint8_t tasks[GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP)]; // Array of the acquired action masks in each GPIO ETM task channel + uint8_t events[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)]; // Array of the acquired event masks in each GPIO ETM event channel uint8_t actions[SOC_GPIO_PIN_COUNT]; // Array of the masks of the added actions to each GPIO - uint8_t edges[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP]; // Array of the masks of the bound event edges in each GPIO ETM event channel + uint8_t edges[GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP)]; // Array of the masks of the bound event edges in each GPIO ETM event channel } gpio_etm_group_t; struct gpio_etm_event_t { @@ -63,7 +64,7 @@ static esp_err_t gpio_etm_acquire_event_channel(uint8_t event_mask, int *chan_id int free_chan_id = -1; // loop to search free event channel in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP; j++) { + for (int j = 0; j < GPIO_CAPS_GET(ETM_EVENT_CHANNELS_PER_GROUP); j++) { if (!group->events[j]) { free_chan_id = j; group->events[j] = event_mask; @@ -94,7 +95,7 @@ static esp_err_t gpio_etm_acquire_task_channel(uint8_t task_mask, int *chan_id) int free_chan_id = -1; // loop to search free task channel in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP; j++) { + for (int j = 0; j < GPIO_CAPS_GET(ETM_TASK_CHANNELS_PER_GROUP); j++) { if (!group->tasks[j]) { free_chan_id = j; group->tasks[j] = task_mask; diff --git a/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c b/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c index 2e62b784433..39e3c912956 100644 --- a/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c +++ b/components/esp_driver_gpio/src/gpio_pin_glitch_filter.c @@ -12,6 +12,7 @@ #include "hal/gpio_ll.h" #include "esp_clk_tree.h" #include "esp_private/io_mux.h" +#include "hal/gpio_caps.h" static const char *TAG = "gpio-filter"; @@ -93,11 +94,11 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf // create pm lock according to different clock source #if CONFIG_PM_ENABLE esp_pm_lock_type_t lock_type = ESP_PM_NO_LIGHT_SLEEP; -#if SOC_GPIO_FILTER_CLK_SUPPORT_APB +#if GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB) if (config->clk_src == GLITCH_FILTER_CLK_SRC_APB) { lock_type = ESP_PM_APB_FREQ_MAX; } -#endif // SOC_GPIO_FILTER_CLK_SUPPORT_APB +#endif // GPIO_CAPS_GET(FILTER_CLK_SUPPORT_APB) sprintf(filter->pm_lock_name, "filter_io_%d", config->gpio_num); // e.g. filter_io_0 ESP_GOTO_ON_ERROR(esp_pm_lock_create(lock_type, 0, filter->pm_lock_name, &filter->pm_lock), err, TAG, "create pm_lock failed"); diff --git a/components/esp_driver_gpio/src/rtc_io.c b/components/esp_driver_gpio/src/rtc_io.c index 362ad86c813..6e955feb7b2 100644 --- a/components/esp_driver_gpio/src/rtc_io.c +++ b/components/esp_driver_gpio/src/rtc_io.c @@ -16,6 +16,9 @@ #include "hal/rtc_io_hal.h" #include "hal/rtc_io_periph.h" #include "soc/soc_caps.h" +#if SOC_RTCIO_PIN_COUNT > 0 +#include "hal/rtc_gpio_caps.h" +#endif #if SOC_LP_GPIO_MATRIX_SUPPORTED #include "soc/lp_gpio_pins.h" #endif @@ -263,11 +266,11 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num) esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error"); -#if !SOC_RTCIO_EDGE_WAKE_SUPPORTED +#if !RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED) if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) { return ESP_ERR_INVALID_ARG; // Dont support this mode. } -#endif //!SOC_RTCIO_EDGE_WAKE_SUPPORTED +#endif //!RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED) RTCIO_ENTER_CRITICAL(); rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type); RTCIO_EXIT_CRITICAL(); diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index 097bcd08a02..a9ab9c8be35 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -12,6 +12,7 @@ #include "unity_test_utils.h" #include "esp_rom_sys.h" #include "soc/soc_caps_full.h" +#include "hal/dedic_gpio_caps.h" #include "hal/dedic_gpio_periph.h" #include "hal/dedic_gpio_cpu_ll.h" #include "driver/gpio.h" @@ -19,9 +20,9 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") { - const int test_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2] = {0}; - const int test2_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2 + 1] = {0}; - const int test3_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) + 1] = {0}; + const int test_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2] = {0}; + const int test2_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2 + 1] = {0}; + const int test3_gpios[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) + 1] = {0}; dedic_gpio_bundle_handle_t test_bundle, test_bundle2, test_bundle3 = NULL; dedic_gpio_bundle_config_t bundle_config = { .gpio_array = test_gpios, @@ -48,7 +49,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, dedic_gpio_new_bundle(&bundle_config, &test_bundle), "create bundle with half channels failed"); uint32_t mask = 0; TEST_ESP_OK(dedic_gpio_get_out_mask(test_bundle, &mask)); - TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask"); + TEST_ASSERT_EQUAL_MESSAGE((1 << (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask"); TEST_ESP_OK(dedic_gpio_get_in_mask(test_bundle, &mask)); TEST_ASSERT_EQUAL_MESSAGE(0, mask, "wrong in mask"); diff --git a/components/esp_driver_sdm/src/sdm.c b/components/esp_driver_sdm/src/sdm.c index 0cc91805a43..924d4cdfbef 100644 --- a/components/esp_driver_sdm/src/sdm.c +++ b/components/esp_driver_sdm/src/sdm.c @@ -23,6 +23,7 @@ #include "esp_clk_tree.h" #include "driver/gpio.h" #include "driver/sdm.h" +#include "hal/sdm_caps.h" #include "hal/sdm_periph.h" #include "hal/sdm_hal.h" #include "hal/sdm_ll.h" @@ -50,15 +51,15 @@ typedef struct sdm_channel_t sdm_channel_t; struct sdm_platform_t { _lock_t mutex; // platform level mutex lock - sdm_group_t *groups[SOC_SDM_ATTR(INST_NUM)]; // sdm group pool - int group_ref_counts[SOC_SDM_ATTR(INST_NUM)];// reference count used to protect group install/uninstall + sdm_group_t *groups[SDM_CAPS_GET(INST_NUM)]; // sdm group pool + int group_ref_counts[SDM_CAPS_GET(INST_NUM)];// reference count used to protect group install/uninstall }; struct sdm_group_t { int group_id; // Group ID, index from 0 portMUX_TYPE spinlock; // to protect per-group register level concurrent access sdm_hal_context_t hal; // hal context - sdm_channel_t *channels[SOC_SDM_ATTR(CHANS_PER_INST)]; // array of sdm channels + sdm_channel_t *channels[SDM_CAPS_GET(CHANS_PER_INST)]; // array of sdm channels sdm_clock_source_t clk_src; // Clock source #if CONFIG_PM_ENABLE esp_pm_lock_handle_t pm_lock; // PM lock, to prevent the system going into light sleep when SDM is running @@ -162,11 +163,11 @@ static sdm_group_t *sdm_acquire_group_handle(int group_id, sdm_clock_source_t cl ESP_LOGD(TAG, "new group (%d) at %p", group_id, group); #if CONFIG_PM_ENABLE esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP; -#if SDM_LL_FUNC_CLOCK_SUPPORT_APB +#if SDM_CAPS_GET(FUNC_CLOCK_SUPPORT_APB) if (clk_src == SDM_CLK_SRC_APB) { pm_type = ESP_PM_APB_FREQ_MAX; } -#endif // SDM_LL_FUNC_CLOCK_SUPPORT_APB +#endif // SDM_CAPS_GET(FUNC_CLOCK_SUPPORT_APB) if (esp_pm_lock_create(pm_type, 0, soc_sdm_signals[group_id].module_name, &group->pm_lock) != ESP_OK) { ESP_LOGE(TAG, "fail to create PM lock for group %d", group_id); } @@ -216,12 +217,12 @@ static esp_err_t sdm_register_to_group(sdm_channel_t *chan, sdm_clock_source_t c { sdm_group_t *group = NULL; int chan_id = -1; - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { group = sdm_acquire_group_handle(i, clk_src); ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i); // loop to search free unit in the group portENTER_CRITICAL(&group->spinlock); - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { if (!group->channels[j]) { chan_id = j; group->channels[j] = chan; diff --git a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp index 4940c0c218e..ea77cfd0dd1 100644 --- a/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp +++ b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp @@ -11,6 +11,7 @@ #include "unity.h" #include "driver/sdm.h" #include "hal/sdm_periph.h" +#include "hal/sdm_caps.h" #include "esp_attr.h" TEST_CASE("sdm_channel_install_uninstall", "[sdm]") @@ -25,17 +26,17 @@ TEST_CASE("sdm_channel_install_uninstall", "[sdm]") .allow_pd = false, }, }; - sdm_channel_handle_t chans[SOC_SDM_ATTR(INST_NUM)][SOC_SDM_ATTR(CHANS_PER_INST)] = {}; - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + sdm_channel_handle_t chans[SDM_CAPS_GET(INST_NUM)][SDM_CAPS_GET(CHANS_PER_INST)] = {}; + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(sdm_new_channel(&config, &chans[i][j])); } TEST_ESP_ERR(ESP_ERR_NOT_FOUND, sdm_new_channel(&config, &chans[0][0])); } printf("delete sdm channels\r\n"); - for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) { - for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) { + for (int i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { + for (int j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { TEST_ESP_OK(sdm_del_channel(chans[i][j])); } } diff --git a/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h new file mode 100644 index 00000000000..960a06d7042 --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_MATRIX_DELAY_NS 25 /* the gpio matrix signal routing const time */ diff --git a/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h index 7a94f87366a..234de25f0c6 100644 --- a/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/gpio_ll.h @@ -28,9 +28,6 @@ // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) -// the gpio matrix signal routing const time -#define GPIO_LL_MATRIX_DELAY_NS 25 - #define GPIO_LL_APP_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1)) #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2)) diff --git a/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h index 502d49d4a1c..02081cc9d5b 100644 --- a/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h index 74eec52ce92..e3c67f91f23 100644 --- a/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c2/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32c2/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h index 049b212ee31..c342299a8ba 100644 --- a/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h new file mode 100644 index 00000000000..7839dcc335f --- /dev/null +++ b/components/esp_hal_gpio/esp32c3/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h index 63a4d75b446..e5d14f48c85 100644 --- a/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32c3/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h index 52a06e7fc3e..0e85a7f2aa3 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h index f1f5622dfce..d70c2364e91 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/gpio_glitch_filter_ll.h @@ -15,8 +15,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32c5/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h index 50b98b95a84..1608eff7130 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h index 86d52ba43da..7f8f2387367 100644 --- a/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32c6/include/hal/gpio_glitch_filter_ll.h @@ -15,9 +15,10 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" // the max window size is expected to be 64, but due to a hardware issue, we need to limit it to 63 -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 63 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32c6/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h index fd955da5656..0cce6ab497b 100644 --- a/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h index 52a06e7fc3e..0e85a7f2aa3 100644 --- a/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h index 014605bae91..41b6c91bcb6 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h index 49281c3366f..44077aff549 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h index 5d19a96188f..c81d1b0c1c5 100644 --- a/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h2/include/hal/gpio_glitch_filter_ll.h @@ -15,9 +15,10 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" // the max window size is expected to be 64, but due to a hardware issue, we need to limit it to 63 -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 63 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h2/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h index c982d3e2b60..ac07b357a6b 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h index ba4e7fd73ff..4885ee3e164 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h index 45546d2ff93..4f53a17d859 100644 --- a/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h21/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h21/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..0ec5943e91f --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h index c982d3e2b60..ac07b357a6b 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h index 45d1433d11e..6b4162225ab 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h index 69944fc0d30..7383e8c3d9f 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h new file mode 100644 index 00000000000..142ba12ad57 --- /dev/null +++ b/components/esp_hal_gpio/esp32h4/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 4 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..8df3815d517 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_caps.h @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h index 0abb50c15d2..6a7434e1ab9 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/dedic_gpio_cpu_ll.h @@ -14,9 +14,6 @@ #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ -#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h new file mode 100644 index 00000000000..a8b9168c753 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h index 49281c3366f..44077aff549 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_etm_ll.h @@ -22,9 +22,6 @@ #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) -#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 -#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h b/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h index 8799ec6d3f9..cc95ba73205 100644 --- a/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h +++ b/components/esp_hal_gpio/esp32p4/include/hal/gpio_glitch_filter_ll.h @@ -9,8 +9,9 @@ #include #include "hal/assert.h" #include "soc/gpio_ext_struct.h" +#include "soc/gpio_ext_reg.h" -#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V + 1) #ifdef __cplusplus extern "C" { diff --git a/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..0aebcd28f56 --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr + +#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1 diff --git a/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h new file mode 100644 index 00000000000..9ccd64b34ec --- /dev/null +++ b/components/esp_hal_gpio/esp32p4/include/hal/sdm_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..ec92fb90fa2 --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ +#define _DEDIC_GPIO_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h index d377896cf8e..e8f83dcd202 100644 --- a/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/dedic_gpio_ll.h @@ -11,8 +11,6 @@ #include "soc/dedic_gpio_struct.h" #include "soc/system_reg.h" -#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32s2/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h index d4cb9a1ae23..591acb8140c 100644 --- a/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s2/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h new file mode 100644 index 00000000000..606b0bea769 --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/dedic_gpio_caps.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr + +#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h new file mode 100644 index 00000000000..97e5df2225e --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/gpio_caps.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr + +#define _GPIO_FILTER_CLK_SUPPORT_APB 1 diff --git a/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h new file mode 100644 index 00000000000..340f7a22c7c --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/rtc_gpio_caps.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr diff --git a/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h b/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h new file mode 100644 index 00000000000..fe517ba2211 --- /dev/null +++ b/components/esp_hal_gpio/esp32s3/include/hal/sdm_caps.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define SDM_CAPS_GET(_attr) _SDM_ ## _attr + +#define _SDM_INST_NUM 1 /* Number of SDM instances */ +#define _SDM_CHANS_PER_INST 8 /* Number of channels in each SDM instance */ +#define _SDM_FUNC_CLOCK_SUPPORT_APB 1 /* SDM function clock can be sourced from APB */ diff --git a/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h index 9965358f632..86d757688ab 100644 --- a/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h +++ b/components/esp_hal_gpio/esp32s3/include/hal/sdm_ll.h @@ -17,9 +17,6 @@ #define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1) -// Support APB as function clock -#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h b/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h index fe32aa9a8b4..8cc727dd160 100644 --- a/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h +++ b/components/esp_hal_gpio/include/hal/dedic_gpio_periph.h @@ -15,14 +15,13 @@ extern "C" { #endif #if SOC_HAS(DEDICATED_GPIO) -// helper macros to access module attributes -#define SOC_DEDIC_GPIO_ATTR(_attr) SOC_MODULE_ATTR(DEDIC_GPIO, _attr) +#include "hal/dedic_gpio_caps.h" typedef struct { const int irq; // Interrupt resource (-1 means no interrupt supported) struct { - const int in_sig_per_channel[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; - const int out_sig_per_channel[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)]; + const int in_sig_per_channel[DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)]; + const int out_sig_per_channel[DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)]; } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix } dedic_gpio_signal_conn_t; diff --git a/components/esp_hal_gpio/include/hal/sdm_periph.h b/components/esp_hal_gpio/include/hal/sdm_periph.h index 65f37a3dd91..27cff9cbc80 100644 --- a/components/esp_hal_gpio/include/hal/sdm_periph.h +++ b/components/esp_hal_gpio/include/hal/sdm_periph.h @@ -16,23 +16,21 @@ #include "soc/retention_periph_defs.h" #endif // SOC_HAS(PAU) -// helper macros to access module attributes -#define SOC_SDM_ATTR(_attr) SOC_MODULE_ATTR(SDM, _attr) - #ifdef __cplusplus extern "C" { #endif #if SOC_HAS(SDM) +#include "hal/sdm_caps.h" typedef struct { const char *module_name; // Module name struct { const int sig_id_matrix; // signal ID in the GPIO matrix - } channels[SOC_SDM_ATTR(CHANS_PER_INST)]; + } channels[SDM_CAPS_GET(CHANS_PER_INST)]; } soc_sdm_signal_desc_t; -extern const soc_sdm_signal_desc_t soc_sdm_signals[SOC_SDM_ATTR(INST_NUM)]; +extern const soc_sdm_signal_desc_t soc_sdm_signals[SDM_CAPS_GET(INST_NUM)]; #if SOC_HAS(PAU) @@ -42,7 +40,7 @@ typedef struct { const size_t array_size; // Size of the regdma_entry_array } soc_sdm_retention_desc_t; -extern const soc_sdm_retention_desc_t soc_sdm_retention_infos[SOC_SDM_ATTR(INST_NUM)]; +extern const soc_sdm_retention_desc_t soc_sdm_retention_infos[SDM_CAPS_GET(INST_NUM)]; #endif // SOC_HAS(PAU) diff --git a/components/esp_hal_mspi/CMakeLists.txt b/components/esp_hal_mspi/CMakeLists.txt index 21f45931725..3fc892961b2 100644 --- a/components/esp_hal_mspi/CMakeLists.txt +++ b/components/esp_hal_mspi/CMakeLists.txt @@ -4,6 +4,11 @@ idf_build_get_property(esp_tee_build ESP_TEE_BUILD) set(srcs) set(includes "include" "${target}/include") +set(priv_requires) +if(${target} STREQUAL "esp32") + list(APPEND priv_requires esp_hal_gpio) +endif() + if(esp_tee_build) if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1) list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c") @@ -26,4 +31,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} - REQUIRES soc hal) + REQUIRES soc hal + PRIV_REQUIRES "${priv_requires}") diff --git a/components/esp_hal_mspi/spi_flash_hal.c b/components/esp_hal_mspi/spi_flash_hal.c index 101ac5154bb..5a9f443a436 100644 --- a/components/esp_hal_mspi/spi_flash_hal.c +++ b/components/esp_hal_mspi/spi_flash_hal.c @@ -11,7 +11,7 @@ #include #include #include "soc/soc_caps.h" -#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS +#include "hal/gpio_caps.h" //for GPIO_CAPS_GET(MATRIX_DELAY_NS) #include "hal/spi_flash_hal.h" #include "hal/assert.h" #include "hal/log.h" @@ -66,8 +66,8 @@ static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk //calculate how many apb clocks a period has const int apbclk_n = APB_CLK_FREQ / eff_clk; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 6e0dba99eae..4f74be5e7ea 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -170,6 +170,7 @@ elseif(NOT BOOTLOADER_BUILD) endif() if(CONFIG_SOC_GPSPI_SUPPORTED) + # Remember to add esp_hal_gpio to esp_hal_spi PRIV_REQUIRES!!! list(APPEND srcs "spi_hal.c" "spi_hal_iram.c" diff --git a/components/hal/spi_hal_iram.c b/components/hal/spi_hal_iram.c index cfde4fd5182..f77ec2f7528 100644 --- a/components/hal/spi_hal_iram.c +++ b/components/hal/spi_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ #include "hal/spi_hal.h" #include "hal/log.h" #include "hal/assert.h" -#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS +#include "hal/gpio_caps.h" //for GPIO_CAPS_GET(MATRIX_DELAY_NS) #include "soc/ext_mem_defs.h" #include "soc/soc_caps.h" @@ -75,8 +75,8 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int //how many apb clocks a period has const int spiclk_apb_n = source_freq_hz / eff_clk; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. @@ -109,8 +109,8 @@ int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns) { const int apbclk_kHz = APB_CLK_FREQ / 1000; int gpio_delay_ns = 0; -#if GPIO_LL_MATRIX_DELAY_NS - gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#if GPIO_CAPS_GET(MATRIX_DELAY_NS) + gpio_delay_ns = gpio_is_used ? GPIO_CAPS_GET(MATRIX_DELAY_NS) : 0; #endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 39c9bd8fc9a..a8903e7de89 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -180,10 +180,6 @@ #define SOC_GPIO_PORT (1U) #define SOC_GPIO_PIN_COUNT 40 -// SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must -// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to -// control pullup/down/capability, independent with RTC registers. - // 0~39 valid except 24, 28~31 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31)) // GPIO >= 34 are input only diff --git a/components/soc/esp32/include/soc/soc_caps_full.h b/components/soc/esp32/include/soc/soc_caps_full.h index 5eaba84584c..8e64cba1c70 100644 --- a/components/soc/esp32/include/soc/soc_caps_full.h +++ b/components/soc/esp32/include/soc/soc_caps_full.h @@ -9,9 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 10 // Number of touch sensor channels diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 4f0620fa26a..bd0b5055093 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -283,10 +283,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index e12c2d482cc..6a1e185aca6 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -124,7 +124,6 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 21 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) diff --git a/components/soc/esp32c2/include/soc/soc_caps_full.h b/components/soc/esp32c2/include/soc/soc_caps_full.h index 185c9ed19f9..ca1d6414d90 100644 --- a/components/soc/esp32c2/include/soc/soc_caps_full.h +++ b/components/soc/esp32c2/include/soc/soc_caps_full.h @@ -8,7 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 7b13f91ad2d..6879a0145ef 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -379,10 +379,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 19d4c25b6ba..1d2ee74d59b 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -163,7 +163,6 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 22 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) diff --git a/components/soc/esp32c3/include/soc/soc_caps_full.h b/components/soc/esp32c3/include/soc/soc_caps_full.h index 2dd4e7932c0..ca1d6414d90 100644 --- a/components/soc/esp32c3/include/soc/soc_caps_full.h +++ b/components/soc/esp32c3/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 05661030505..ca151f8d360 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -555,10 +555,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -623,10 +619,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 7cf47cb950c..b1313a95c96 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -219,8 +219,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // LP IO peripherals have independent clock gating to manage @@ -256,7 +254,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps_full.h b/components/soc/esp32c5/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32c5/include/soc/soc_caps_full.h +++ b/components/soc/esp32c5/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 5e94b8ec6a6..2e6785ae6ff 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -475,10 +475,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -543,10 +539,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 88ebb7e8b15..b29be2880f5 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -194,8 +194,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C6 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // LP IO peripherals have independent clock gating to manage @@ -231,7 +229,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32c6/include/soc/soc_caps_full.h b/components/soc/esp32c6/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32c6/include/soc/soc_caps_full.h +++ b/components/soc/esp32c6/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index bc99bec18d9..4db0ed97667 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -431,10 +431,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y @@ -499,10 +495,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_ANA_CMPR_NUM int default 1 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index ab325171cf6..26132f13643 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -177,8 +177,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) @@ -215,7 +213,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*------------------------- Analog Comparator CAPS ---------------------------*/ #define SOC_ANA_CMPR_NUM (1U) diff --git a/components/soc/esp32c61/include/soc/soc_caps_full.h b/components/soc/esp32c61/include/soc/soc_caps_full.h index 185c9ed19f9..ca1d6414d90 100644 --- a/components/soc/esp32c61/include/soc/soc_caps_full.h +++ b/components/soc/esp32c61/include/soc/soc_caps_full.h @@ -8,7 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 633711f08e2..751b58d43f8 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -507,10 +507,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 57563c2993a..fafa48bcf70 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -220,9 +220,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) -// Digital IOs have their own registers to control pullup/down/capability -// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32h2/include/soc/soc_caps_full.h b/components/soc/esp32h2/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h2/include/soc/soc_caps_full.h +++ b/components/soc/esp32h2/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 4384253e2bd..2b24aaca173 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -399,10 +399,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index ad0da4fca0e..d10a369e597 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -202,9 +202,6 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has no full LP IO subsystem, GPIO5~11 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) -// Digital IOs have their own registers to control pullup/down/capability -// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) diff --git a/components/soc/esp32h21/include/soc/soc_caps_full.h b/components/soc/esp32h21/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h21/include/soc/soc_caps_full.h +++ b/components/soc/esp32h21/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 605b50bcc6b..bfb0ddf52c0 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -351,10 +351,6 @@ config SOC_GPIO_ETM_TASKS_PER_GROUP int default 8 -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y @@ -395,10 +391,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 458ffc11b83..6b2abd9d942 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -218,8 +218,6 @@ #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem -// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1 // LP IO peripherals have independent clock gating to manage #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) @@ -246,7 +244,6 @@ when the pins are switched to RTC function. */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32h4/include/soc/soc_caps_full.h b/components/soc/esp32h4/include/soc/soc_caps_full.h index 0e28befab1c..ca1d6414d90 100644 --- a/components/soc/esp32h4/include/soc/soc_caps_full.h +++ b/components/soc/esp32h4/include/soc/soc_caps_full.h @@ -8,11 +8,3 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 93ed278ace3..028eb125539 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -671,10 +671,6 @@ config SOC_GPIO_SUPPORT_ETM bool default y -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y @@ -755,10 +751,6 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_RTCIO_EDGE_WAKE_SUPPORTED - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index e97b33a7064..b5545d36d1d 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -250,8 +250,7 @@ #define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem -// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) + // GPIO0~15 on ESP32P4 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) @@ -292,7 +291,6 @@ */ #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 -#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 diff --git a/components/soc/esp32p4/include/soc/soc_caps_full.h b/components/soc/esp32p4/include/soc/soc_caps_full.h index 33259a694d3..655b7649040 100644 --- a/components/soc/esp32p4/include/soc/soc_caps_full.h +++ b/components/soc/esp32p4/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 14 // Number of touch sensor channels diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 6e4533574f7..088f8f0fb02 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -379,14 +379,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index d50c1c3c1b2..701af3e4461 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -167,11 +167,7 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 47 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 -// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register. -// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S2 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) diff --git a/components/soc/esp32s2/include/soc/soc_caps_full.h b/components/soc/esp32s2/include/soc/soc_caps_full.h index a79d5014ac5..1cedce872cd 100644 --- a/components/soc/esp32s2/include/soc/soc_caps_full.h +++ b/components/soc/esp32s2/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 15 // Number of touch sensor channels diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index fcef9d594bc..5a062d5c0e0 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -443,14 +443,6 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 09cb7e37a52..c6415e6d634 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -179,10 +179,7 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 49 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 -// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S3 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) diff --git a/components/soc/esp32s3/include/soc/soc_caps_full.h b/components/soc/esp32s3/include/soc/soc_caps_full.h index a79d5014ac5..1cedce872cd 100644 --- a/components/soc/esp32s3/include/soc/soc_caps_full.h +++ b/components/soc/esp32s3/include/soc/soc_caps_full.h @@ -9,13 +9,5 @@ #include "soc/soc_caps.h" #include "soc/soc_caps_eval.h" -/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ -#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances -#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance - -/*------------------------------- Dedicated GPIO ------------------------------*/ -#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ -#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ - /*------------------------------- Touch Sensor ------------------------------------*/ #define _SOC_CAPS_TOUCH_CHAN_NUM 15 // Number of touch sensor channels