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Merge branch 'esp32c5_trace_encoder' into 'master'

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feat(esp_riscv_trace): add ESP32-C5 support

See merge request espressif/esp-idf!51384
This commit is contained in:
Erhan Kurubas
2026-08-07 13:45:10 +02:00
parent b89de9bbaf 1a59c3e769
commit 57ccd12f17
12 changed files with 302 additions and 7 deletions
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components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
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@@ -1878,3 +1878,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 2
config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+1
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@@ -698,3 +698,4 @@
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (2U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */