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Merge branch 'fix/spi_master_bit_trans_add_check_v5.4' into 'release/v5.4'

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fix(driver_spi): spi master bit length check and set idle level for all data pin v5.4

See merge request espressif/esp-idf!45135
This commit is contained in:
Jiang Jiang Jian
2026-03-15 13:03:17 +08:00
parent 525343e488 53458fc6aa
commit 5729128d7c
19 changed files with 262 additions and 93 deletions
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components/hal/esp32p4/include/hal/spi_ll.h
+9 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -41,6 +41,8 @@ extern "C" {
#define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_TX_MINI_EXTRA_BITS 1 //Minimum length of TX non byte aligned data in bits
#define SPI_LL_RX_MINI_EXTRA_BITS 1 //Minimum length of RX non byte aligned data in bits
#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral
#define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
@@ -913,13 +915,16 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**