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feat(esp_hw_support): support entry 2 xtalx2 power pu in esp32h4

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This commit is contained in:
hebinglin
2026-05-21 19:55:37 +08:00
parent 2c91b280f4
commit 5710783a89
8 changed files with 101 additions and 1 deletions
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components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+4
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@@ -1223,6 +1223,10 @@ config SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH
bool
default y
config SOC_PM_XTALX2_PD_IN_MODEM_STATES
bool
default y
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
components/soc/esp32h4/include/soc/retention_periph_defs.h
+1
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@@ -56,6 +56,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_BLE_MAC = 30,
SLEEP_RETENTION_MODULE_BT_BB = 31,
SLEEP_RETENTION_MODULE_802154_MAC = 32,
SLEEP_RETENTION_MODULE_POWER = 33,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
components/soc/esp32h4/include/soc/soc_caps.h
+1
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@@ -515,6 +515,7 @@
#define SOC_PM_RETENTION_MODULE_NUM (64)
#define SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH (1) // In ESP32H4, RTC_PERIPH should be pd only together with TOP, otherwise there is some current leak.
#define SOC_PM_XTALX2_PD_IN_MODEM_STATES (1)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
components/soc/include/soc/regdma.h
+2 -1
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@@ -68,7 +68,7 @@ extern "C" {
#define REGDMA_JPEG_LINK(_pri) ((0x28 << 8) | _pri)
#define REGDMA_LCDCAM_LINK(_pri) ((0x29 << 8) | _pri)
#define REGDMA_H264_LINK(_pri) ((0x2a << 8) | _pri)
#define REGDMA_POWER_LINK(_pri) ((0xFD << 8) | _pri)
#define REGDMA_CLOCK_ICG_LINK(_pri) ((0xFE << 8) | _pri)
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
@@ -79,6 +79,7 @@ extern "C" {
#define REGDMA_LINK_PRI_WIFI_MAC_BB REGDMA_LINK_PRI_3
#define REGDMA_LINK_PRI_NON_CRITICAL_TEE_APM REGDMA_LINK_PRI_4
#define REGDMA_LINK_PRI_BT_MAC_BB REGDMA_LINK_PRI_5
#define REGDMA_LINK_PRI_POWER REGDMA_LINK_PRI_5
#define REGDMA_LINK_PRI_SYS_PERIPH_HIGH REGDMA_LINK_PRI_5 // INT_MTX & HP_SYSTEM & Console UART
#define REGDMA_LINK_PRI_SYS_PERIPH_LOW REGDMA_LINK_PRI_6 // TG0 & IO MUX & SPI MEM & Systimer
#define REGDMA_LINK_PRI_GENERAL_PERIPH REGDMA_LINK_PRI_7 // Low retenion priority for general peripherals