diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h index e1f54ec7bba..9be06b72dc6 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h @@ -33,8 +33,9 @@ extern "C" { #define SPI1_MEM_C_SLV_ST_S 4 /** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_PE (BIT(17)) #define SPI1_MEM_C_FLASH_PE_M (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_HPM (BIT(19)) #define SPI1_MEM_C_FLASH_HPM_M (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RES (BIT(20)) #define SPI1_MEM_C_FLASH_RES_M (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_DP (BIT(21)) #define SPI1_MEM_C_FLASH_DP_M (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_CE (BIT(22)) #define SPI1_MEM_C_FLASH_CE_M (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_BE (BIT(23)) #define SPI1_MEM_C_FLASH_BE_M (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_SE (BIT(24)) #define SPI1_MEM_C_FLASH_SE_M (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_PP (BIT(25)) #define SPI1_MEM_C_FLASH_PP_M (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WRSR (BIT(26)) #define SPI1_MEM_C_FLASH_WRSR_M (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RDSR (BIT(27)) #define SPI1_MEM_C_FLASH_RDSR_M (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RDID (BIT(28)) #define SPI1_MEM_C_FLASH_RDID_M (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WRDI (BIT(29)) #define SPI1_MEM_C_FLASH_WRDI_M (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WREN (BIT(30)) #define SPI1_MEM_C_FLASH_WREN_M (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_READ (BIT(31)) #define SPI1_MEM_C_FLASH_READ_M (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_C_FCS_CRC_EN_M (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S) @@ -233,14 +248,15 @@ extern "C" { #define SPI1_MEM_C_FCS_CRC_EN_S 10 /** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_TX_CRC_EN (BIT(11)) #define SPI1_MEM_C_TX_CRC_EN_M (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S) #define SPI1_MEM_C_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_C_TX_CRC_EN_S 11 /** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout - * and spi1_mem_c_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ #define SPI1_MEM_C_FASTRD_MODE (BIT(13)) #define SPI1_MEM_C_FASTRD_MODE_M (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S) @@ -255,7 +271,8 @@ extern "C" { #define SPI1_MEM_C_FREAD_DUAL_S 14 /** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with - * spi1_mem_c_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_RESANDRES (BIT(15)) #define SPI1_MEM_C_RESANDRES_M (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_WRSR_2B (BIT(22)) #define SPI1_MEM_C_WRSR_2B_M (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S) @@ -328,13 +346,30 @@ extern "C" { #define SPI1_MEM_C_CLK_MODE_V 0x00000003U #define SPI1_MEM_C_CLK_MODE_S 0 /** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES_M (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S) #define SPI1_MEM_C_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES_S 2 +/** SPI1_MEM_C_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ +#define SPI1_MEM_C_CS_HOLD_DLY_PER 0x000001FFU +#define SPI1_MEM_C_CS_HOLD_DLY_PER_M (SPI1_MEM_C_CS_HOLD_DLY_PER_V << SPI1_MEM_C_CS_HOLD_DLY_PER_S) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_V 0x000001FFU +#define SPI1_MEM_C_CS_HOLD_DLY_PER_S 12 +/** SPI1_MEM_C_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN (BIT(23)) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V 0x00000001U +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S 23 /** SPI1_MEM_C_CTRL2_REG register * SPI1 control2 register. @@ -353,22 +388,22 @@ extern "C" { */ #define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14) /** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N. */ #define SPI1_MEM_C_CLKCNT_L 0x000000FFU #define SPI1_MEM_C_CLKCNT_L_M (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S) #define SPI1_MEM_C_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_L_S 0 /** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1). */ #define SPI1_MEM_C_CLKCNT_H 0x000000FFU #define SPI1_MEM_C_CLKCNT_H_M (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S) #define SPI1_MEM_C_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_H_S 8 /** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is - * system/(spi1_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_C_CLKCNT_N+1) */ #define SPI1_MEM_C_CLKCNT_N 0x000000FFU #define SPI1_MEM_C_CLKCNT_N_M (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S) @@ -387,7 +422,7 @@ extern "C" { */ #define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18) /** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ #define SPI1_MEM_C_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_C_CK_OUT_EDGE_M (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S) @@ -422,16 +457,18 @@ extern "C" { #define SPI1_MEM_C_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_C_FWRITE_QIO_S 15 /** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_USR_MISO_HIGHPART (BIT(24)) #define SPI1_MEM_C_USR_MISO_HIGHPART_M (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S) #define SPI1_MEM_C_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_C_USR_MISO_HIGHPART_S 24 /** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_USR_MOSI_HIGHPART (BIT(25)) #define SPI1_MEM_C_USR_MOSI_HIGHPART_M (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S) @@ -485,7 +522,7 @@ extern "C" { */ #define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c) /** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ #define SPI1_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU @@ -548,14 +585,15 @@ extern "C" { */ #define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c) /** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ #define SPI1_MEM_C_STATUS 0x0000FFFFU #define SPI1_MEM_C_STATUS_M (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S) #define SPI1_MEM_C_STATUS_V 0x0000FFFFU #define SPI1_MEM_C_STATUS_S 0 /** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_WB_MODE 0x000000FFU #define SPI1_MEM_C_WB_MODE_M (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S) @@ -599,10 +637,13 @@ extern "C" { /** SPI1_MEM_C_TX_CRC_REG register * SPI1 TX CRC data register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38) /** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_TX_CRC_DATA 0xFFFFFFFFU #define SPI1_MEM_C_TX_CRC_DATA_M (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S) @@ -611,10 +652,13 @@ extern "C" { /** SPI1_MEM_C_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c) /** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S) @@ -622,7 +666,8 @@ extern "C" { #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 /** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_c_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDIN_DUAL (BIT(3)) #define SPI1_MEM_C_FDIN_DUAL_M (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S) @@ -630,7 +675,8 @@ extern "C" { #define SPI1_MEM_C_FDIN_DUAL_S 3 /** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_C_FDOUT_DUAL_M (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S) @@ -638,7 +684,8 @@ extern "C" { #define SPI1_MEM_C_FDOUT_DUAL_S 4 /** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FADDR_DUAL (BIT(5)) #define SPI1_MEM_C_FADDR_DUAL_M (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S) @@ -646,7 +693,8 @@ extern "C" { #define SPI1_MEM_C_FADDR_DUAL_S 5 /** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDIN_QUAD (BIT(6)) #define SPI1_MEM_C_FDIN_QUAD_M (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S) @@ -654,7 +702,8 @@ extern "C" { #define SPI1_MEM_C_FDIN_QUAD_S 6 /** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_C_FDOUT_QUAD_M (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S) @@ -662,7 +711,8 @@ extern "C" { #define SPI1_MEM_C_FDOUT_QUAD_S 7 /** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FADDR_QUAD (BIT(8)) #define SPI1_MEM_C_FADDR_QUAD_M (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S) @@ -891,8 +941,8 @@ extern "C" { #define SPI1_MEM_C_WAITI_ADDR_EN_S 2 /** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_C_WAITI_ADDR_EN is cleared. */ #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S) @@ -1010,8 +1060,8 @@ extern "C" { #define SPI1_MEM_C_PES_END_EN_V 0x00000001U #define SPI1_MEM_C_PES_END_EN_S 24 /** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ #define SPI1_MEM_C_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_C_SUS_TIMEOUT_CNT_M (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S) @@ -1059,8 +1109,8 @@ extern "C" { #define SPI1_MEM_C_WAIT_PESR_CMD_2B_S 1 /** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ #define SPI1_MEM_C_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_C_FLASH_HPM_DLY_128_M (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S) @@ -1068,8 +1118,8 @@ extern "C" { #define SPI1_MEM_C_FLASH_HPM_DLY_128_S 2 /** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ #define SPI1_MEM_C_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_C_FLASH_RES_DLY_128_M (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S) @@ -1077,8 +1127,8 @@ extern "C" { #define SPI1_MEM_C_FLASH_RES_DLY_128_S 3 /** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ #define SPI1_MEM_C_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_C_FLASH_DP_DLY_128_M (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S) @@ -1086,9 +1136,9 @@ extern "C" { #define SPI1_MEM_C_FLASH_DP_DLY_128_S 4 /** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ #define SPI1_MEM_C_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_C_FLASH_PER_DLY_128_M (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S) @@ -1096,9 +1146,9 @@ extern "C" { #define SPI1_MEM_C_FLASH_PER_DLY_128_S 5 /** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ #define SPI1_MEM_C_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_C_FLASH_PES_DLY_128_M (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S) @@ -1242,16 +1292,16 @@ extern "C" { #define SPI1_MEM_C_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_PES_END_INT_RAW_S 1 /** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ #define SPI1_MEM_C_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_C_WPE_END_INT_RAW_M (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S) #define SPI1_MEM_C_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_WPE_END_INT_RAW_S 2 /** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI1_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) @@ -1259,8 +1309,8 @@ extern "C" { #define SPI1_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_SLV_ST_END_INT_RAW_S 3 /** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI1_MEM_C_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_C_MST_ST_END_INT_RAW_M (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S) @@ -1379,8 +1429,8 @@ extern "C" { #define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S 14 /** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI1_MEM_C_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1468,7 +1518,7 @@ extern "C" { * Version control register */ #define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc) -/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128; +/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ #define SPI1_MEM_C_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h index 52941e2d361..84903e35775 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h @@ -29,8 +29,9 @@ typedef union { uint32_t reserved_8:9; /** flash_pe : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -130,7 +144,7 @@ typedef union { struct { uint32_t reserved_0:9; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; @@ -152,13 +166,15 @@ typedef union { uint32_t fwrite_qio:1; uint32_t reserved_16:8; /** usr_miso_highpart : HRO; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usr_mosi_highpart:1; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; @@ -195,7 +211,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -268,16 +284,18 @@ typedef union { /** fcs_crc_en : HRO; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : HRO; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout - * and spi1_mem_c_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -286,7 +304,8 @@ typedef union { uint32_t fread_dual:1; /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with - * spi1_mem_c_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +328,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +358,23 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_per:9; + uint32_t reserved_21:2; + /** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ + uint32_t cs_hold_dly_per_en:1; + uint32_t reserved_24:8; }; uint32_t val; } spi1_mem_c_ctrl1_reg_t; @@ -367,16 +399,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is - * system/(spi1_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_C_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -422,11 +454,12 @@ typedef union { typedef union { struct { /** status : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; uint32_t reserved_24:8; @@ -471,37 +504,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_c_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -531,8 +571,8 @@ typedef union { uint32_t waiti_addr_en:1; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_C_WAITI_ADDR_EN is cleared. */ uint32_t waiti_addr_cyclelen:2; uint32_t reserved_5:4; @@ -613,8 +653,8 @@ typedef union { */ uint32_t pes_end_en:1; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ uint32_t sus_timeout_cnt:7; }; @@ -655,34 +695,34 @@ typedef union { uint32_t wait_pesr_cmd_2b:1; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ uint32_t flash_hpm_dly_128:1; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ uint32_t flash_res_dly_128:1; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ uint32_t flash_dp_dly_128:1; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ uint32_t flash_per_dly_128:1; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ uint32_t flash_pes_dly_128:1; /** spi0_lock_en : R/W; bitpos: [7]; default: 0; @@ -739,8 +779,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -801,12 +841,14 @@ typedef union { struct { /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_data:32; }; uint32_t val; } spi1_mem_c_tx_crc_reg_t; + /** Group: Interrupt registers */ /** Type of int_ena register * SPI1 interrupt enable register @@ -894,19 +936,19 @@ typedef union { */ uint32_t pes_end_int_raw:1; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ uint32_t wpe_end_int_raw:1; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; uint32_t reserved_5:5; @@ -985,7 +1027,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35660128; + /** date : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h index 22df90ee72a..f8219e708e1 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h @@ -33,8 +33,9 @@ extern "C" { #define SPI1_MEM_S_SLV_ST_S 4 /** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_PE (BIT(17)) #define SPI1_MEM_S_FLASH_PE_M (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_HPM (BIT(19)) #define SPI1_MEM_S_FLASH_HPM_M (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RES (BIT(20)) #define SPI1_MEM_S_FLASH_RES_M (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_DP (BIT(21)) #define SPI1_MEM_S_FLASH_DP_M (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_CE (BIT(22)) #define SPI1_MEM_S_FLASH_CE_M (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_BE (BIT(23)) #define SPI1_MEM_S_FLASH_BE_M (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_SE (BIT(24)) #define SPI1_MEM_S_FLASH_SE_M (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_PP (BIT(25)) #define SPI1_MEM_S_FLASH_PP_M (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WRSR (BIT(26)) #define SPI1_MEM_S_FLASH_WRSR_M (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RDSR (BIT(27)) #define SPI1_MEM_S_FLASH_RDSR_M (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RDID (BIT(28)) #define SPI1_MEM_S_FLASH_RDID_M (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WRDI (BIT(29)) #define SPI1_MEM_S_FLASH_WRDI_M (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WREN (BIT(30)) #define SPI1_MEM_S_FLASH_WREN_M (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_READ (BIT(31)) #define SPI1_MEM_S_FLASH_READ_M (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_S_FCS_CRC_EN_M (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S) @@ -233,14 +248,15 @@ extern "C" { #define SPI1_MEM_S_FCS_CRC_EN_S 10 /** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_TX_CRC_EN (BIT(11)) #define SPI1_MEM_S_TX_CRC_EN_M (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S) #define SPI1_MEM_S_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_S_TX_CRC_EN_S 11 /** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout - * and spi1_mem_s_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ #define SPI1_MEM_S_FASTRD_MODE (BIT(13)) #define SPI1_MEM_S_FASTRD_MODE_M (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S) @@ -255,7 +271,8 @@ extern "C" { #define SPI1_MEM_S_FREAD_DUAL_S 14 /** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with - * spi1_mem_s_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_RESANDRES (BIT(15)) #define SPI1_MEM_S_RESANDRES_M (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_WRSR_2B (BIT(22)) #define SPI1_MEM_S_WRSR_2B_M (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S) @@ -328,13 +346,30 @@ extern "C" { #define SPI1_MEM_S_CLK_MODE_V 0x00000003U #define SPI1_MEM_S_CLK_MODE_S 0 /** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES_M (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S) #define SPI1_MEM_S_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES_S 2 +/** SPI1_MEM_S_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ +#define SPI1_MEM_S_CS_HOLD_DLY_PER 0x000001FFU +#define SPI1_MEM_S_CS_HOLD_DLY_PER_M (SPI1_MEM_S_CS_HOLD_DLY_PER_V << SPI1_MEM_S_CS_HOLD_DLY_PER_S) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_V 0x000001FFU +#define SPI1_MEM_S_CS_HOLD_DLY_PER_S 12 +/** SPI1_MEM_S_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN (BIT(23)) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V 0x00000001U +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S 23 /** SPI1_MEM_S_CTRL2_REG register * SPI1 control2 register. @@ -353,22 +388,22 @@ extern "C" { */ #define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14) /** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N. */ #define SPI1_MEM_S_CLKCNT_L 0x000000FFU #define SPI1_MEM_S_CLKCNT_L_M (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S) #define SPI1_MEM_S_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_L_S 0 /** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1). */ #define SPI1_MEM_S_CLKCNT_H 0x000000FFU #define SPI1_MEM_S_CLKCNT_H_M (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S) #define SPI1_MEM_S_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_H_S 8 /** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is - * system/(spi1_mem_s_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_S_CLKCNT_N+1) */ #define SPI1_MEM_S_CLKCNT_N 0x000000FFU #define SPI1_MEM_S_CLKCNT_N_M (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S) @@ -387,7 +422,7 @@ extern "C" { */ #define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18) /** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ #define SPI1_MEM_S_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_S_CK_OUT_EDGE_M (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S) @@ -422,7 +457,7 @@ extern "C" { #define SPI1_MEM_S_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_S_FWRITE_QIO_S 15 /** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ #define SPI1_MEM_S_USR_MISO_HIGHPART (BIT(24)) @@ -430,7 +465,7 @@ extern "C" { #define SPI1_MEM_S_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_S_USR_MISO_HIGHPART_S 24 /** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ #define SPI1_MEM_S_USR_MOSI_HIGHPART (BIT(25)) @@ -485,7 +520,7 @@ extern "C" { */ #define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c) /** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ #define SPI1_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU @@ -548,14 +583,15 @@ extern "C" { */ #define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c) /** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ #define SPI1_MEM_S_STATUS 0x0000FFFFU #define SPI1_MEM_S_STATUS_M (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S) #define SPI1_MEM_S_STATUS_V 0x0000FFFFU #define SPI1_MEM_S_STATUS_S 0 /** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_WB_MODE 0x000000FFU #define SPI1_MEM_S_WB_MODE_M (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S) @@ -611,10 +647,13 @@ extern "C" { /** SPI1_MEM_S_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c) /** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S) @@ -622,7 +661,8 @@ extern "C" { #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 /** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_s_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDIN_DUAL (BIT(3)) #define SPI1_MEM_S_FDIN_DUAL_M (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S) @@ -630,7 +670,8 @@ extern "C" { #define SPI1_MEM_S_FDIN_DUAL_S 3 /** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_S_FDOUT_DUAL_M (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S) @@ -638,7 +679,8 @@ extern "C" { #define SPI1_MEM_S_FDOUT_DUAL_S 4 /** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FADDR_DUAL (BIT(5)) #define SPI1_MEM_S_FADDR_DUAL_M (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S) @@ -646,7 +688,8 @@ extern "C" { #define SPI1_MEM_S_FADDR_DUAL_S 5 /** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDIN_QUAD (BIT(6)) #define SPI1_MEM_S_FDIN_QUAD_M (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S) @@ -654,7 +697,8 @@ extern "C" { #define SPI1_MEM_S_FDIN_QUAD_S 6 /** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_S_FDOUT_QUAD_M (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S) @@ -662,7 +706,8 @@ extern "C" { #define SPI1_MEM_S_FDOUT_QUAD_S 7 /** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FADDR_QUAD (BIT(8)) #define SPI1_MEM_S_FADDR_QUAD_M (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S) @@ -891,8 +936,8 @@ extern "C" { #define SPI1_MEM_S_WAITI_ADDR_EN_S 2 /** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_S_WAITI_ADDR_EN is cleared. */ #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S) @@ -1010,8 +1055,8 @@ extern "C" { #define SPI1_MEM_S_PES_END_EN_V 0x00000001U #define SPI1_MEM_S_PES_END_EN_S 24 /** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ #define SPI1_MEM_S_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_S_SUS_TIMEOUT_CNT_M (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S) @@ -1059,8 +1104,8 @@ extern "C" { #define SPI1_MEM_S_WAIT_PESR_CMD_2B_S 1 /** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ #define SPI1_MEM_S_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_S_FLASH_HPM_DLY_128_M (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S) @@ -1068,8 +1113,8 @@ extern "C" { #define SPI1_MEM_S_FLASH_HPM_DLY_128_S 2 /** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ #define SPI1_MEM_S_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_S_FLASH_RES_DLY_128_M (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S) @@ -1077,8 +1122,8 @@ extern "C" { #define SPI1_MEM_S_FLASH_RES_DLY_128_S 3 /** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ #define SPI1_MEM_S_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_S_FLASH_DP_DLY_128_M (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S) @@ -1086,9 +1131,9 @@ extern "C" { #define SPI1_MEM_S_FLASH_DP_DLY_128_S 4 /** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ #define SPI1_MEM_S_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_S_FLASH_PER_DLY_128_M (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S) @@ -1096,9 +1141,9 @@ extern "C" { #define SPI1_MEM_S_FLASH_PER_DLY_128_S 5 /** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ #define SPI1_MEM_S_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_S_FLASH_PES_DLY_128_M (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S) @@ -1242,16 +1287,16 @@ extern "C" { #define SPI1_MEM_S_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_PES_END_INT_RAW_S 1 /** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ #define SPI1_MEM_S_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_S_WPE_END_INT_RAW_M (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S) #define SPI1_MEM_S_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_WPE_END_INT_RAW_S 2 /** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI1_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) @@ -1259,8 +1304,8 @@ extern "C" { #define SPI1_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_SLV_ST_END_INT_RAW_S 3 /** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI1_MEM_S_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_S_MST_ST_END_INT_RAW_M (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S) @@ -1379,8 +1424,8 @@ extern "C" { #define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 /** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI1_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1468,7 +1513,7 @@ extern "C" { * Version control register */ #define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc) -/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216; +/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ #define SPI1_MEM_S_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h index 756985a0470..e36743cc8a0 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h @@ -29,8 +29,9 @@ typedef union { uint32_t reserved_8:9; /** flash_pe : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -130,7 +144,7 @@ typedef union { struct { uint32_t reserved_0:9; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; @@ -152,12 +166,12 @@ typedef union { uint32_t fwrite_qio:1; uint32_t reserved_16:8; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ uint32_t usr_mosi_highpart:1; @@ -195,7 +209,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -268,16 +282,18 @@ typedef union { /** fcs_crc_en : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout - * and spi1_mem_s_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -286,7 +302,8 @@ typedef union { uint32_t fread_dual:1; /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with - * spi1_mem_s_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +326,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +356,23 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_per:9; + uint32_t reserved_21:2; + /** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ + uint32_t cs_hold_dly_per_en:1; + uint32_t reserved_24:8; }; uint32_t val; } spi1_mem_s_ctrl1_reg_t; @@ -367,16 +397,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is - * system/(spi1_mem_s_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_S_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -422,11 +452,12 @@ typedef union { typedef union { struct { /** status : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; uint32_t reserved_24:8; @@ -471,37 +502,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_s_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -531,8 +569,8 @@ typedef union { uint32_t waiti_addr_en:1; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_S_WAITI_ADDR_EN is cleared. */ uint32_t waiti_addr_cyclelen:2; uint32_t reserved_5:4; @@ -613,8 +651,8 @@ typedef union { */ uint32_t pes_end_en:1; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ uint32_t sus_timeout_cnt:7; }; @@ -655,34 +693,34 @@ typedef union { uint32_t wait_pesr_cmd_2b:1; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ uint32_t flash_hpm_dly_128:1; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ uint32_t flash_res_dly_128:1; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ uint32_t flash_dp_dly_128:1; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ uint32_t flash_per_dly_128:1; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ uint32_t flash_pes_dly_128:1; /** spi0_lock_en : R/W; bitpos: [7]; default: 0; @@ -739,8 +777,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -1105,19 +1143,19 @@ typedef union { */ uint32_t pes_end_int_raw:1; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ uint32_t wpe_end_int_raw:1; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; uint32_t reserved_5:5; @@ -1196,7 +1234,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 34673216; + /** date : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h index d105863da38..14dcc8ec501 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h @@ -34,9 +34,9 @@ extern "C" { #define SPI_MEM_C_SLV_ST_V 0x0000000FU #define SPI_MEM_C_SLV_ST_S 4 /** SPI_MEM_C_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ #define SPI_MEM_C_USR (BIT(18)) #define SPI_MEM_C_USR_M (SPI_MEM_C_USR_V << SPI_MEM_C_USR_S) @@ -117,8 +117,8 @@ extern "C" { #define SPI_MEM_C_FCMD_OCT_V 0x00000001U #define SPI_MEM_C_FCMD_OCT_S 9 /** SPI_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, SPI_MEM_C_FREAD_QOUT - * and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, + * SPI_MEM_C_FREAD_QOUT and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. */ #define SPI_MEM_C_FASTRD_MODE (BIT(13)) #define SPI_MEM_C_FASTRD_MODE_M (SPI_MEM_C_FASTRD_MODE_V << SPI_MEM_C_FASTRD_MODE_S) @@ -220,14 +220,6 @@ extern "C" { #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_MEM_C_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_MEM_C_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_M (SPI_MEM_C_AXI_RDATA_BACK_FAST_V << SPI_MEM_C_AXI_RDATA_BACK_FAST_S) -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_S 23 /** SPI_MEM_C_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -316,8 +308,8 @@ extern "C" { #define SPI_MEM_C_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_C_CS_HOLD_TIME_S 5 /** SPI_MEM_C_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; - * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ #define SPI_MEM_C_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_C_ECC_CS_HOLD_TIME_M (SPI_MEM_C_ECC_CS_HOLD_TIME_V << SPI_MEM_C_ECC_CS_HOLD_TIME_S) @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI0_BASE + 0x14) /** SPI_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_C_CLKCNT_N. */ #define SPI_MEM_C_CLKCNT_L 0x000000FFU #define SPI_MEM_C_CLKCNT_L_M (SPI_MEM_C_CLKCNT_L_V << SPI_MEM_C_CLKCNT_L_S) #define SPI_MEM_C_CLKCNT_L_V 0x000000FFU #define SPI_MEM_C_CLKCNT_L_S 0 /** SPI_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_C_CLKCNT_N+1)/2-1). */ #define SPI_MEM_C_CLKCNT_H 0x000000FFU #define SPI_MEM_C_CLKCNT_H_M (SPI_MEM_C_CLKCNT_H_V << SPI_MEM_C_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_C_CLKCNT_H_S 8 /** SPI_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_C_CLKCNT_N+1) */ #define SPI_MEM_C_CLKCNT_N 0x000000FFU #define SPI_MEM_C_CLKCNT_N_M (SPI_MEM_C_CLKCNT_N_V << SPI_MEM_C_CLKCNT_N_S) @@ -486,10 +478,46 @@ extern "C" { #define SPI_MEM_C_USR_COMMAND_BITLEN_V 0x0000000FU #define SPI_MEM_C_USR_COMMAND_BITLEN_S 28 +/** SPI_MEM_C_RD_STATUS_REG register + * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI0_BASE + 0x2c) +/** SPI_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_WB_MODE 0x000000FFU +#define SPI_MEM_C_WB_MODE_M (SPI_MEM_C_WB_MODE_V << SPI_MEM_C_WB_MODE_S) +#define SPI_MEM_C_WB_MODE_V 0x000000FFU +#define SPI_MEM_C_WB_MODE_S 16 + /** SPI_MEM_C_MISC_REG register * SPI0 misc register */ #define SPI_MEM_C_MISC_REG (DR_REG_FLASH_SPI0_BASE + 0x34) +/** SPI_MEM_C_DQ_OE_CTRL : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_DQ_OE_CTRL (BIT(4)) +#define SPI_MEM_C_DQ_OE_CTRL_M (SPI_MEM_C_DQ_OE_CTRL_V << SPI_MEM_C_DQ_OE_CTRL_S) +#define SPI_MEM_C_DQ_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_DQ_OE_CTRL_S 4 +/** SPI_MEM_C_CK_OE_CTRL : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_CK_OE_CTRL (BIT(5)) +#define SPI_MEM_C_CK_OE_CTRL_M (SPI_MEM_C_CK_OE_CTRL_V << SPI_MEM_C_CK_OE_CTRL_S) +#define SPI_MEM_C_CK_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_CK_OE_CTRL_S 5 +/** SPI_MEM_C_CS_OE_CTRL : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_CS_OE_CTRL (BIT(6)) +#define SPI_MEM_C_CS_OE_CTRL_M (SPI_MEM_C_CS_OE_CTRL_V << SPI_MEM_C_CS_OE_CTRL_S) +#define SPI_MEM_C_CS_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_CS_OE_CTRL_S 6 /** SPI_MEM_C_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -523,11 +551,129 @@ extern "C" { * SPI0 bit mode control register. */ #define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c) +/** SPI_MEM_C_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_C_AXI_REQ_EN_M (SPI_MEM_C_AXI_REQ_EN_V << SPI_MEM_C_AXI_REQ_EN_S) +#define SPI_MEM_C_AXI_REQ_EN_V 0x00000001U +#define SPI_MEM_C_AXI_REQ_EN_S 0 +/** SPI_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_C_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_C_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_M (SPI_MEM_C_CACHE_FLASH_USR_CMD_V << SPI_MEM_C_CACHE_FLASH_USR_CMD_S) +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_V 0x00000001U +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_S 2 +/** SPI_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDIN_DUAL (BIT(3)) +#define SPI_MEM_C_FDIN_DUAL_M (SPI_MEM_C_FDIN_DUAL_V << SPI_MEM_C_FDIN_DUAL_S) +#define SPI_MEM_C_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_C_FDIN_DUAL_S 3 +/** SPI_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_C_FDOUT_DUAL_M (SPI_MEM_C_FDOUT_DUAL_V << SPI_MEM_C_FDOUT_DUAL_S) +#define SPI_MEM_C_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_C_FDOUT_DUAL_S 4 +/** SPI_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FADDR_DUAL (BIT(5)) +#define SPI_MEM_C_FADDR_DUAL_M (SPI_MEM_C_FADDR_DUAL_V << SPI_MEM_C_FADDR_DUAL_S) +#define SPI_MEM_C_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_C_FADDR_DUAL_S 5 +/** SPI_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDIN_QUAD (BIT(6)) +#define SPI_MEM_C_FDIN_QUAD_M (SPI_MEM_C_FDIN_QUAD_V << SPI_MEM_C_FDIN_QUAD_S) +#define SPI_MEM_C_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_C_FDIN_QUAD_S 6 +/** SPI_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_C_FDOUT_QUAD_M (SPI_MEM_C_FDOUT_QUAD_V << SPI_MEM_C_FDOUT_QUAD_S) +#define SPI_MEM_C_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_C_FDOUT_QUAD_S 7 +/** SPI_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FADDR_QUAD (BIT(8)) +#define SPI_MEM_C_FADDR_QUAD_M (SPI_MEM_C_FADDR_QUAD_V << SPI_MEM_C_FADDR_QUAD_S) +#define SPI_MEM_C_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_C_FADDR_QUAD_S 8 +/** SPI_MEM_C_ARB_WEI_EN : HRO; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ +#define SPI_MEM_C_ARB_WEI_EN (BIT(9)) +#define SPI_MEM_C_ARB_WEI_EN_M (SPI_MEM_C_ARB_WEI_EN_V << SPI_MEM_C_ARB_WEI_EN_S) +#define SPI_MEM_C_ARB_WEI_EN_V 0x00000001U +#define SPI_MEM_C_ARB_WEI_EN_S 9 +/** SPI_MEM_C_ARB_REQ0_PRI : HRO; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_C_ARB_REQ0_PRI (BIT(10)) +#define SPI_MEM_C_ARB_REQ0_PRI_M (SPI_MEM_C_ARB_REQ0_PRI_V << SPI_MEM_C_ARB_REQ0_PRI_S) +#define SPI_MEM_C_ARB_REQ0_PRI_V 0x00000001U +#define SPI_MEM_C_ARB_REQ0_PRI_S 10 +/** SPI_MEM_C_ARB_REQ1_PRI : HRO; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_C_ARB_REQ1_PRI (BIT(11)) +#define SPI_MEM_C_ARB_REQ1_PRI_M (SPI_MEM_C_ARB_REQ1_PRI_V << SPI_MEM_C_ARB_REQ1_PRI_S) +#define SPI_MEM_C_ARB_REQ1_PRI_V 0x00000001U +#define SPI_MEM_C_ARB_REQ1_PRI_S 11 +/** SPI_MEM_C_ARB_REQ0_WEI : HRO; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_C_ARB_REQ0_WEI 0x0000000FU +#define SPI_MEM_C_ARB_REQ0_WEI_M (SPI_MEM_C_ARB_REQ0_WEI_V << SPI_MEM_C_ARB_REQ0_WEI_S) +#define SPI_MEM_C_ARB_REQ0_WEI_V 0x0000000FU +#define SPI_MEM_C_ARB_REQ0_WEI_S 12 +/** SPI_MEM_C_ARB_REQ1_WEI : HRO; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_C_ARB_REQ1_WEI 0x0000000FU +#define SPI_MEM_C_ARB_REQ1_WEI_M (SPI_MEM_C_ARB_REQ1_WEI_V << SPI_MEM_C_ARB_REQ1_WEI_S) +#define SPI_MEM_C_ARB_REQ1_WEI_V 0x0000000FU +#define SPI_MEM_C_ARB_REQ1_WEI_S 16 /** SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M (SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V << SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S) #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S 30 /** SPI_MEM_C_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; @@ -535,14 +681,247 @@ extern "C" { * SLV_ERR will be replied to BRESP/RRESP. */ #define SPI_MEM_C_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_MEM_C_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_MEM_C_CLOSE_AXI_INF_EN_M (SPI_MEM_C_CLOSE_AXI_INF_EN_V << SPI_MEM_C_CLOSE_AXI_INF_EN_S) #define SPI_MEM_C_CLOSE_AXI_INF_EN_V 0x00000001U #define SPI_MEM_C_CLOSE_AXI_INF_EN_S 31 +/** SPI_MEM_C_CACHE_SCTRL_REG register + * SPI0 external RAM control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_CACHE_SCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x40) +/** SPI_MEM_C_CACHE_USR_SADDR_4BYTE : HRO; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_C_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_C_CACHE_USR_SADDR_4BYTE_S) +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_V 0x00000001U +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_S 0 +/** SPI_MEM_C_USR_SRAM_DIO : HRO; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_C_USR_SRAM_DIO_M (SPI_MEM_C_USR_SRAM_DIO_V << SPI_MEM_C_USR_SRAM_DIO_S) +#define SPI_MEM_C_USR_SRAM_DIO_V 0x00000001U +#define SPI_MEM_C_USR_SRAM_DIO_S 1 +/** SPI_MEM_C_USR_SRAM_QIO : HRO; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_C_USR_SRAM_QIO_M (SPI_MEM_C_USR_SRAM_QIO_V << SPI_MEM_C_USR_SRAM_QIO_S) +#define SPI_MEM_C_USR_SRAM_QIO_V 0x00000001U +#define SPI_MEM_C_USR_SRAM_QIO_S 2 +/** SPI_MEM_C_USR_WR_SRAM_DUMMY : HRO; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_M (SPI_MEM_C_USR_WR_SRAM_DUMMY_V << SPI_MEM_C_USR_WR_SRAM_DUMMY_S) +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_S 3 +/** SPI_MEM_C_USR_RD_SRAM_DUMMY : HRO; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_M (SPI_MEM_C_USR_RD_SRAM_DUMMY_V << SPI_MEM_C_USR_RD_SRAM_DUMMY_S) +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_S 4 +/** SPI_MEM_C_CACHE_SRAM_USR_RCMD : HRO; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_M (SPI_MEM_C_CACHE_SRAM_USR_RCMD_V << SPI_MEM_C_CACHE_SRAM_USR_RCMD_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_V 0x00000001U +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_S 5 +/** SPI_MEM_C_SRAM_RDUMMY_CYCLELEN : HRO; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_S) +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_S 6 +/** SPI_MEM_C_SRAM_ADDR_BITLEN : HRO; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_C_SRAM_ADDR_BITLEN_M (SPI_MEM_C_SRAM_ADDR_BITLEN_V << SPI_MEM_C_SRAM_ADDR_BITLEN_S) +#define SPI_MEM_C_SRAM_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_ADDR_BITLEN_S 14 +/** SPI_MEM_C_CACHE_SRAM_USR_WCMD : HRO; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_M (SPI_MEM_C_CACHE_SRAM_USR_WCMD_V << SPI_MEM_C_CACHE_SRAM_USR_WCMD_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_V 0x00000001U +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_S 20 +/** SPI_MEM_C_SRAM_OCT : HRO; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_OCT (BIT(21)) +#define SPI_MEM_C_SRAM_OCT_M (SPI_MEM_C_SRAM_OCT_V << SPI_MEM_C_SRAM_OCT_S) +#define SPI_MEM_C_SRAM_OCT_V 0x00000001U +#define SPI_MEM_C_SRAM_OCT_S 21 +/** SPI_MEM_C_SRAM_WDUMMY_CYCLELEN : HRO; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_S) +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_S 22 + /** SPI_MEM_C_SRAM_CMD_REG register * SPI0 external RAM mode control register */ #define SPI_MEM_C_SRAM_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x44) +/** SPI_MEM_C_SCLK_MODE : HRO; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLK_MODE 0x00000003U +#define SPI_MEM_C_SCLK_MODE_M (SPI_MEM_C_SCLK_MODE_V << SPI_MEM_C_SCLK_MODE_S) +#define SPI_MEM_C_SCLK_MODE_V 0x00000003U +#define SPI_MEM_C_SCLK_MODE_S 0 +/** SPI_MEM_C_SWB_MODE : HRO; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SWB_MODE 0x000000FFU +#define SPI_MEM_C_SWB_MODE_M (SPI_MEM_C_SWB_MODE_V << SPI_MEM_C_SWB_MODE_S) +#define SPI_MEM_C_SWB_MODE_V 0x000000FFU +#define SPI_MEM_C_SWB_MODE_S 2 +/** SPI_MEM_C_SDIN_DUAL : HRO; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_DUAL (BIT(10)) +#define SPI_MEM_C_SDIN_DUAL_M (SPI_MEM_C_SDIN_DUAL_V << SPI_MEM_C_SDIN_DUAL_S) +#define SPI_MEM_C_SDIN_DUAL_V 0x00000001U +#define SPI_MEM_C_SDIN_DUAL_S 10 +/** SPI_MEM_C_SDOUT_DUAL : HRO; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_C_SDOUT_DUAL_M (SPI_MEM_C_SDOUT_DUAL_V << SPI_MEM_C_SDOUT_DUAL_S) +#define SPI_MEM_C_SDOUT_DUAL_V 0x00000001U +#define SPI_MEM_C_SDOUT_DUAL_S 11 +/** SPI_MEM_C_SADDR_DUAL : HRO; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_DUAL (BIT(12)) +#define SPI_MEM_C_SADDR_DUAL_M (SPI_MEM_C_SADDR_DUAL_V << SPI_MEM_C_SADDR_DUAL_S) +#define SPI_MEM_C_SADDR_DUAL_V 0x00000001U +#define SPI_MEM_C_SADDR_DUAL_S 12 +/** SPI_MEM_C_SDIN_QUAD : HRO; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_QUAD (BIT(14)) +#define SPI_MEM_C_SDIN_QUAD_M (SPI_MEM_C_SDIN_QUAD_V << SPI_MEM_C_SDIN_QUAD_S) +#define SPI_MEM_C_SDIN_QUAD_V 0x00000001U +#define SPI_MEM_C_SDIN_QUAD_S 14 +/** SPI_MEM_C_SDOUT_QUAD : HRO; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_C_SDOUT_QUAD_M (SPI_MEM_C_SDOUT_QUAD_V << SPI_MEM_C_SDOUT_QUAD_S) +#define SPI_MEM_C_SDOUT_QUAD_V 0x00000001U +#define SPI_MEM_C_SDOUT_QUAD_S 15 +/** SPI_MEM_C_SADDR_QUAD : HRO; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_QUAD (BIT(16)) +#define SPI_MEM_C_SADDR_QUAD_M (SPI_MEM_C_SADDR_QUAD_V << SPI_MEM_C_SADDR_QUAD_S) +#define SPI_MEM_C_SADDR_QUAD_V 0x00000001U +#define SPI_MEM_C_SADDR_QUAD_S 16 +/** SPI_MEM_C_SCMD_QUAD : HRO; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCMD_QUAD (BIT(17)) +#define SPI_MEM_C_SCMD_QUAD_M (SPI_MEM_C_SCMD_QUAD_V << SPI_MEM_C_SCMD_QUAD_S) +#define SPI_MEM_C_SCMD_QUAD_V 0x00000001U +#define SPI_MEM_C_SCMD_QUAD_S 17 +/** SPI_MEM_C_SDIN_OCT : HRO; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_OCT (BIT(18)) +#define SPI_MEM_C_SDIN_OCT_M (SPI_MEM_C_SDIN_OCT_V << SPI_MEM_C_SDIN_OCT_S) +#define SPI_MEM_C_SDIN_OCT_V 0x00000001U +#define SPI_MEM_C_SDIN_OCT_S 18 +/** SPI_MEM_C_SDOUT_OCT : HRO; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_OCT (BIT(19)) +#define SPI_MEM_C_SDOUT_OCT_M (SPI_MEM_C_SDOUT_OCT_V << SPI_MEM_C_SDOUT_OCT_S) +#define SPI_MEM_C_SDOUT_OCT_V 0x00000001U +#define SPI_MEM_C_SDOUT_OCT_S 19 +/** SPI_MEM_C_SADDR_OCT : HRO; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_OCT (BIT(20)) +#define SPI_MEM_C_SADDR_OCT_M (SPI_MEM_C_SADDR_OCT_V << SPI_MEM_C_SADDR_OCT_S) +#define SPI_MEM_C_SADDR_OCT_V 0x00000001U +#define SPI_MEM_C_SADDR_OCT_S 20 +/** SPI_MEM_C_SCMD_OCT : HRO; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCMD_OCT (BIT(21)) +#define SPI_MEM_C_SCMD_OCT_M (SPI_MEM_C_SCMD_OCT_V << SPI_MEM_C_SCMD_OCT_S) +#define SPI_MEM_C_SCMD_OCT_V 0x00000001U +#define SPI_MEM_C_SCMD_OCT_S 21 +/** SPI_MEM_C_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_C_SDUMMY_RIN_M (SPI_MEM_C_SDUMMY_RIN_V << SPI_MEM_C_SDUMMY_RIN_S) +#define SPI_MEM_C_SDUMMY_RIN_V 0x00000001U +#define SPI_MEM_C_SDUMMY_RIN_S 22 +/** SPI_MEM_C_SDUMMY_WOUT : HRO; bitpos: [23]; default: 0; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_C_SDUMMY_WOUT_M (SPI_MEM_C_SDUMMY_WOUT_V << SPI_MEM_C_SDUMMY_WOUT_S) +#define SPI_MEM_C_SDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_C_SDUMMY_WOUT_S 23 /** SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -576,16 +955,107 @@ extern "C" { #define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U #define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S 31 +/** SPI_MEM_C_SRAM_DRD_CMD_REG register + * SPI0 external RAM DDR read command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_DRD_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x48) +/** SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/** SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/** SPI_MEM_C_SRAM_DWR_CMD_REG register + * SPI0 external RAM DDR write command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_DWR_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x4c) +/** SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/** SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/** SPI_MEM_C_SRAM_CLK_REG register + * SPI0 external RAM clock control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_CLK_REG (DR_REG_FLASH_SPI0_BASE + 0x50) +/** SPI_MEM_C_SCLKCNT_L : HRO; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_C_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_L 0x000000FFU +#define SPI_MEM_C_SCLKCNT_L_M (SPI_MEM_C_SCLKCNT_L_V << SPI_MEM_C_SCLKCNT_L_S) +#define SPI_MEM_C_SCLKCNT_L_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_L_S 0 +/** SPI_MEM_C_SCLKCNT_H : HRO; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_C_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_H 0x000000FFU +#define SPI_MEM_C_SCLKCNT_H_M (SPI_MEM_C_SCLKCNT_H_V << SPI_MEM_C_SCLKCNT_H_S) +#define SPI_MEM_C_SCLKCNT_H_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_H_S 8 +/** SPI_MEM_C_SCLKCNT_N : HRO; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_C_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_N 0x000000FFU +#define SPI_MEM_C_SCLKCNT_N_M (SPI_MEM_C_SCLKCNT_N_V << SPI_MEM_C_SCLKCNT_N_S) +#define SPI_MEM_C_SCLKCNT_N_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_N_S 16 +/** SPI_MEM_C_SCLK_EQU_SYSCLK : HRO; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_C_SCLK_EQU_SYSCLK_M (SPI_MEM_C_SCLK_EQU_SYSCLK_V << SPI_MEM_C_SCLK_EQU_SYSCLK_S) +#define SPI_MEM_C_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_C_SCLK_EQU_SYSCLK_S 31 + /** SPI_MEM_C_FSM_REG register * SPI0 FSM status register */ #define SPI_MEM_C_FSM_REG (DR_REG_FLASH_SPI0_BASE + 0x54) -/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_C_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_C_LOCK_DELAY_TIME_M (SPI_MEM_C_LOCK_DELAY_TIME_V << SPI_MEM_C_LOCK_DELAY_TIME_S) -#define SPI_MEM_C_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_C_LOCK_DELAY_TIME_S 7 /** SPI_MEM_C_INT_ENA_REG register @@ -641,6 +1111,20 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_ENA : HRO; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_M (SPI_MEM_C_RX_TRANS_OVF_INT_ENA_V << SPI_MEM_C_RX_TRANS_OVF_INT_ENA_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_ENA : HRO; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_M (SPI_MEM_C_TX_TRANS_UDF_INT_ENA_V << SPI_MEM_C_TX_TRANS_UDF_INT_ENA_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_S 27 /** SPI_MEM_C_INT_CLR_REG register * SPI0 interrupt clear register @@ -695,14 +1179,28 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_CLR : HRO; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_M (SPI_MEM_C_RX_TRANS_OVF_INT_CLR_V << SPI_MEM_C_RX_TRANS_OVF_INT_CLR_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_CLR : HRO; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_M (SPI_MEM_C_TX_TRANS_UDF_INT_CLR_V << SPI_MEM_C_TX_TRANS_UDF_INT_CLR_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_S 27 /** SPI_MEM_C_INT_RAW_REG register * SPI0 interrupt raw register */ #define SPI_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI0_BASE + 0xc8) /** SPI_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) @@ -710,32 +1208,33 @@ extern "C" { #define SPI_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_C_SLV_ST_END_INT_RAW_S 3 /** SPI_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI_MEM_C_MST_ST_END_INT_RAW (BIT(4)) #define SPI_MEM_C_MST_ST_END_INT_RAW_M (SPI_MEM_C_MST_ST_END_INT_RAW_V << SPI_MEM_C_MST_ST_END_INT_RAW_S) #define SPI_MEM_C_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_C_MST_ST_END_INT_RAW_S 4 /** SPI_MEM_C_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set - * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When - * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and - * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When + * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is + * cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are + * equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN + * is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when + * the error times of SPI0/1 ECC read external RAM are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error + * times of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. */ #define SPI_MEM_C_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_C_ECC_ERR_INT_RAW_M (SPI_MEM_C_ECC_ERR_INT_RAW_V << SPI_MEM_C_ECC_ERR_INT_RAW_S) #define SPI_MEM_C_ECC_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_ECC_ERR_INT_RAW_S 5 /** SPI_MEM_C_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ #define SPI_MEM_C_PMS_REJECT_INT_RAW (BIT(6)) #define SPI_MEM_C_PMS_REJECT_INT_RAW_M (SPI_MEM_C_PMS_REJECT_INT_RAW_V << SPI_MEM_C_PMS_REJECT_INT_RAW_S) @@ -750,8 +1249,8 @@ extern "C" { #define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S 7 /** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ #define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) #define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S) @@ -765,6 +1264,22 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_M (SPI_MEM_C_RX_TRANS_OVF_INT_RAW_V << SPI_MEM_C_RX_TRANS_OVF_INT_RAW_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_M (SPI_MEM_C_TX_TRANS_UDF_INT_RAW_V << SPI_MEM_C_TX_TRANS_UDF_INT_RAW_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_S 27 /** SPI_MEM_C_INT_ST_REG register * SPI0 interrupt status register @@ -819,6 +1334,20 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_ST : HRO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_M (SPI_MEM_C_RX_TRANS_OVF_INT_ST_V << SPI_MEM_C_RX_TRANS_OVF_INT_ST_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_ST : HRO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_M (SPI_MEM_C_TX_TRANS_UDF_INT_ST_V << SPI_MEM_C_TX_TRANS_UDF_INT_ST_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_S 27 /** SPI_MEM_C_DDR_REG register * SPI0 flash DDR mode control register @@ -891,8 +1420,8 @@ extern "C" { #define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S 14 /** SPI_MEM_C_FMEM__DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_C_FMEM__DDR_DQS_LOOP (BIT(21)) @@ -1016,8 +1545,8 @@ extern "C" { #define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_C_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_C_SMEM_DDR_DQS_LOOP (BIT(21)) @@ -1071,8 +1600,70 @@ extern "C" { #define SPI_MEM_C_SMEM_HYPERBUS_CA_V 0x00000001U #define SPI_MEM_C_SMEM_HYPERBUS_CA_S 30 +/** SPI_MEM_C_DLL_DLY_DB_REG register + * MSPI DLL function and debug configuration register + */ +#define SPI_MEM_C_DLL_DLY_DB_REG (DR_REG_FLASH_SPI0_BASE + 0xdc) +/** SPI_MEM_C_DLL_DB_CFG_VLD_CNT : HRO; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT 0x000000FFU +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_M (SPI_MEM_C_DLL_DB_CFG_VLD_CNT_V << SPI_MEM_C_DLL_DB_CFG_VLD_CNT_S) +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_V 0x000000FFU +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_S 0 +/** SPI_MEM_C_DLL_DB_CNT_MODE_SEL : HRO; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL 0x0000000FU +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_M (SPI_MEM_C_DLL_DB_CNT_MODE_SEL_V << SPI_MEM_C_DLL_DB_CNT_MODE_SEL_S) +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_V 0x0000000FU +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_S 8 +/** SPI_MEM_C_DLL_DB_CNT_CLR : HRO; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ +#define SPI_MEM_C_DLL_DB_CNT_CLR (BIT(12)) +#define SPI_MEM_C_DLL_DB_CNT_CLR_M (SPI_MEM_C_DLL_DB_CNT_CLR_V << SPI_MEM_C_DLL_DB_CNT_CLR_S) +#define SPI_MEM_C_DLL_DB_CNT_CLR_V 0x00000001U +#define SPI_MEM_C_DLL_DB_CNT_CLR_S 12 +/** SPI_MEM_C_DLL_DIN_DLY_SEL : HRO; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ +#define SPI_MEM_C_DLL_DIN_DLY_SEL (BIT(13)) +#define SPI_MEM_C_DLL_DIN_DLY_SEL_M (SPI_MEM_C_DLL_DIN_DLY_SEL_V << SPI_MEM_C_DLL_DIN_DLY_SEL_S) +#define SPI_MEM_C_DLL_DIN_DLY_SEL_V 0x00000001U +#define SPI_MEM_C_DLL_DIN_DLY_SEL_S 13 + +/** SPI_MEM_C_DLL_DB_ST0_REG register + * MSPI DLL debug status0 register + */ +#define SPI_MEM_C_DLL_DB_ST0_REG (DR_REG_FLASH_SPI0_BASE + 0xe0) +/** SPI_MEM_C_DB_FIFO_CNT_H : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ +#define SPI_MEM_C_DB_FIFO_CNT_H 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_H_M (SPI_MEM_C_DB_FIFO_CNT_H_V << SPI_MEM_C_DB_FIFO_CNT_H_S) +#define SPI_MEM_C_DB_FIFO_CNT_H_V 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_H_S 0 + +/** SPI_MEM_C_DLL_DB_ST1_REG register + * MSPI DLL debug status1 register + */ +#define SPI_MEM_C_DLL_DB_ST1_REG (DR_REG_FLASH_SPI0_BASE + 0xe4) +/** SPI_MEM_C_DB_FIFO_CNT_L : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ +#define SPI_MEM_C_DB_FIFO_CNT_L 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_L_M (SPI_MEM_C_DB_FIFO_CNT_L_V << SPI_MEM_C_DB_FIFO_CNT_L_S) +#define SPI_MEM_C_DB_FIFO_CNT_L_V 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_L_S 0 + /** SPI_MEM_C_FMEM__PMS0_ATTR_REG register - * MSPI flash PMS section 0 attribute register + * SPI1 flash PMS section 0 attribute register */ #define SPI_MEM_C_FMEM__PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x100) /** SPI_MEM_C_FMEM__PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1098,9 +1689,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS0_ECC_M (SPI_MEM_C_FMEM__PMS0_ECC_V << SPI_MEM_C_FMEM__PMS0_ECC_S) #define SPI_MEM_C_FMEM__PMS0_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS0_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers SPI_MEM_C_FMEM__PMS0_ADDR_REG + * and SPI_MEM_C_FMEM__PMS0_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS1_ATTR_REG register - * MSPI flash PMS section 1 attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_MEM_C_FMEM__PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x104) /** SPI_MEM_C_FMEM__PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1126,9 +1740,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS1_ECC_M (SPI_MEM_C_FMEM__PMS1_ECC_V << SPI_MEM_C_FMEM__PMS1_ECC_S) #define SPI_MEM_C_FMEM__PMS1_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS1_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 1 is configured by registers SPI_MEM_C_FMEM__PMS1_ADDR_REG + * and SPI_MEM_C_FMEM__PMS1_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS2_ATTR_REG register - * MSPI flash PMS section 2 attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_MEM_C_FMEM__PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x108) /** SPI_MEM_C_FMEM__PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1154,9 +1791,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS2_ECC_M (SPI_MEM_C_FMEM__PMS2_ECC_V << SPI_MEM_C_FMEM__PMS2_ECC_S) #define SPI_MEM_C_FMEM__PMS2_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS2_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 2 is configured by registers SPI_MEM_C_FMEM__PMS2_ADDR_REG + * and SPI_MEM_C_FMEM__PMS2_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS3_ATTR_REG register - * MSPI flash PMS section 3 attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_MEM_C_FMEM__PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x10c) /** SPI_MEM_C_FMEM__PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1182,6 +1842,29 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS3_ECC_M (SPI_MEM_C_FMEM__PMS3_ECC_V << SPI_MEM_C_FMEM__PMS3_ECC_S) #define SPI_MEM_C_FMEM__PMS3_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS3_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 3 is configured by registers SPI_MEM_C_FMEM__PMS3_ADDR_REG + * and SPI_MEM_C_FMEM__PMS3_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register @@ -1284,7 +1967,7 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS3_SIZE_S 0 /** SPI_MEM_C_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_MEM_C_SMEM_PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x130) /** SPI_MEM_C_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1303,16 +1986,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG and - * SPI_MEM_C_SMEM_PMS0_SIZE_REG. + * external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG + * and SPI_MEM_C_SMEM_PMS0_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS0_ECC_M (SPI_MEM_C_SMEM_PMS0_ECC_V << SPI_MEM_C_SMEM_PMS0_ECC_S) #define SPI_MEM_C_SMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS0_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 0 is configured by registers + * SPI_MEM_C_SMEM_PMS0_ADDR_REG and SPI_MEM_C_SMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 start address register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_MEM_C_SMEM_PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x134) /** SPI_MEM_C_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1331,16 +2037,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG and - * SPI_MEM_C_SMEM_PMS1_SIZE_REG. + * external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG + * and SPI_MEM_C_SMEM_PMS1_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS1_ECC_M (SPI_MEM_C_SMEM_PMS1_ECC_V << SPI_MEM_C_SMEM_PMS1_ECC_S) #define SPI_MEM_C_SMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS1_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 1 is configured by registers + * SPI_MEM_C_SMEM_PMS1_ADDR_REG and SPI_MEM_C_SMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 start address register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_MEM_C_SMEM_PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x138) /** SPI_MEM_C_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1359,16 +2088,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG and - * SPI_MEM_C_SMEM_PMS2_SIZE_REG. + * external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG + * and SPI_MEM_C_SMEM_PMS2_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS2_ECC_M (SPI_MEM_C_SMEM_PMS2_ECC_V << SPI_MEM_C_SMEM_PMS2_ECC_S) #define SPI_MEM_C_SMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS2_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 2 is configured by registers + * SPI_MEM_C_SMEM_PMS2_ADDR_REG and SPI_MEM_C_SMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 start address register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_MEM_C_SMEM_PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x13c) /** SPI_MEM_C_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1387,13 +2139,36 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG and - * SPI_MEM_C_SMEM_PMS3_SIZE_REG. + * external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG + * and SPI_MEM_C_SMEM_PMS3_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS3_ECC_M (SPI_MEM_C_SMEM_PMS3_ECC_V << SPI_MEM_C_SMEM_PMS3_ECC_S) #define SPI_MEM_C_SMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS3_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 3 is configured by registers + * SPI_MEM_C_SMEM_PMS3_ADDR_REG and SPI_MEM_C_SMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register @@ -1560,7 +2335,8 @@ extern "C" { #define SPI_MEM_C_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_C_ECC_ERR_CNT_S 5 /** SPI_MEM_C_FMEM__ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT + * interrupt. */ #define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM 0x0000003FU #define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_M (SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V << SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S) @@ -2447,8 +3223,8 @@ extern "C" { #define SPI_MEM_C_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_C_SMEM_CS_HOLD_TIME_S 7 /** SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; - * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ #define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S) @@ -2472,8 +3248,8 @@ extern "C" { #define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S 16 /** SPI_MEM_C_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ #define SPI_MEM_C_SMEM_CS_HOLD_DELAY 0x0000003FU #define SPI_MEM_C_SMEM_CS_HOLD_DELAY_M (SPI_MEM_C_SMEM_CS_HOLD_DELAY_V << SPI_MEM_C_SMEM_CS_HOLD_DELAY_S) @@ -2493,13 +3269,13 @@ extern "C" { * SPI0 clock gate register */ #define SPI_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI0_BASE + 0x200) -/** SPI_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1; +/** SPI_MEM_C_CLK : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ -#define SPI_MEM_C_CLK_EN (BIT(0)) -#define SPI_MEM_C_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_MEM_C_CLK_EN_V 0x00000001U -#define SPI_MEM_C_CLK_EN_S 0 +#define SPI_MEM_C_CLK (BIT(0)) +#define SPI_MEM_C_CLK_M (SPI_MEM_C_CLK_V << SPI_MEM_C_CLK_S) +#define SPI_MEM_C_CLK_V 0x00000001U +#define SPI_MEM_C_CLK_S 0 /** SPI_MEM_C_XTS_PLAIN_BASE_REG register * The base address of the memory that stores plaintext in Manual Encryption @@ -2510,7 +3286,7 @@ extern "C" { * Please do not use this field. */ #define SPI_MEM_C_XTS_PLAIN 0xFFFFFFFFU -#define SPI_MEM_C_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_MEM_C_XTS_PLAIN_M (SPI_MEM_C_XTS_PLAIN_V << SPI_MEM_C_XTS_PLAIN_S) #define SPI_MEM_C_XTS_PLAIN_V 0xFFFFFFFFU #define SPI_MEM_C_XTS_PLAIN_S 0 @@ -2524,7 +3300,7 @@ extern "C" { * 32-bytes, 2: 64-bytes, 3:reserved. */ #define SPI_MEM_C_XTS_LINESIZE 0x00000003U -#define SPI_MEM_C_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_MEM_C_XTS_LINESIZE_M (SPI_MEM_C_XTS_LINESIZE_V << SPI_MEM_C_XTS_LINESIZE_S) #define SPI_MEM_C_XTS_LINESIZE_V 0x00000003U #define SPI_MEM_C_XTS_LINESIZE_S 0 @@ -2537,7 +3313,7 @@ extern "C" { * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. */ #define SPI_MEM_C_XTS_DESTINATION (BIT(0)) -#define SPI_MEM_C_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_MEM_C_XTS_DESTINATION_M (SPI_MEM_C_XTS_DESTINATION_V << SPI_MEM_C_XTS_DESTINATION_S) #define SPI_MEM_C_XTS_DESTINATION_V 0x00000001U #define SPI_MEM_C_XTS_DESTINATION_S 0 @@ -2545,21 +3321,21 @@ extern "C" { * Manual Encryption physical address register */ #define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG (DR_REG_FLASH_SPI0_BASE + 0x348) -/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; +/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M (SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S) +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU #define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S 0 /** SPI_MEM_C_XTS_TRIGGER_REG register * Manual Encryption physical address register */ #define SPI_MEM_C_XTS_TRIGGER_REG (DR_REG_FLASH_SPI0_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; +/** SPI_MEM_C_XTS_TRIGGER : WT; bitpos: [0]; default: 0; * Set this bit to trigger the process of manual encryption calculation. This action * should only be asserted when manual encryption status is 0. After this action, * manual encryption status becomes 1. After calculation is done, manual encryption @@ -2580,7 +3356,7 @@ extern "C" { * status will become 3. */ #define SPI_MEM_C_XTS_RELEASE (BIT(0)) -#define SPI_MEM_C_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_MEM_C_XTS_RELEASE_M (SPI_MEM_C_XTS_RELEASE_V << SPI_MEM_C_XTS_RELEASE_S) #define SPI_MEM_C_XTS_RELEASE_V 0x00000001U #define SPI_MEM_C_XTS_RELEASE_S 0 @@ -2594,7 +3370,7 @@ extern "C" { * become 0. */ #define SPI_MEM_C_XTS_DESTROY (BIT(0)) -#define SPI_MEM_C_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_MEM_C_XTS_DESTROY_M (SPI_MEM_C_XTS_DESTROY_V << SPI_MEM_C_XTS_DESTROY_S) #define SPI_MEM_C_XTS_DESTROY_V 0x00000001U #define SPI_MEM_C_XTS_DESTROY_S 0 @@ -2608,7 +3384,7 @@ extern "C" { * invisible to mspi, 3: the encrypted result is visible to mspi. */ #define SPI_MEM_C_XTS_STATE 0x00000003U -#define SPI_MEM_C_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_MEM_C_XTS_STATE_M (SPI_MEM_C_XTS_STATE_V << SPI_MEM_C_XTS_STATE_S) #define SPI_MEM_C_XTS_STATE_V 0x00000003U #define SPI_MEM_C_XTS_STATE_S 0 @@ -2616,11 +3392,11 @@ extern "C" { * Manual Encryption version register */ #define SPI_MEM_C_XTS_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x35c) -/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; +/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ #define SPI_MEM_C_XTS_DATE 0x3FFFFFFFU -#define SPI_MEM_C_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_MEM_C_XTS_DATE_M (SPI_MEM_C_XTS_DATE_V << SPI_MEM_C_XTS_DATE_S) #define SPI_MEM_C_XTS_DATE_V 0x3FFFFFFFU #define SPI_MEM_C_XTS_DATE_S 0 @@ -2632,7 +3408,7 @@ extern "C" { * MSPI-MMU item content */ #define SPI_MEM_C_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MEM_C_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MEM_C_MMU_ITEM_CONTENT_M (SPI_MEM_C_MMU_ITEM_CONTENT_V << SPI_MEM_C_MMU_ITEM_CONTENT_S) #define SPI_MEM_C_MMU_ITEM_CONTENT_V 0xFFFFFFFFU #define SPI_MEM_C_MMU_ITEM_CONTENT_S 0 @@ -2644,7 +3420,7 @@ extern "C" { * MSPI-MMU item index */ #define SPI_MEM_C_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MEM_C_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MEM_C_MMU_ITEM_INDEX_M (SPI_MEM_C_MMU_ITEM_INDEX_V << SPI_MEM_C_MMU_ITEM_INDEX_S) #define SPI_MEM_C_MMU_ITEM_INDEX_V 0xFFFFFFFFU #define SPI_MEM_C_MMU_ITEM_INDEX_S 0 @@ -2656,14 +3432,14 @@ extern "C" { * Set this bit to enable mmu-memory clock force on */ #define SPI_MEM_C_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MEM_C_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MEM_C_MMU_MEM_FORCE_ON_M (SPI_MEM_C_MMU_MEM_FORCE_ON_V << SPI_MEM_C_MMU_MEM_FORCE_ON_S) #define SPI_MEM_C_MMU_MEM_FORCE_ON_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_ON_S 0 /** SPI_MEM_C_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ #define SPI_MEM_C_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MEM_C_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PD_M (SPI_MEM_C_MMU_MEM_FORCE_PD_V << SPI_MEM_C_MMU_MEM_FORCE_PD_S) #define SPI_MEM_C_MMU_MEM_FORCE_PD_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_PD_S 1 /** SPI_MEM_C_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; @@ -2671,14 +3447,14 @@ extern "C" { * controlled by rtc. */ #define SPI_MEM_C_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MEM_C_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PU_M (SPI_MEM_C_MMU_MEM_FORCE_PU_V << SPI_MEM_C_MMU_MEM_FORCE_PU_S) #define SPI_MEM_C_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_PU_S 2 /** SPI_MEM_C_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ #define SPI_MEM_C_MMU_PAGE_SIZE 0x00000003U -#define SPI_MEM_C_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MEM_C_MMU_PAGE_SIZE_M (SPI_MEM_C_MMU_PAGE_SIZE_V << SPI_MEM_C_MMU_PAGE_SIZE_S) #define SPI_MEM_C_MMU_PAGE_SIZE_V 0x00000003U #define SPI_MEM_C_MMU_PAGE_SIZE_S 3 /** SPI_MEM_C_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; @@ -2688,6 +3464,22 @@ extern "C" { #define SPI_MEM_C_AUX_CTRL_M (SPI_MEM_C_AUX_CTRL_V << SPI_MEM_C_AUX_CTRL_S) #define SPI_MEM_C_AUX_CTRL_V 0x00003FFFU #define SPI_MEM_C_AUX_CTRL_S 16 +/** SPI_MEM_C_RDN_ENA : HRO; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_RDN_ENA (BIT(30)) +#define SPI_MEM_C_RDN_ENA_M (SPI_MEM_C_RDN_ENA_V << SPI_MEM_C_RDN_ENA_S) +#define SPI_MEM_C_RDN_ENA_V 0x00000001U +#define SPI_MEM_C_RDN_ENA_S 30 +/** SPI_MEM_C_RDN_RESULT : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_RDN_RESULT (BIT(31)) +#define SPI_MEM_C_RDN_RESULT_M (SPI_MEM_C_RDN_RESULT_V << SPI_MEM_C_RDN_RESULT_S) +#define SPI_MEM_C_RDN_RESULT_V 0x00000001U +#define SPI_MEM_C_RDN_RESULT_S 31 /** SPI_MEM_C_DPA_CTRL_REG register * SPI memory cryption DPA register @@ -2699,32 +3491,98 @@ extern "C" { * performance of cryption will decrease together with this number increasing) */ #define SPI_MEM_C_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M (SPI_MEM_C_CRYPT_SECURITY_LEVEL_V << SPI_MEM_C_CRYPT_SECURITY_LEVEL_S) #define SPI_MEM_C_CRYPT_SECURITY_LEVEL_V 0x00000007U #define SPI_MEM_C_CRYPT_SECURITY_LEVEL_S 0 /** SPI_MEM_C_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * Only available when SPI_MEM_C_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that * using key 1. */ #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M (SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V << SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S) #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V 0x00000001U #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S 3 /** SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + * 1: MSPI XTS DPA clock gate is controlled by SPI_MEM_C_CRYPT_CALC_D_DPA_EN and + * SPI_MEM_C_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M (SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V << SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S) #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S 4 +/** SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_FLASH_SPI0_BASE + 0x38c) +/** SPI_MEM_C_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_C_MODE_PSEUDO 0x00000003U +#define SPI_MEM_C_MODE_PSEUDO_M (SPI_MEM_C_MODE_PSEUDO_V << SPI_MEM_C_MODE_PSEUDO_S) +#define SPI_MEM_C_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_C_MODE_PSEUDO_S 0 +/** SPI_MEM_C_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_C_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_C_PSEUDO_RNG_CNT_M (SPI_MEM_C_PSEUDO_RNG_CNT_V << SPI_MEM_C_PSEUDO_RNG_CNT_S) +#define SPI_MEM_C_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_C_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_C_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_C_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_C_PSEUDO_BASE_M (SPI_MEM_C_PSEUDO_BASE_V << SPI_MEM_C_PSEUDO_BASE_S) +#define SPI_MEM_C_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_C_PSEUDO_BASE_S 5 +/** SPI_MEM_C_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_C_PSEUDO_INC 0x00000003U +#define SPI_MEM_C_PSEUDO_INC_M (SPI_MEM_C_PSEUDO_INC_V << SPI_MEM_C_PSEUDO_INC_S) +#define SPI_MEM_C_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_C_PSEUDO_INC_S 9 + +/** SPI_MEM_C_REGISTERRND_ECO_HIGH_REG register + * MSPI ECO high register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_REG (DR_REG_FLASH_SPI0_BASE + 0x3f0) +/** SPI_MEM_C_REGISTERRND_ECO_HIGH : RO; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_HIGH 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_M (SPI_MEM_C_REGISTERRND_ECO_HIGH_V << SPI_MEM_C_REGISTERRND_ECO_HIGH_S) +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_S 0 + +/** SPI_MEM_C_REGISTERRND_ECO_LOW_REG register + * MSPI ECO low register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_LOW_REG (DR_REG_FLASH_SPI0_BASE + 0x3f4) +/** SPI_MEM_C_REGISTERRND_ECO_LOW : RO; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_LOW 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_LOW_M (SPI_MEM_C_REGISTERRND_ECO_LOW_V << SPI_MEM_C_REGISTERRND_ECO_LOW_S) +#define SPI_MEM_C_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_LOW_S 0 + /** SPI_MEM_C_DATE_REG register * SPI0 version control register */ #define SPI_MEM_C_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x3fc) -/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 36712560; +/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 38805888; * SPI0 register version. */ #define SPI_MEM_C_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h index 9ddcb3f6ce5..e4c093e73a7 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h @@ -30,9 +30,9 @@ typedef union { uint32_t slv_st:4; uint32_t reserved_8:10; /** usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ uint32_t usr:1; uint32_t reserved_19:13; @@ -47,8 +47,8 @@ typedef union { struct { /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_C_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_C_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_C_AXI_RADDR_ERR_IN_CLR bit is set. */ uint32_t axi_err_addr:27; uint32_t reserved_27:5; @@ -108,8 +108,8 @@ typedef union { uint32_t fcmd_oct:1; uint32_t reserved_10:3; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT - * and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, + * SPI_MEM_C_FREAD_QOUT and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -180,15 +180,11 @@ typedef union { * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; + uint32_t reserved_23:1; /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_C_ECC_ERR_ADDR_REG. + * in SPI_MEM_C_ECC_ERR_ADDR_REG. */ uint32_t rresp_ecc_err_en:1; /** ar_splice_en : HRO; bitpos: [25]; default: 0; @@ -200,9 +196,9 @@ typedef union { */ uint32_t aw_splice_en:1; /** ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t ram0_en:1; @@ -238,17 +234,17 @@ typedef union { struct { /** cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_C_CS_SETUP bit. + * SPI_MEM_C_CS_SETUP bit. */ uint32_t cs_setup_time:5; /** cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_C_CS_HOLD bit. + * SPI_MEM_C_CS_HOLD bit. */ uint32_t cs_hold_time:5; /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; - * spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ uint32_t ecc_cs_hold_time:3; /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; @@ -270,7 +266,7 @@ typedef union { uint32_t split_trans_en:1; /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_C_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t cs_hold_delay:6; @@ -287,7 +283,19 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:7; + uint32_t reserved_0:4; + /** dq_oe_ctrl : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ + uint32_t dq_oe_ctrl:1; + /** ck_oe_ctrl : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ + uint32_t ck_oe_ctrl:1; + /** cs_oe_ctrl : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ + uint32_t cs_oe_ctrl:1; /** fsub_pin : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -314,7 +322,83 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:30; + /** axi_req_en : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t axi_req_en:1; + /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_usr_addr_4byte:1; + /** cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_flash_usr_cmd:1; + /** fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdin_dual:1; + /** fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdout_dual:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t faddr_dual:1; + /** fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdin_quad:1; + /** fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdout_quad:1; + /** faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t faddr_quad:1; + /** arb_wei_en : HRO; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ + uint32_t arb_wei_en:1; + /** arb_req0_pri : HRO; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t arb_req0_pri:1; + /** arb_req1_pri : HRO; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t arb_req1_pri:1; + /** arb_req0_wei : HRO; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t arb_req0_wei:4; + /** arb_req1_wei : HRO; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t arb_req1_wei:4; + uint32_t reserved_20:10; /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -373,8 +457,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -420,16 +504,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_C_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_C_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_C_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -442,15 +526,47 @@ typedef union { uint32_t val; } spi_mem_c_clock_reg_t; +/** Type of sram_clk register + * SPI0 external RAM clock control register + */ +typedef union { + struct { + /** sclkcnt_l : HRO; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_C_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_l:8; + /** sclkcnt_h : HRO; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_C_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_h:8; + /** sclkcnt_n : HRO; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_C_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_n:8; + uint32_t reserved_24:7; + /** sclk_equ_sysclk : HRO; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_c_sram_clk_reg_t; + /** Type of clock_gate register * SPI0 clock gate register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 1; + /** clk : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ - uint32_t clk_en:1; + uint32_t clk:1; uint32_t reserved_1:31; }; uint32_t val; @@ -474,7 +590,7 @@ typedef union { uint32_t cs_setup:1; uint32_t reserved_8:1; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t ck_out_edge:1; uint32_t reserved_10:16; @@ -498,7 +614,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -533,14 +649,189 @@ typedef union { uint32_t val; } spi_mem_c_user2_reg_t; +/** Type of rd_status register + * SPI0 read control register. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t wb_mode:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi_mem_c_rd_status_reg_t; + /** Group: External RAM Control and configuration registers */ +/** Type of cache_sctrl register + * SPI0 external RAM control register + */ +typedef union { + struct { + /** cache_usr_saddr_4byte : HRO; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_usr_saddr_4byte:1; + /** usr_sram_dio : HRO; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_sram_dio:1; + /** usr_sram_qio : HRO; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_sram_qio:1; + /** usr_wr_sram_dummy : HRO; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_wr_sram_dummy:1; + /** usr_rd_sram_dummy : HRO; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_rd_sram_dummy:1; + /** cache_sram_usr_rcmd : HRO; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rcmd:1; + /** sram_rdummy_cyclelen : HRO; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_rdummy_cyclelen:6; + uint32_t reserved_12:2; + /** sram_addr_bitlen : HRO; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_addr_bitlen:6; + /** cache_sram_usr_wcmd : HRO; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wcmd:1; + /** sram_oct : HRO; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_oct:1; + /** sram_wdummy_cyclelen : HRO; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_wdummy_cyclelen:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_c_cache_sctrl_reg_t; + /** Type of sram_cmd register * SPI0 external RAM mode control register */ typedef union { struct { - uint32_t reserved_0:24; + /** sclk_mode : HRO; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclk_mode:2; + /** swb_mode : HRO; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t swb_mode:8; + /** sdin_dual : HRO; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_dual:1; + /** sdout_dual : HRO; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_dual:1; + /** saddr_dual : HRO; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_dual:1; + uint32_t reserved_13:1; + /** sdin_quad : HRO; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_quad:1; + /** sdout_quad : HRO; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_quad:1; + /** saddr_quad : HRO; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_quad:1; + /** scmd_quad : HRO; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t scmd_quad:1; + /** sdin_oct : HRO; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_oct:1; + /** sdout_oct : HRO; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_oct:1; + /** saddr_oct : HRO; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_oct:1; + /** scmd_oct : HRO; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t scmd_oct:1; + /** sdummy_rin : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdummy_rin:1; + /** sdummy_wout : HRO; bitpos: [23]; default: 0; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdummy_wout:1; /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -566,6 +857,50 @@ typedef union { uint32_t val; } spi_mem_c_sram_cmd_reg_t; +/** Type of sram_drd_cmd register + * SPI0 external RAM DDR read command control register + */ +typedef union { + struct { + /** cache_sram_usr_rd_cmd_value : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rd_cmd_value:16; + uint32_t reserved_16:12; + /** cache_sram_usr_rd_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rd_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_c_sram_drd_cmd_reg_t; + +/** Type of sram_dwr_cmd register + * SPI0 external RAM DDR write command control register + */ +typedef union { + struct { + /** cache_sram_usr_wr_cmd_value : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wr_cmd_value:16; + uint32_t reserved_16:12; + /** cache_sram_usr_wr_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wr_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_c_sram_dwr_cmd_reg_t; + /** Type of smem_ddr register * SPI0 external RAM DDR mode control register */ @@ -611,8 +946,8 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t smem_ddr_dqs_loop:1; @@ -667,17 +1002,17 @@ typedef union { uint32_t smem_cs_hold:1; /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_c_cs_setup bit. + * spi_mem_cs_setup bit. */ uint32_t smem_cs_setup_time:5; /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_c_cs_hold bit. + * combined with spi_mem_cs_hold bit. */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; - * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; @@ -693,8 +1028,8 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; /** smem_split_trans_en : HRO; bitpos: [31]; default: 1; @@ -715,11 +1050,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t lock_delay_time:12; + uint32_t reserved_19:13; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -733,34 +1068,43 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_ena:1; /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_ena:1; /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_ena:1; /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_ena:1; /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_ena:1; /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_ena:1; /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int__ena:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_ena : HRO; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_ena:1; + /** tx_trans_udf_int_ena : HRO; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_ena:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_ena_reg_t; @@ -772,34 +1116,43 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_clr:1; /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_clr:1; /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_clr:1; /** pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_clr:1; /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_clr:1; /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_clr:1; /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int_clr:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_clr : HRO; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_clr:1; + /** tx_trans_udf_int_clr : HRO; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_clr:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_clr_reg_t; @@ -811,50 +1164,62 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set - * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When - * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and - * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When + * SPI_MEM_C_fmem_ECC_ERR_INT_EN is set and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is + * cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are + * equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN + * is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when + * the error times of SPI0/1 ECC read external RAM are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error + * times of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. */ uint32_t ecc_err_int_raw:1; /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ uint32_t pms_reject_int_raw:1; /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t axi_raddr_err_int_raw:1; /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ uint32_t axi_wr_flash_err_int_raw:1; /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t axi_waddr_err_int_raw:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ + uint32_t rx_trans_ovf_int_raw:1; + /** tx_trans_udf_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ + uint32_t tx_trans_udf_int_raw:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_raw_reg_t; @@ -866,42 +1231,112 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_st:1; /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_st:1; /** ecc_err_int_st : HRO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The status bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_st:1; /** pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_st:1; /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_st:1; /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_st:1; /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int_st:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_st : HRO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_st:1; + /** tx_trans_udf_int_st : HRO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_st:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_st_reg_t; +/** Group: DLL debug and configuration registers */ +/** Type of dll_dly_db register + * MSPI DLL function and debug configuration register + */ +typedef union { + struct { + /** dll_db_cfg_vld_cnt : HRO; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ + uint32_t dll_db_cfg_vld_cnt:8; + /** dll_db_cnt_mode_sel : HRO; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ + uint32_t dll_db_cnt_mode_sel:4; + /** dll_db_cnt_clr : HRO; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ + uint32_t dll_db_cnt_clr:1; + /** dll_din_dly_sel : HRO; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ + uint32_t dll_din_dly_sel:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} spi_mem_c_dll_dly_db_reg_t; + + +/** Group: DLL debug status registers */ +/** Type of dll_db_st0 register + * MSPI DLL debug status0 register + */ +typedef union { + struct { + /** db_fifo_cnt_h : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ + uint32_t db_fifo_cnt_h:32; + }; + uint32_t val; +} spi_mem_c_dll_db_st0_reg_t; + +/** Type of dll_db_st1 register + * MSPI DLL debug status1 register + */ +typedef union { + struct { + /** db_fifo_cnt_l : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ + uint32_t db_fifo_cnt_l:32; + }; + uint32_t val; +} spi_mem_c_dll_db_st1_reg_t; + + /** Group: PMS control and configuration registers */ /** Type of fmem_pmsn_attr register - * MSPI flash PMS section n attribute register + * SPI1 flash PMS section n attribute register */ typedef union { struct { @@ -915,11 +1350,25 @@ typedef union { uint32_t fmem_pmsn_wr_attr:1; /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and - * SPI_MEM_C_FMEM__PMSn_SIZE_REG. + * section n is configured by registers SPI_MEM_C_fmem_PMSn_ADDR_REG and + * SPI_MEM_C_fmem_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_rd_attr:1; + /** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_wr_attr:1; + /** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section n is configured by registers SPI_MEM_C_fmem_PMSn_ADDR_REG + * and SPI_MEM_C_fmem_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_c_fmem_pmsn_attr_reg_t; @@ -944,8 +1393,8 @@ typedef union { typedef union { struct { /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S, - * SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE) + * SPI1 flash PMS section n address region is (SPI_MEM_C_fmem_PMSn_ADDR_S, + * SPI_MEM_C_fmem_PMSn_ADDR_S + SPI_MEM_C_fmem_PMSn_SIZE) */ uint32_t fmem_pmsn_size:15; uint32_t reserved_15:17; @@ -954,7 +1403,7 @@ typedef union { } spi_mem_c_fmem_pmsn_size_reg_t; /** Type of smem_pmsn_attr register - * SPI1 flash PMS section n start address register + * SPI1 external RAM PMS section n attribute register */ typedef union { struct { @@ -968,11 +1417,25 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and - * SPI_MEM_C_SMEM_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG + * and SPI_MEM_C_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_rd_attr:1; + /** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_wr_attr:1; + /** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section n is configured by registers + * SPI_MEM_C_SMEM_PMSn_ADDR_REG and SPI_MEM_C_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_c_smem_pmsn_attr_reg_t; @@ -1013,7 +1476,7 @@ typedef union { struct { /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t reject_addr:27; /** pm_en : R/W; bitpos: [27]; default: 0; @@ -1022,22 +1485,22 @@ typedef union { uint32_t pm_en:1; /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_ld:1; /** pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_st:1; /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_multi_hit:1; /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_ivd:1; }; @@ -1054,11 +1517,12 @@ typedef union { uint32_t reserved_0:5; /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. */ uint32_t ecc_err_cnt:6; /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT + * interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; @@ -1082,9 +1546,9 @@ typedef union { uint32_t usr_ecc_addr_en:1; uint32_t reserved_22:2; /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and - * spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in SPI_MEM_C_ECC_ERR_BITS and SPI_MEM_C_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_C_ECC_ERR_BITS and + * SPI_MEM_C_ECC_ERR_ADDR record the first ECC error information. */ uint32_t ecc_continue_record_err_en:1; /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0; @@ -1103,7 +1567,7 @@ typedef union { struct { /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. */ uint32_t ecc_err_addr:27; uint32_t reserved_27:5; @@ -1744,13 +2208,13 @@ typedef union { */ typedef union { struct { - /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ - uint32_t xts_physical_address:26; - uint32_t reserved_26:6; + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; }; uint32_t val; } spi_mem_c_xts_physical_address_reg_t; @@ -1829,7 +2293,7 @@ typedef union { */ typedef union { struct { - /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ uint32_t xts_date:30; @@ -1895,7 +2359,16 @@ typedef union { * MMU PSRAM aux control register */ uint32_t aux_ctrl:14; - uint32_t reserved_30:2; + /** rdn_ena : HRO; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t rdn_result:1; }; uint32_t val; } spi_mem_c_mmu_power_ctrl_reg_t; @@ -1914,14 +2387,14 @@ typedef union { */ uint32_t crypt_security_level:3; /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * Only available when SPI_MEM_C_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that * using key 1. */ uint32_t crypt_calc_d_dpa_en:1; /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + * 1: MSPI XTS DPA clock gate is controlled by SPI_MEM_C_CRYPT_CALC_D_DPA_EN and + * SPI_MEM_C_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ uint32_t crypt_dpa_select_register:1; uint32_t reserved_5:27; @@ -1930,13 +2403,74 @@ typedef union { } spi_mem_c_dpa_ctrl_reg_t; +/** Group: External mem cryption PSEUDO registers */ +/** Type of xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mode_pseudo:2; + /** pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t pseudo_rng_cnt:3; + /** pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ + uint32_t pseudo_base:4; + /** pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ + uint32_t pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_c_xts_pseudo_round_conf_reg_t; + + +/** Group: ECO registers */ +/** Type of registerrnd_eco_high register + * MSPI ECO high register + */ +typedef union { + struct { + /** registerrnd_eco_high : RO; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t registerrnd_eco_high:32; + }; + uint32_t val; +} spi_mem_c_registerrnd_eco_high_reg_t; + +/** Type of registerrnd_eco_low register + * MSPI ECO low register + */ +typedef union { + struct { + /** registerrnd_eco_low : RO; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t registerrnd_eco_low:32; + }; + uint32_t val; +} spi_mem_c_registerrnd_eco_low_reg_t; + + /** Group: Version control register */ /** Type of date register * SPI0 version control register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36712560; + /** date : R/W; bitpos: [27:0]; default: 38805888; * SPI0 register version. */ uint32_t date:28; @@ -1946,7 +2480,7 @@ typedef union { } spi_mem_c_date_reg_t; -typedef struct spi_mem_c_dev_s { +typedef struct { volatile spi_mem_c_cmd_reg_t cmd; uint32_t reserved_004; volatile spi_mem_c_ctrl_reg_t ctrl; @@ -1956,13 +2490,17 @@ typedef struct spi_mem_c_dev_s { volatile spi_mem_c_user_reg_t user; volatile spi_mem_c_user1_reg_t user1; volatile spi_mem_c_user2_reg_t user2; - uint32_t reserved_024[4]; + uint32_t reserved_024[2]; + volatile spi_mem_c_rd_status_reg_t rd_status; + uint32_t reserved_030; volatile spi_mem_c_misc_reg_t misc; uint32_t reserved_038; volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl; - uint32_t reserved_040; + volatile spi_mem_c_cache_sctrl_reg_t cache_sctrl; volatile spi_mem_c_sram_cmd_reg_t sram_cmd; - uint32_t reserved_048[3]; + volatile spi_mem_c_sram_drd_cmd_reg_t sram_drd_cmd; + volatile spi_mem_c_sram_dwr_cmd_reg_t sram_dwr_cmd; + volatile spi_mem_c_sram_clk_reg_t sram_clk; volatile spi_mem_c_fsm_reg_t fsm; uint32_t reserved_058[26]; volatile spi_mem_c_int_ena_reg_t int_ena; @@ -1972,7 +2510,10 @@ typedef struct spi_mem_c_dev_s { uint32_t reserved_0d0; volatile spi_mem_c_ddr_reg_t ddr; volatile spi_mem_c_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; + volatile spi_mem_c_dll_dly_db_reg_t dll_dly_db; + volatile spi_mem_c_dll_db_st0_reg_t dll_db_st0; + volatile spi_mem_c_dll_db_st1_reg_t dll_db_st1; + uint32_t reserved_0e8[6]; volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; @@ -2014,7 +2555,11 @@ typedef struct spi_mem_c_dev_s { volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index; volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl; volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl; - uint32_t reserved_38c[28]; + volatile spi_mem_c_xts_pseudo_round_conf_reg_t xts_pseudo_round_conf; + uint32_t reserved_390[24]; + volatile spi_mem_c_registerrnd_eco_high_reg_t registerrnd_eco_high; + volatile spi_mem_c_registerrnd_eco_low_reg_t registerrnd_eco_low; + uint32_t reserved_3f8; volatile spi_mem_c_date_reg_t date; } spi_mem_c_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h index cb15d5b07d2..003f89681ec 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h @@ -34,9 +34,9 @@ extern "C" { #define SPI_MEM_S_SLV_ST_V 0x0000000FU #define SPI_MEM_S_SLV_ST_S 4 /** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ #define SPI_MEM_S_USR (BIT(18)) #define SPI_MEM_S_USR_M (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S) @@ -117,8 +117,8 @@ extern "C" { #define SPI_MEM_S_FCMD_OCT_V 0x00000001U #define SPI_MEM_S_FCMD_OCT_S 9 /** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT - * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, + * SPI_MEM_S_FREAD_QOUT and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. */ #define SPI_MEM_S_FASTRD_MODE (BIT(13)) #define SPI_MEM_S_FASTRD_MODE_M (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S) @@ -220,14 +220,6 @@ extern "C" { #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_MEM_S_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S) -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S 23 /** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -316,8 +308,8 @@ extern "C" { #define SPI_MEM_S_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_S_CS_HOLD_TIME_S 5 /** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ #define SPI_MEM_S_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_S_ECC_CS_HOLD_TIME_M (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S) @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14) /** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_S_CLKCNT_N. */ #define SPI_MEM_S_CLKCNT_L 0x000000FFU #define SPI_MEM_S_CLKCNT_L_M (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S) #define SPI_MEM_S_CLKCNT_L_V 0x000000FFU #define SPI_MEM_S_CLKCNT_L_S 0 /** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_S_CLKCNT_N+1)/2-1). */ #define SPI_MEM_S_CLKCNT_H 0x000000FFU #define SPI_MEM_S_CLKCNT_H_M (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_S_CLKCNT_H_S 8 /** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_S_CLKCNT_N+1) */ #define SPI_MEM_S_CLKCNT_N 0x000000FFU #define SPI_MEM_S_CLKCNT_N_M (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S) @@ -488,10 +480,13 @@ extern "C" { /** SPI_MEM_S_RD_STATUS_REG register * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x2c) /** SPI_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_WB_MODE 0x000000FFU #define SPI_MEM_S_WB_MODE_M (SPI_MEM_S_WB_MODE_V << SPI_MEM_S_WB_MODE_S) @@ -502,14 +497,35 @@ extern "C" { * SPI0 misc register */ #define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34) -/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0; +/** SPI_MEM_S_DQ_OE_CTRL : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_DQ_OE_CTRL (BIT(4)) +#define SPI_MEM_S_DQ_OE_CTRL_M (SPI_MEM_S_DQ_OE_CTRL_V << SPI_MEM_S_DQ_OE_CTRL_S) +#define SPI_MEM_S_DQ_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_DQ_OE_CTRL_S 4 +/** SPI_MEM_S_CK_OE_CTRL : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_CK_OE_CTRL (BIT(5)) +#define SPI_MEM_S_CK_OE_CTRL_M (SPI_MEM_S_CK_OE_CTRL_V << SPI_MEM_S_CK_OE_CTRL_S) +#define SPI_MEM_S_CK_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_CK_OE_CTRL_S 5 +/** SPI_MEM_S_CS_OE_CTRL : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_CS_OE_CTRL (BIT(6)) +#define SPI_MEM_S_CS_OE_CTRL_M (SPI_MEM_S_CS_OE_CTRL_V << SPI_MEM_S_CS_OE_CTRL_S) +#define SPI_MEM_S_CS_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_CS_OE_CTRL_S 6 +/** SPI_MEM_S_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ #define SPI_MEM_S_FSUB_PIN (BIT(7)) #define SPI_MEM_S_FSUB_PIN_M (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S) #define SPI_MEM_S_FSUB_PIN_V 0x00000001U #define SPI_MEM_S_FSUB_PIN_S 7 -/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0; +/** SPI_MEM_S_SSUB_PIN : HRO; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ #define SPI_MEM_S_SSUB_PIN (BIT(8)) @@ -537,6 +553,7 @@ extern "C" { #define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c) /** SPI_MEM_S_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_AXI_REQ_EN (BIT(0)) #define SPI_MEM_S_AXI_REQ_EN_M (SPI_MEM_S_AXI_REQ_EN_V << SPI_MEM_S_AXI_REQ_EN_S) @@ -544,6 +561,7 @@ extern "C" { #define SPI_MEM_S_AXI_REQ_EN_S 0 /** SPI_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S) @@ -551,6 +569,7 @@ extern "C" { #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 /** SPI_MEM_S_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_FLASH_USR_CMD (BIT(2)) #define SPI_MEM_S_CACHE_FLASH_USR_CMD_M (SPI_MEM_S_CACHE_FLASH_USR_CMD_V << SPI_MEM_S_CACHE_FLASH_USR_CMD_S) @@ -559,6 +578,7 @@ extern "C" { /** SPI_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDIN_DUAL (BIT(3)) #define SPI_MEM_S_FDIN_DUAL_M (SPI_MEM_S_FDIN_DUAL_V << SPI_MEM_S_FDIN_DUAL_S) @@ -567,6 +587,7 @@ extern "C" { /** SPI_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDOUT_DUAL (BIT(4)) #define SPI_MEM_S_FDOUT_DUAL_M (SPI_MEM_S_FDOUT_DUAL_V << SPI_MEM_S_FDOUT_DUAL_S) @@ -575,6 +596,7 @@ extern "C" { /** SPI_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FADDR_DUAL (BIT(5)) #define SPI_MEM_S_FADDR_DUAL_M (SPI_MEM_S_FADDR_DUAL_V << SPI_MEM_S_FADDR_DUAL_S) @@ -583,6 +605,7 @@ extern "C" { /** SPI_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDIN_QUAD (BIT(6)) #define SPI_MEM_S_FDIN_QUAD_M (SPI_MEM_S_FDIN_QUAD_V << SPI_MEM_S_FDIN_QUAD_S) @@ -591,6 +614,7 @@ extern "C" { /** SPI_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDOUT_QUAD (BIT(7)) #define SPI_MEM_S_FDOUT_QUAD_M (SPI_MEM_S_FDOUT_QUAD_V << SPI_MEM_S_FDOUT_QUAD_S) @@ -599,11 +623,52 @@ extern "C" { /** SPI_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FADDR_QUAD (BIT(8)) #define SPI_MEM_S_FADDR_QUAD_M (SPI_MEM_S_FADDR_QUAD_V << SPI_MEM_S_FADDR_QUAD_S) #define SPI_MEM_S_FADDR_QUAD_V 0x00000001U #define SPI_MEM_S_FADDR_QUAD_S 8 +/** SPI_MEM_S_ARB_WEI_EN : R/W; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ +#define SPI_MEM_S_ARB_WEI_EN (BIT(9)) +#define SPI_MEM_S_ARB_WEI_EN_M (SPI_MEM_S_ARB_WEI_EN_V << SPI_MEM_S_ARB_WEI_EN_S) +#define SPI_MEM_S_ARB_WEI_EN_V 0x00000001U +#define SPI_MEM_S_ARB_WEI_EN_S 9 +/** SPI_MEM_S_ARB_REQ0_PRI : R/W; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_S_ARB_REQ0_PRI (BIT(10)) +#define SPI_MEM_S_ARB_REQ0_PRI_M (SPI_MEM_S_ARB_REQ0_PRI_V << SPI_MEM_S_ARB_REQ0_PRI_S) +#define SPI_MEM_S_ARB_REQ0_PRI_V 0x00000001U +#define SPI_MEM_S_ARB_REQ0_PRI_S 10 +/** SPI_MEM_S_ARB_REQ1_PRI : R/W; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_S_ARB_REQ1_PRI (BIT(11)) +#define SPI_MEM_S_ARB_REQ1_PRI_M (SPI_MEM_S_ARB_REQ1_PRI_V << SPI_MEM_S_ARB_REQ1_PRI_S) +#define SPI_MEM_S_ARB_REQ1_PRI_V 0x00000001U +#define SPI_MEM_S_ARB_REQ1_PRI_S 11 +/** SPI_MEM_S_ARB_REQ0_WEI : R/W; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_S_ARB_REQ0_WEI 0x0000000FU +#define SPI_MEM_S_ARB_REQ0_WEI_M (SPI_MEM_S_ARB_REQ0_WEI_V << SPI_MEM_S_ARB_REQ0_WEI_S) +#define SPI_MEM_S_ARB_REQ0_WEI_V 0x0000000FU +#define SPI_MEM_S_ARB_REQ0_WEI_S 12 +/** SPI_MEM_S_ARB_REQ1_WEI : R/W; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_S_ARB_REQ1_WEI 0x0000000FU +#define SPI_MEM_S_ARB_REQ1_WEI_M (SPI_MEM_S_ARB_REQ1_WEI_V << SPI_MEM_S_ARB_REQ1_WEI_S) +#define SPI_MEM_S_ARB_REQ1_WEI_V 0x0000000FU +#define SPI_MEM_S_ARB_REQ1_WEI_S 16 /** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -622,11 +687,14 @@ extern "C" { /** SPI_MEM_S_CACHE_SCTRL_REG register * SPI0 external RAM control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_CACHE_SCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x40) /** SPI_MEM_S_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE (BIT(0)) #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S) @@ -634,6 +702,7 @@ extern "C" { #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S 0 /** SPI_MEM_S_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_SRAM_DIO (BIT(1)) #define SPI_MEM_S_USR_SRAM_DIO_M (SPI_MEM_S_USR_SRAM_DIO_V << SPI_MEM_S_USR_SRAM_DIO_S) @@ -641,6 +710,7 @@ extern "C" { #define SPI_MEM_S_USR_SRAM_DIO_S 1 /** SPI_MEM_S_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_SRAM_QIO (BIT(2)) #define SPI_MEM_S_USR_SRAM_QIO_M (SPI_MEM_S_USR_SRAM_QIO_V << SPI_MEM_S_USR_SRAM_QIO_S) @@ -649,6 +719,7 @@ extern "C" { /** SPI_MEM_S_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_WR_SRAM_DUMMY (BIT(3)) #define SPI_MEM_S_USR_WR_SRAM_DUMMY_M (SPI_MEM_S_USR_WR_SRAM_DUMMY_V << SPI_MEM_S_USR_WR_SRAM_DUMMY_S) @@ -657,6 +728,7 @@ extern "C" { /** SPI_MEM_S_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_RD_SRAM_DUMMY (BIT(4)) #define SPI_MEM_S_USR_RD_SRAM_DUMMY_M (SPI_MEM_S_USR_RD_SRAM_DUMMY_V << SPI_MEM_S_USR_RD_SRAM_DUMMY_S) @@ -664,6 +736,7 @@ extern "C" { #define SPI_MEM_S_USR_RD_SRAM_DUMMY_S 4 /** SPI_MEM_S_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RCMD (BIT(5)) #define SPI_MEM_S_CACHE_SRAM_USR_RCMD_M (SPI_MEM_S_CACHE_SRAM_USR_RCMD_V << SPI_MEM_S_CACHE_SRAM_USR_RCMD_S) @@ -672,6 +745,7 @@ extern "C" { /** SPI_MEM_S_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN 0x0000003FU #define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S) @@ -680,6 +754,7 @@ extern "C" { /** SPI_MEM_S_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_ADDR_BITLEN 0x0000003FU #define SPI_MEM_S_SRAM_ADDR_BITLEN_M (SPI_MEM_S_SRAM_ADDR_BITLEN_V << SPI_MEM_S_SRAM_ADDR_BITLEN_S) @@ -687,6 +762,7 @@ extern "C" { #define SPI_MEM_S_SRAM_ADDR_BITLEN_S 14 /** SPI_MEM_S_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WCMD (BIT(20)) #define SPI_MEM_S_CACHE_SRAM_USR_WCMD_M (SPI_MEM_S_CACHE_SRAM_USR_WCMD_V << SPI_MEM_S_CACHE_SRAM_USR_WCMD_S) @@ -694,6 +770,7 @@ extern "C" { #define SPI_MEM_S_CACHE_SRAM_USR_WCMD_S 20 /** SPI_MEM_S_SRAM_OCT : R/W; bitpos: [21]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_OCT (BIT(21)) #define SPI_MEM_S_SRAM_OCT_M (SPI_MEM_S_SRAM_OCT_V << SPI_MEM_S_SRAM_OCT_S) @@ -702,6 +779,7 @@ extern "C" { /** SPI_MEM_S_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN 0x0000003FU #define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S) @@ -716,6 +794,7 @@ extern "C" { * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLK_MODE 0x00000003U #define SPI_MEM_S_SCLK_MODE_M (SPI_MEM_S_SCLK_MODE_V << SPI_MEM_S_SCLK_MODE_S) @@ -724,6 +803,7 @@ extern "C" { /** SPI_MEM_S_SWB_MODE : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SWB_MODE 0x000000FFU #define SPI_MEM_S_SWB_MODE_M (SPI_MEM_S_SWB_MODE_V << SPI_MEM_S_SWB_MODE_S) @@ -732,6 +812,7 @@ extern "C" { /** SPI_MEM_S_SDIN_DUAL : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_DUAL (BIT(10)) #define SPI_MEM_S_SDIN_DUAL_M (SPI_MEM_S_SDIN_DUAL_V << SPI_MEM_S_SDIN_DUAL_S) @@ -740,6 +821,7 @@ extern "C" { /** SPI_MEM_S_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_DUAL (BIT(11)) #define SPI_MEM_S_SDOUT_DUAL_M (SPI_MEM_S_SDOUT_DUAL_V << SPI_MEM_S_SDOUT_DUAL_S) @@ -748,6 +830,7 @@ extern "C" { /** SPI_MEM_S_SADDR_DUAL : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_DUAL (BIT(12)) #define SPI_MEM_S_SADDR_DUAL_M (SPI_MEM_S_SADDR_DUAL_V << SPI_MEM_S_SADDR_DUAL_S) @@ -756,6 +839,7 @@ extern "C" { /** SPI_MEM_S_SDIN_QUAD : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_QUAD (BIT(14)) #define SPI_MEM_S_SDIN_QUAD_M (SPI_MEM_S_SDIN_QUAD_V << SPI_MEM_S_SDIN_QUAD_S) @@ -764,6 +848,7 @@ extern "C" { /** SPI_MEM_S_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_QUAD (BIT(15)) #define SPI_MEM_S_SDOUT_QUAD_M (SPI_MEM_S_SDOUT_QUAD_V << SPI_MEM_S_SDOUT_QUAD_S) @@ -772,6 +857,7 @@ extern "C" { /** SPI_MEM_S_SADDR_QUAD : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_QUAD (BIT(16)) #define SPI_MEM_S_SADDR_QUAD_M (SPI_MEM_S_SADDR_QUAD_V << SPI_MEM_S_SADDR_QUAD_S) @@ -780,6 +866,7 @@ extern "C" { /** SPI_MEM_S_SCMD_QUAD : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCMD_QUAD (BIT(17)) #define SPI_MEM_S_SCMD_QUAD_M (SPI_MEM_S_SCMD_QUAD_V << SPI_MEM_S_SCMD_QUAD_S) @@ -787,6 +874,7 @@ extern "C" { #define SPI_MEM_S_SCMD_QUAD_S 17 /** SPI_MEM_S_SDIN_OCT : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_OCT (BIT(18)) #define SPI_MEM_S_SDIN_OCT_M (SPI_MEM_S_SDIN_OCT_V << SPI_MEM_S_SDIN_OCT_S) @@ -794,6 +882,7 @@ extern "C" { #define SPI_MEM_S_SDIN_OCT_S 18 /** SPI_MEM_S_SDOUT_OCT : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_OCT (BIT(19)) #define SPI_MEM_S_SDOUT_OCT_M (SPI_MEM_S_SDOUT_OCT_V << SPI_MEM_S_SDOUT_OCT_S) @@ -801,6 +890,7 @@ extern "C" { #define SPI_MEM_S_SDOUT_OCT_S 19 /** SPI_MEM_S_SADDR_OCT : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_OCT (BIT(20)) #define SPI_MEM_S_SADDR_OCT_M (SPI_MEM_S_SADDR_OCT_V << SPI_MEM_S_SADDR_OCT_S) @@ -808,6 +898,7 @@ extern "C" { #define SPI_MEM_S_SADDR_OCT_S 20 /** SPI_MEM_S_SCMD_OCT : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCMD_OCT (BIT(21)) #define SPI_MEM_S_SCMD_OCT_M (SPI_MEM_S_SCMD_OCT_V << SPI_MEM_S_SCMD_OCT_S) @@ -816,6 +907,7 @@ extern "C" { /** SPI_MEM_S_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDUMMY_RIN (BIT(22)) #define SPI_MEM_S_SDUMMY_RIN_M (SPI_MEM_S_SDUMMY_RIN_V << SPI_MEM_S_SDUMMY_RIN_S) @@ -824,6 +916,7 @@ extern "C" { /** SPI_MEM_S_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDUMMY_WOUT (BIT(23)) #define SPI_MEM_S_SDUMMY_WOUT_M (SPI_MEM_S_SDUMMY_WOUT_V << SPI_MEM_S_SDUMMY_WOUT_S) @@ -831,7 +924,7 @@ extern "C" { #define SPI_MEM_S_SDUMMY_WOUT_S 23 /** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_MEM_S_DQS is output by the MSPI controller. + * the level of SPI_DQS is output by the MSPI controller. */ #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) @@ -839,7 +932,7 @@ extern "C" { #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 /** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_MEM_S_IO[7:0] is output by the MSPI controller. + * the level of SPI_IO[7:0] is output by the MSPI controller. */ #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S) @@ -847,6 +940,7 @@ extern "C" { #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S 25 /** SPI_MEM_S_SDIN_HEX : R/W; bitpos: [26]; default: 0; * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_HEX (BIT(26)) #define SPI_MEM_S_SDIN_HEX_M (SPI_MEM_S_SDIN_HEX_V << SPI_MEM_S_SDIN_HEX_S) @@ -854,13 +948,14 @@ extern "C" { #define SPI_MEM_S_SDIN_HEX_S 26 /** SPI_MEM_S_SDOUT_HEX : R/W; bitpos: [27]; default: 0; * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_HEX (BIT(27)) #define SPI_MEM_S_SDOUT_HEX_M (SPI_MEM_S_SDOUT_HEX_V << SPI_MEM_S_SDOUT_HEX_S) #define SPI_MEM_S_SDOUT_HEX_V 0x00000001U #define SPI_MEM_S_SDOUT_HEX_S 27 /** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_DQS are + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) @@ -868,7 +963,7 @@ extern "C" { #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S 30 /** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_IO[7:0] + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ #define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) @@ -878,11 +973,14 @@ extern "C" { /** SPI_MEM_S_SRAM_DRD_CMD_REG register * SPI0 external RAM DDR read command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_DRD_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x48) /** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S) @@ -891,6 +989,7 @@ extern "C" { /** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S) @@ -899,11 +998,14 @@ extern "C" { /** SPI_MEM_S_SRAM_DWR_CMD_REG register * SPI0 external RAM DDR write command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_DWR_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x4c) /** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S) @@ -912,6 +1014,7 @@ extern "C" { /** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S) @@ -920,17 +1023,21 @@ extern "C" { /** SPI_MEM_S_SRAM_CLK_REG register * SPI0 external RAM clock control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_CLK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x50) /** SPI_MEM_S_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_S_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_L 0x000000FFU #define SPI_MEM_S_SCLKCNT_L_M (SPI_MEM_S_SCLKCNT_L_V << SPI_MEM_S_SCLKCNT_L_S) #define SPI_MEM_S_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_S_SCLKCNT_L_S 0 /** SPI_MEM_S_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_S_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_H 0x000000FFU #define SPI_MEM_S_SCLKCNT_H_M (SPI_MEM_S_SCLKCNT_H_V << SPI_MEM_S_SCLKCNT_H_S) @@ -938,7 +1045,8 @@ extern "C" { #define SPI_MEM_S_SCLKCNT_H_S 8 /** SPI_MEM_S_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_S_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_N 0x000000FFU #define SPI_MEM_S_SCLKCNT_N_M (SPI_MEM_S_SCLKCNT_N_V << SPI_MEM_S_SCLKCNT_N_S) @@ -947,6 +1055,7 @@ extern "C" { /** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_S_SCLK_EQU_SYSCLK_M (SPI_MEM_S_SCLK_EQU_SYSCLK_V << SPI_MEM_S_SCLK_EQU_SYSCLK_S) @@ -957,12 +1066,12 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54) -/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_S_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_S_LOCK_DELAY_TIME_M (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S) -#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_S_LOCK_DELAY_TIME_S 7 /** SPI_MEM_S_INT_ENA_REG register @@ -1018,6 +1127,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_M (SPI_MEM_S_RX_TRANS_OVF_INT_ENA_V << SPI_MEM_S_RX_TRANS_OVF_INT_ENA_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_M (SPI_MEM_S_TX_TRANS_UDF_INT_ENA_V << SPI_MEM_S_TX_TRANS_UDF_INT_ENA_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1100,6 +1223,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_CLR : WT; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_M (SPI_MEM_S_RX_TRANS_OVF_INT_CLR_V << SPI_MEM_S_RX_TRANS_OVF_INT_CLR_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_CLR : WT; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_M (SPI_MEM_S_TX_TRANS_UDF_INT_CLR_V << SPI_MEM_S_TX_TRANS_UDF_INT_CLR_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1134,8 +1271,8 @@ extern "C" { */ #define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8) /** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) @@ -1143,32 +1280,33 @@ extern "C" { #define SPI_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_S_SLV_ST_END_INT_RAW_S 3 /** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI_MEM_S_MST_ST_END_INT_RAW (BIT(4)) #define SPI_MEM_S_MST_ST_END_INT_RAW_M (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S) #define SPI_MEM_S_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_S_MST_ST_END_INT_RAW_S 4 /** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set - * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When - * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and - * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN + * is set and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when + * the error times of SPI0/1 ECC read flash are equal or bigger than + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of + * SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. + * When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this + * bit is triggered when the total error times of SPI0/1 ECC read external RAM and + * flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN are cleared, this + * bit will not be triggered. */ #define SPI_MEM_S_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_S_ECC_ERR_INT_RAW_M (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S) #define SPI_MEM_S_ECC_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_ECC_ERR_INT_RAW_S 5 /** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ #define SPI_MEM_S_PMS_REJECT_INT_RAW (BIT(6)) #define SPI_MEM_S_PMS_REJECT_INT_RAW_M (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S) @@ -1183,8 +1321,8 @@ extern "C" { #define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S 7 /** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ #define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) #define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S) @@ -1198,6 +1336,22 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_M (SPI_MEM_S_RX_TRANS_OVF_INT_RAW_V << SPI_MEM_S_RX_TRANS_OVF_INT_RAW_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_M (SPI_MEM_S_TX_TRANS_UDF_INT_RAW_V << SPI_MEM_S_TX_TRANS_UDF_INT_RAW_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. @@ -1215,16 +1369,16 @@ extern "C" { #define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U #define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S 29 /** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO + * is underflow. */ #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW (BIT(30)) #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S) #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S 30 /** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO + * is underflow. */ #define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW (BIT(31)) #define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S) @@ -1284,6 +1438,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_ST : RO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_M (SPI_MEM_S_RX_TRANS_OVF_INT_ST_V << SPI_MEM_S_RX_TRANS_OVF_INT_ST_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_ST : RO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_M (SPI_MEM_S_TX_TRANS_UDF_INT_ST_V << SPI_MEM_S_TX_TRANS_UDF_INT_ST_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1384,8 +1552,8 @@ extern "C" { #define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1509,8 +1677,8 @@ extern "C" { #define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_S_SMEM_DDR_DQS_LOOP (BIT(21)) @@ -1564,124 +1732,278 @@ extern "C" { #define SPI_MEM_S_SMEM_HYPERBUS_CA_V 0x00000001U #define SPI_MEM_S_SMEM_HYPERBUS_CA_S 30 +/** SPI_MEM_S_DLL_DLY_DB_REG register + * MSPI DLL function and debug configuration register + */ +#define SPI_MEM_S_DLL_DLY_DB_REG (DR_REG_PSRAM_MSPI0_BASE + 0xdc) +/** SPI_MEM_S_DLL_DB_CFG_VLD_CNT : R/W; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT 0x000000FFU +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_M (SPI_MEM_S_DLL_DB_CFG_VLD_CNT_V << SPI_MEM_S_DLL_DB_CFG_VLD_CNT_S) +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_V 0x000000FFU +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_S 0 +/** SPI_MEM_S_DLL_DB_CNT_MODE_SEL : R/W; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL 0x0000000FU +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_M (SPI_MEM_S_DLL_DB_CNT_MODE_SEL_V << SPI_MEM_S_DLL_DB_CNT_MODE_SEL_S) +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_V 0x0000000FU +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_S 8 +/** SPI_MEM_S_DLL_DB_CNT_CLR : R/W; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ +#define SPI_MEM_S_DLL_DB_CNT_CLR (BIT(12)) +#define SPI_MEM_S_DLL_DB_CNT_CLR_M (SPI_MEM_S_DLL_DB_CNT_CLR_V << SPI_MEM_S_DLL_DB_CNT_CLR_S) +#define SPI_MEM_S_DLL_DB_CNT_CLR_V 0x00000001U +#define SPI_MEM_S_DLL_DB_CNT_CLR_S 12 +/** SPI_MEM_S_DLL_DIN_DLY_SEL : R/W; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ +#define SPI_MEM_S_DLL_DIN_DLY_SEL (BIT(13)) +#define SPI_MEM_S_DLL_DIN_DLY_SEL_M (SPI_MEM_S_DLL_DIN_DLY_SEL_V << SPI_MEM_S_DLL_DIN_DLY_SEL_S) +#define SPI_MEM_S_DLL_DIN_DLY_SEL_V 0x00000001U +#define SPI_MEM_S_DLL_DIN_DLY_SEL_S 13 + +/** SPI_MEM_S_DLL_DB_ST0_REG register + * MSPI DLL debug status0 register + */ +#define SPI_MEM_S_DLL_DB_ST0_REG (DR_REG_PSRAM_MSPI0_BASE + 0xe0) +/** SPI_MEM_S_DB_FIFO_CNT_H : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ +#define SPI_MEM_S_DB_FIFO_CNT_H 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_H_M (SPI_MEM_S_DB_FIFO_CNT_H_V << SPI_MEM_S_DB_FIFO_CNT_H_S) +#define SPI_MEM_S_DB_FIFO_CNT_H_V 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_H_S 0 + +/** SPI_MEM_S_DLL_DB_ST1_REG register + * MSPI DLL debug status1 register + */ +#define SPI_MEM_S_DLL_DB_ST1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xe4) +/** SPI_MEM_S_DB_FIFO_CNT_L : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ +#define SPI_MEM_S_DB_FIFO_CNT_L 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_L_M (SPI_MEM_S_DB_FIFO_CNT_L_V << SPI_MEM_S_DB_FIFO_CNT_L_S) +#define SPI_MEM_S_DB_FIFO_CNT_L_V 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_L_S 0 + /** SPI_MEM_S_FMEM_PMS0_ATTR_REG register * MSPI flash PMS section $n attribute register */ #define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100) /** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS0_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS0_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and + * SPI_MEM_S_FMEM_PMS0_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS0_ECC_M (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S) #define SPI_MEM_S_FMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and + * SPI_MEM_S_FMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104) /** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS1_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS1_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and + * SPI_MEM_S_FMEM_PMS1_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS1_ECC_M (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S) #define SPI_MEM_S_FMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and + * SPI_MEM_S_FMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108) /** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS2_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS2_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and + * SPI_MEM_S_FMEM_PMS2_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS2_ECC_M (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S) #define SPI_MEM_S_FMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and + * SPI_MEM_S_FMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c) /** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS3_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS3_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and + * SPI_MEM_S_FMEM_PMS3_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS3_ECC_M (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S) #define SPI_MEM_S_FMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and + * SPI_MEM_S_FMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS0_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 0 start address register */ #define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110) /** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; - * SPI1 flash PMS section $n start address value + * SPI1 flash PMS section 0 start address value */ #define SPI_MEM_S_FMEM_PMS0_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS0_ADDR_S_M (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S) @@ -1689,11 +2011,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS0_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS1_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 1 start address register */ #define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114) -/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 1 start address value */ #define SPI_MEM_S_FMEM_PMS1_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS1_ADDR_S_M (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S) @@ -1701,11 +2023,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS1_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS2_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 2 start address register */ #define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118) -/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 2 start address value */ #define SPI_MEM_S_FMEM_PMS2_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS2_ADDR_S_M (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S) @@ -1713,11 +2035,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS2_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS3_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 3 start address register */ #define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c) -/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 3 start address value */ #define SPI_MEM_S_FMEM_PMS3_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS3_ADDR_S_M (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S) @@ -1725,12 +2047,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS3_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS0_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 0 start address register */ #define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120) /** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 0 address region is (SPI_MEM_S_FMEM_PMS0_ADDR_S, + * SPI_MEM_S_FMEM_PMS0_ADDR_S + SPI_MEM_S_FMEM_PMS0_SIZE) */ #define SPI_MEM_S_FMEM_PMS0_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS0_SIZE_M (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S) @@ -1738,12 +2060,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS0_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS1_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 1 start address register */ #define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124) /** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 1 address region is (SPI_MEM_S_FMEM_PMS1_ADDR_S, + * SPI_MEM_S_FMEM_PMS1_ADDR_S + SPI_MEM_S_FMEM_PMS1_SIZE) */ #define SPI_MEM_S_FMEM_PMS1_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS1_SIZE_M (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S) @@ -1751,12 +2073,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS1_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS2_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 2 start address register */ #define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128) /** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 2 address region is (SPI_MEM_S_FMEM_PMS2_ADDR_S, + * SPI_MEM_S_FMEM_PMS2_ADDR_S + SPI_MEM_S_FMEM_PMS2_SIZE) */ #define SPI_MEM_S_FMEM_PMS2_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS2_SIZE_M (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S) @@ -1764,12 +2086,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS2_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS3_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 3 start address register */ #define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c) /** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 3 address region is (SPI_MEM_S_FMEM_PMS3_ADDR_S, + * SPI_MEM_S_FMEM_PMS3_ADDR_S + SPI_MEM_S_FMEM_PMS3_SIZE) */ #define SPI_MEM_S_FMEM_PMS3_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS3_SIZE_M (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S) @@ -1777,123 +2099,215 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS3_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130) /** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS0_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS0_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_MEM_S_SMEM_PMS0_ADDR_REG + * and SPI_MEM_S_SMEM_PMS0_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS0_ECC_M (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S) #define SPI_MEM_S_SMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 0 is configured by registers + * SPI_MEM_S_SMEM_PMS0_ADDR_REG and SPI_MEM_S_SMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS1_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134) /** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS1_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS1_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_MEM_S_SMEM_PMS1_ADDR_REG + * and SPI_MEM_S_SMEM_PMS1_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS1_ECC_M (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S) #define SPI_MEM_S_SMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 1 is configured by registers + * SPI_MEM_S_SMEM_PMS1_ADDR_REG and SPI_MEM_S_SMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS2_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138) /** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS2_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS2_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_MEM_S_SMEM_PMS2_ADDR_REG + * and SPI_MEM_S_SMEM_PMS2_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS2_ECC_M (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S) #define SPI_MEM_S_SMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 2 is configured by registers + * SPI_MEM_S_SMEM_PMS2_ADDR_REG and SPI_MEM_S_SMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS3_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c) /** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS3_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS3_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_MEM_S_SMEM_PMS3_ADDR_REG + * and SPI_MEM_S_SMEM_PMS3_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS3_ECC_M (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S) #define SPI_MEM_S_SMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 3 is configured by registers + * SPI_MEM_S_SMEM_PMS3_ADDR_REG and SPI_MEM_S_SMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS0_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 0 start address register */ #define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140) /** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; - * SPI1 external RAM PMS section $n start address value + * SPI1 external RAM PMS section 0 start address value */ #define SPI_MEM_S_SMEM_PMS0_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS0_ADDR_S_M (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S) @@ -1901,11 +2315,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS0_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS1_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 1 start address register */ #define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144) -/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value */ #define SPI_MEM_S_SMEM_PMS1_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS1_ADDR_S_M (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S) @@ -1913,11 +2327,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS1_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS2_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 2 start address register */ #define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148) -/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value */ #define SPI_MEM_S_SMEM_PMS2_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS2_ADDR_S_M (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S) @@ -1925,11 +2339,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS2_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS3_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 3 start address register */ #define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c) -/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value */ #define SPI_MEM_S_SMEM_PMS3_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS3_ADDR_S_M (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S) @@ -1937,12 +2351,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS3_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS0_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 0 start address register */ #define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150) /** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 0 address region is (SPI_MEM_S_SMEM_PMS0_ADDR_S, + * SPI_MEM_S_SMEM_PMS0_ADDR_S + SPI_MEM_S_SMEM_PMS0_SIZE) */ #define SPI_MEM_S_SMEM_PMS0_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS0_SIZE_M (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S) @@ -1950,12 +2364,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS0_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS1_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 1 start address register */ #define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154) /** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 1 address region is (SPI_MEM_S_SMEM_PMS1_ADDR_S, + * SPI_MEM_S_SMEM_PMS1_ADDR_S + SPI_MEM_S_SMEM_PMS1_SIZE) */ #define SPI_MEM_S_SMEM_PMS1_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS1_SIZE_M (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S) @@ -1963,12 +2377,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS1_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS2_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 2 start address register */ #define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158) /** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 2 address region is (SPI_MEM_S_SMEM_PMS2_ADDR_S, + * SPI_MEM_S_SMEM_PMS2_ADDR_S + SPI_MEM_S_SMEM_PMS2_SIZE) */ #define SPI_MEM_S_SMEM_PMS2_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS2_SIZE_M (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S) @@ -1976,12 +2390,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS2_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS3_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 3 start address register */ #define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c) /** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 3 address region is (SPI_MEM_S_SMEM_PMS3_ADDR_S, + * SPI_MEM_S_SMEM_PMS3_ADDR_S + SPI_MEM_S_SMEM_PMS3_SIZE) */ #define SPI_MEM_S_SMEM_PMS3_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS3_SIZE_M (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S) @@ -2053,7 +2467,8 @@ extern "C" { #define SPI_MEM_S_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_S_ECC_ERR_CNT_S 5 /** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT + * interrupt. */ #define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM 0x0000003FU #define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S) @@ -2940,8 +3355,8 @@ extern "C" { #define SPI_MEM_S_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_S_SMEM_CS_HOLD_TIME_S 7 /** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ #define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S) @@ -2965,8 +3380,8 @@ extern "C" { #define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S 16 /** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ #define SPI_MEM_S_SMEM_CS_HOLD_DELAY 0x0000003FU #define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S) @@ -3305,14 +3720,14 @@ extern "C" { * Manual Encryption physical address register */ #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348) -/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ -#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M (SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S) -#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S 0 /** SPI_MEM_S_XTS_TRIGGER_REG register @@ -3376,7 +3791,7 @@ extern "C" { * Manual Encryption version register */ #define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c) -/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; +/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ #define SPI_MEM_S_XTS_DATE 0x3FFFFFFFU @@ -3434,6 +3849,13 @@ extern "C" { #define SPI_MEM_S_MMU_MEM_FORCE_PU_M (SPI_MEM_S_MMU_MEM_FORCE_PU_V << SPI_MEM_S_MMU_MEM_FORCE_PU_S) #define SPI_MEM_S_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MEM_S_MMU_MEM_FORCE_PU_S 2 +/** SPI_MEM_S_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MEM_S_MMU_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_MMU_PAGE_SIZE_M (SPI_MEM_S_MMU_PAGE_SIZE_V << SPI_MEM_S_MMU_PAGE_SIZE_S) +#define SPI_MEM_S_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_MMU_PAGE_SIZE_S 3 /** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ @@ -3443,6 +3865,7 @@ extern "C" { #define SPI_MEM_S_AUX_CTRL_S 16 /** SPI_MEM_S_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_RDN_ENA (BIT(30)) #define SPI_MEM_S_RDN_ENA_M (SPI_MEM_S_RDN_ENA_V << SPI_MEM_S_RDN_ENA_S) @@ -3450,6 +3873,7 @@ extern "C" { #define SPI_MEM_S_RDN_ENA_S 30 /** SPI_MEM_S_RDN_RESULT : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_RDN_RESULT (BIT(31)) #define SPI_MEM_S_RDN_RESULT_M (SPI_MEM_S_RDN_RESULT_V << SPI_MEM_S_RDN_RESULT_S) @@ -3487,12 +3911,51 @@ extern "C" { #define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U #define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S 4 +/** SPI_MEM_S_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_S_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_PSRAM_MSPI0_BASE + 0x38c) +/** SPI_MEM_S_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_S_MODE_PSEUDO 0x00000003U +#define SPI_MEM_S_MODE_PSEUDO_M (SPI_MEM_S_MODE_PSEUDO_V << SPI_MEM_S_MODE_PSEUDO_S) +#define SPI_MEM_S_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_S_MODE_PSEUDO_S 0 +/** SPI_MEM_S_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_S_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_S_PSEUDO_RNG_CNT_M (SPI_MEM_S_PSEUDO_RNG_CNT_V << SPI_MEM_S_PSEUDO_RNG_CNT_S) +#define SPI_MEM_S_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_S_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_S_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_S_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_S_PSEUDO_BASE_M (SPI_MEM_S_PSEUDO_BASE_V << SPI_MEM_S_PSEUDO_BASE_S) +#define SPI_MEM_S_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_S_PSEUDO_BASE_S 5 +/** SPI_MEM_S_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_S_PSEUDO_INC 0x00000003U +#define SPI_MEM_S_PSEUDO_INC_M (SPI_MEM_S_PSEUDO_INC_V << SPI_MEM_S_PSEUDO_INC_S) +#define SPI_MEM_S_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_S_PSEUDO_INC_S 9 + /** SPI_MEM_S_REGISTERRND_ECO_HIGH_REG register * MSPI ECO high register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_REGISTERRND_ECO_HIGH_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f0) /** SPI_MEM_S_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_REGISTERRND_ECO_HIGH 0xFFFFFFFFU #define SPI_MEM_S_REGISTERRND_ECO_HIGH_M (SPI_MEM_S_REGISTERRND_ECO_HIGH_V << SPI_MEM_S_REGISTERRND_ECO_HIGH_S) @@ -3501,10 +3964,13 @@ extern "C" { /** SPI_MEM_S_REGISTERRND_ECO_LOW_REG register * MSPI ECO low register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_REGISTERRND_ECO_LOW_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f4) /** SPI_MEM_S_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_REGISTERRND_ECO_LOW 0xFFFFFFFFU #define SPI_MEM_S_REGISTERRND_ECO_LOW_M (SPI_MEM_S_REGISTERRND_ECO_LOW_V << SPI_MEM_S_REGISTERRND_ECO_LOW_S) @@ -3515,7 +3981,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc) -/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704; +/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 38801984; * SPI0 register version. */ #define SPI_MEM_S_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h index 05386290ac7..235cd5d7aa5 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h @@ -180,11 +180,7 @@ typedef union { * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; + uint32_t reserved_23:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -200,9 +196,9 @@ typedef union { */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When spi_mem_s_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -287,12 +283,24 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:7; - /** mem_fsub_pin : R/W; bitpos: [7]; default: 0; + uint32_t reserved_0:4; + /** mem_dq_oe_ctrl : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ + uint32_t mem_dq_oe_ctrl:1; + /** mem_ck_oe_ctrl : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ + uint32_t mem_ck_oe_ctrl:1; + /** mem_cs_oe_ctrl : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ + uint32_t mem_cs_oe_ctrl:1; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : R/W; bitpos: [8]; default: 0; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ uint32_t mem_ssub_pin:1; @@ -316,47 +324,81 @@ typedef union { struct { /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_axi_req_en:1; /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_addr_4byte:1; /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_flash_usr_cmd:1; /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_dual:1; /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_dual:1; /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_dual:1; /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_quad:1; /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_quad:1; /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_quad:1; - uint32_t reserved_9:21; + /** mem_arb_wei_en : R/W; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ + uint32_t mem_arb_wei_en:1; + /** mem_arb_req0_pri : R/W; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t mem_arb_req0_pri:1; + /** mem_arb_req1_pri : R/W; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t mem_arb_req1_pri:1; + /** mem_arb_req0_wei : R/W; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t mem_arb_req0_wei:4; + /** mem_arb_req1_wei : R/W; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t mem_arb_req1_wei:4; + uint32_t reserved_20:10; /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -462,16 +504,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_s_clkcnt_N. + * In the master mode it must be equal to spi_mem_s_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((spi_mem_s_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is - * system/(spi_mem_s_clkcnt_N+1) + * system/(spi_mem_s_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -490,22 +532,26 @@ typedef union { typedef union { struct { /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_s_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to spi_mem_s_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((spi_mem_s_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk - * frequency is system/(spi_mem_s_clkcnt_N+1) + * frequency is system/(spi_mem_s_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; uint32_t reserved_24:7; /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_equ_sysclk:1; }; @@ -544,7 +590,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with spi_mem_s_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -611,6 +657,7 @@ typedef union { uint32_t reserved_0:16; /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_s_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_wb_mode:8; uint32_t reserved_24:8; @@ -628,52 +675,63 @@ typedef union { /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_saddr_4byte:1; /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_dio:1; /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_qio:1; /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_wr_sram_dummy:1; /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_rd_sram_dummy:1; /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rcmd:1; /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_rdummy_cyclelen:6; uint32_t reserved_12:2; /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_addr_bitlen:6; /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wcmd:1; /** mem_sram_oct : R/W; bitpos: [21]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_oct:1; /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_wdummy_cyclelen:6; uint32_t reserved_28:4; @@ -690,73 +748,88 @@ typedef union { * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_mode:2; /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_s_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_swb_mode:8; /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_dual:1; /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_dual:1; /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_dual:1; uint32_t reserved_13:1; /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_quad:1; /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_quad:1; /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_quad:1; /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_quad:1; /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_oct:1; /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_oct:1; /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_oct:1; /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_oct:1; /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_rin:1; /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_wout:1; /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; @@ -771,10 +844,12 @@ typedef union { uint32_t smem_wdummy_always_out:1; /** mem_sdin_hex : R/W; bitpos: [26]; default: 0; * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_hex:1; /** mem_sdout_hex : R/W; bitpos: [27]; default: 0; * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_hex:1; uint32_t reserved_28:2; @@ -800,12 +875,14 @@ typedef union { /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_value:16; uint32_t reserved_16:12; /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; }; @@ -820,12 +897,14 @@ typedef union { /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_value:16; uint32_t reserved_16:12; /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; }; @@ -877,7 +956,7 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in spi_mem_s_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -942,7 +1021,7 @@ typedef union { */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * spi_mem_s_smem_CS_HOLD_TIME + spi_mem_s_smem_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; @@ -959,7 +1038,7 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (spi_mem_s_smem_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; @@ -981,11 +1060,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t mem_lock_delay_time:12; + uint32_t reserved_19:13; }; uint32_t val; } spi_mem_s_fsm_reg_t; @@ -1026,9 +1105,17 @@ typedef union { * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_ena:1; + /** mem_tx_trans_udf_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_ena:1; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + * The enable bit for spi_mem_s_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_ena:1; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; @@ -1081,7 +1168,15 @@ typedef union { * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_clr : WT; bitpos: [26]; default: 0; + * The clear bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_clr:1; + /** mem_tx_trans_udf_int_clr : WT; bitpos: [27]; default: 0; + * The clear bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_clr:1; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1152,7 +1247,17 @@ typedef union { * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx fifo + * to spi bus is overrflow. + */ + uint32_t mem_rx_trans_ovf_int_raw:1; + /** mem_tx_trans_udf_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ + uint32_t mem_tx_trans_udf_int_raw:1; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. @@ -1211,7 +1316,15 @@ typedef union { * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_st : RO; bitpos: [26]; default: 0; + * The status bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_st:1; + /** mem_tx_trans_udf_int_st : RO; bitpos: [27]; default: 0; + * The status bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_st:1; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1233,62 +1346,175 @@ typedef union { } spi_mem_s_int_st_reg_t; +/** Group: DLL debug and configuration registers */ +/** Type of mem_dll_dly_db register + * MSPI DLL function and debug configuration register + */ +typedef union { + struct { + /** mem_dll_db_cfg_vld_cnt : R/W; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ + uint32_t mem_dll_db_cfg_vld_cnt:8; + /** mem_dll_db_cnt_mode_sel : R/W; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ + uint32_t mem_dll_db_cnt_mode_sel:4; + /** mem_dll_db_cnt_clr : R/W; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ + uint32_t mem_dll_db_cnt_clr:1; + /** mem_dll_din_dly_sel : R/W; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ + uint32_t mem_dll_din_dly_sel:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} spi_mem_s_dll_dly_db_reg_t; + + +/** Group: DLL debug status registers */ +/** Type of mem_dll_db_st0 register + * MSPI DLL debug status0 register + */ +typedef union { + struct { + /** mem_db_fifo_cnt_h : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ + uint32_t mem_db_fifo_cnt_h:32; + }; + uint32_t val; +} spi_mem_s_dll_db_st0_reg_t; + +/** Type of mem_dll_db_st1 register + * MSPI DLL debug status1 register + */ +typedef union { + struct { + /** mem_db_fifo_cnt_l : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ + uint32_t mem_db_fifo_cnt_l:32; + }; + uint32_t val; +} spi_mem_s_dll_db_st1_reg_t; + + /** Group: PMS control and configuration registers */ -/** Type of fmem_pmsn_attr register +/** Type of fmem_pms0_attr register * MSPI flash PMS section $n attribute register */ typedef union { struct { - /** fmem_pms_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + /** fmem_pms0_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ - uint32_t fmem_pms_rd_attr:1; - /** fmem_pms_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + uint32_t fmem_pms0_rd_attr:1; + /** fmem_pms0_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. */ - uint32_t fmem_pms_wr_attr:1; - /** fmem_pms_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + uint32_t fmem_pms0_wr_attr:1; + /** fmem_pms0_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and + * spi_mem_s_fmem_PMS0_SIZE_REG. */ - uint32_t fmem_pms_ecc:1; - uint32_t reserved_3:29; + uint32_t fmem_pms0_ecc:1; + /** fmem_pms0_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_nonsecure_rd_attr:1; + /** fmem_pms0_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_nonsecure_wr_attr:1; + /** fmem_pms0_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and + * spi_mem_s_fmem_PMS0_SIZE_REG. + */ + uint32_t fmem_pms0_nonsecure_ecc:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_mem_s_fmem_pms0_attr_reg_t; + +/** Type of fmem_pmsn_attr register + * SPI1 flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and + * spi_mem_s_fmem_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + /** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_rd_attr:1; + /** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_wr_attr:1; + /** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and + * spi_mem_s_fmem_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_s_fmem_pmsn_attr_reg_t; /** Type of fmem_pmsn_addr register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section n start address register */ typedef union { struct { - /** fmem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; - * SPI1 flash PMS section $n start address value + /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section n start address value */ - uint32_t fmem_pms_addr_s:27; + uint32_t fmem_pmsn_addr_s:27; uint32_t reserved_27:5; }; uint32_t val; } spi_mem_s_fmem_pmsn_addr_reg_t; /** Type of fmem_pmsn_size register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section n start address register */ typedef union { struct { - /** fmem_pms_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section n address region is (spi_mem_s_fmem_PMSn_ADDR_S, + * spi_mem_s_fmem_PMSn_ADDR_S + spi_mem_s_fmem_PMSn_SIZE) */ - uint32_t fmem_pms_size:15; + uint32_t fmem_pmsn_size:15; uint32_t reserved_15:17; }; uint32_t val; } spi_mem_s_fmem_pmsn_size_reg_t; /** Type of smem_pmsn_attr register - * SPI1 flash PMS section $n start address register + * SPI1 external RAM PMS section n attribute register */ typedef union { struct { @@ -1306,18 +1532,32 @@ typedef union { * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. */ uint32_t smem_pms_ecc:1; - uint32_t reserved_3:29; + /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_rd_attr:1; + /** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_wr_attr:1; + /** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section n is configured by registers + * spi_mem_s_smem_PMSn_ADDR_REG and spi_mem_s_smem_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_s_smem_pmsn_attr_reg_t; /** Type of smem_pmsn_addr register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; - * SPI1 external RAM PMS section $n start address value + /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section n start address value */ uint32_t smem_pms_addr_s:27; uint32_t reserved_27:5; @@ -1326,7 +1566,7 @@ typedef union { } spi_mem_s_smem_pmsn_addr_reg_t; /** Type of smem_pmsn_size register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section n start address register */ typedef union { struct { @@ -1347,7 +1587,7 @@ typedef union { struct { /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_reject_addr:27; /** mem_pm_en : R/W; bitpos: [27]; default: 0; @@ -1356,22 +1596,22 @@ typedef union { uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; @@ -1388,11 +1628,11 @@ typedef union { uint32_t reserved_0:5; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + * spi_mem_s_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI spi_mem_s_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; @@ -1416,9 +1656,9 @@ typedef union { uint32_t mem_usr_ecc_addr_en:1; uint32_t reserved_22:2; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and - * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in spi_mem_s_ECC_ERR_BITS and spi_mem_s_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: spi_mem_s_ECC_ERR_BITS and + * spi_mem_s_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; @@ -1437,7 +1677,7 @@ typedef union { struct { /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + * spi_mem_s_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_addr:27; uint32_t reserved_27:5; @@ -2279,13 +2519,13 @@ typedef union { */ typedef union { struct { - /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ - uint32_t xts_physical_address:26; - uint32_t reserved_26:6; + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; }; uint32_t val; } spi_mem_s_xts_physical_address_reg_t; @@ -2364,7 +2604,7 @@ typedef union { */ typedef union { struct { - /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ uint32_t xts_date:30; @@ -2421,17 +2661,23 @@ typedef union { * controlled by rtc. */ uint32_t mmu_mem_force_pu:1; - uint32_t reserved_3:13; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ uint32_t mem_aux_ctrl:14; /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_rdn_ena:1; /** mem_rdn_result : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_rdn_result:1; }; @@ -2468,6 +2714,37 @@ typedef union { } spi_mem_s_dpa_ctrl_reg_t; +/** Group: External mem cryption PSEUDO registers */ +/** Type of mem_xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mem_mode_pseudo:2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_base:4; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ + uint32_t mem_pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_s_xts_pseudo_round_conf_reg_t; + + /** Group: ECO registers */ /** Type of mem_registerrnd_eco_high register * MSPI ECO high register @@ -2476,6 +2753,7 @@ typedef union { struct { /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_registerrnd_eco_high:32; }; @@ -2489,6 +2767,7 @@ typedef union { struct { /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_registerrnd_eco_low:32; }; @@ -2502,7 +2781,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36712704; + /** mem_date : R/W; bitpos: [27:0]; default: 38801984; * SPI0 register version. */ uint32_t mem_date:28; @@ -2542,8 +2821,12 @@ typedef struct spi_mem_s_dev_t { uint32_t reserved_0d0; volatile spi_mem_s_ddr_reg_t mem_ddr; volatile spi_mem_s_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; - volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_mem_s_dll_dly_db_reg_t mem_dll_dly_db; + volatile spi_mem_s_dll_db_st0_reg_t mem_dll_db_st0; + volatile spi_mem_s_dll_db_st1_reg_t mem_dll_db_st1; + uint32_t reserved_0e8[6]; + volatile spi_mem_s_fmem_pms0_attr_reg_t fmem_pms0_attr; + volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[3]; volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; @@ -2587,7 +2870,8 @@ typedef struct spi_mem_s_dev_t { volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index; volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl; - uint32_t reserved_38c[25]; + volatile spi_mem_s_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; + uint32_t reserved_390[24]; volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; uint32_t reserved_3f8;