mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
feat(mspi): support 120MHz flash and psram for esp32c61
This commit is contained in:
@@ -675,22 +675,6 @@ config SOC_SPI_MAX_PRE_DIVIDER
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int
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default 8192
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_TIMER_GROUPS
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int
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default 2
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@@ -314,12 +314,6 @@
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_MAX_PRE_DIVIDER 8192
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// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
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@@ -559,22 +559,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -255,11 +255,6 @@
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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@@ -819,22 +819,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -350,11 +350,6 @@
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#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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@@ -1263,26 +1263,14 @@ config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
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bool
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default y
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config SOC_SPI_MEM_FLASH_SUPPORT_HPM
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bool
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default y
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config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -485,13 +485,9 @@
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#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
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#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
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#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
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#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
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#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
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#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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// TODO: [ESP32C5] IDF-8707
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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@@ -1107,18 +1107,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -433,10 +433,6 @@
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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@@ -867,22 +867,14 @@ config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
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bool
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default y
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config SOC_SPI_MEM_FLASH_SUPPORT_HPM
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bool
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default y
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config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -350,12 +350,9 @@
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#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
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#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
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#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
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#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
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#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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@@ -1119,18 +1119,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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@@ -450,10 +450,6 @@
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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@@ -1699,19 +1699,7 @@ config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
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config SOC_SPI_MEM_FLASH_SUPPORT_HPM
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bool
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default y
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@@ -622,10 +622,7 @@
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
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#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
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#define SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT 1
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@@ -759,22 +759,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 1
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@@ -324,10 +324,6 @@
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#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x7FFFFD //23 bit wide reg
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#define SOC_MEMSPI_IS_INDEPENDENT 1
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM (1U) // Number of counter units
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@@ -943,22 +943,6 @@ config SOC_SPI_SCT_CONF_BITLEN_MAX
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hex
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default 0x3FFFA
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config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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bool
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default y
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config SOC_SPIRAM_SUPPORTED
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bool
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default y
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@@ -1447,6 +1431,10 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
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bool
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default y
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config SOC_SPI_MEM_FLASH_SUPPORT_HPM
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bool
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default y
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config SOC_COEX_HW_PTI
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bool
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default y
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@@ -369,11 +369,6 @@
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#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs
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#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg
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#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SPIRAM CAPS ----------------------------------------*/
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#define SOC_SPIRAM_SUPPORTED 1
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#define SOC_SPIRAM_XIP_SUPPORTED 1
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@@ -562,6 +557,8 @@
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#define SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM (1)
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#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
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#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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