From 983a297f1a5be54f516c1ae56cdab0e71107d271 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Thu, 11 Jun 2026 16:22:01 +0800 Subject: [PATCH] fix(regi2c): Fix regi2c for phy testing --- .../esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h | 2 ++ .../esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h | 2 ++ .../esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h | 2 ++ .../esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h | 2 ++ .../esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h | 6 ++++-- 5 files changed, 12 insertions(+), 2 deletions(-) diff --git a/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h index 6b103b0bbbb..6df8f11edc1 100644 --- a/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -12,6 +12,7 @@ #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" #include "soc/pmu_reg.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { @@ -81,6 +82,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { //Enter regi2c reset mode CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + esp_rom_delay_us(1); // 1us delay is recommended by digital design //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); //Release regi2c reset mode, enter work mode diff --git a/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h index 14a50108684..0f32910dbb4 100644 --- a/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -11,6 +11,7 @@ #include "soc/soc.h" #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { @@ -80,6 +81,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { //Enter regi2c reset mode CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + esp_rom_delay_us(1); // 1us delay is recommended by digital design //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); //Release regi2c reset mode, enter work mode diff --git a/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h index 90914c5fe21..3d2629277ea 100644 --- a/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -12,6 +12,7 @@ #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { @@ -81,6 +82,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { //Enter regi2c reset mode CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + esp_rom_delay_us(1); // 1us delay is recommended by digital design //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); //Release regi2c reset mode, enter work mode diff --git a/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h index d54d85165f9..05886a1b03b 100644 --- a/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -12,6 +12,7 @@ #include "soc/lpperi_struct.h" #include "soc/lp_i2c_ana_mst_struct.h" #include "soc/pmu_reg.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { @@ -71,6 +72,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { //Enter regi2c reset mode CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + esp_rom_delay_us(1); // 1us delay is recommended by digital design //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); //Release regi2c reset mode, enter work mode diff --git a/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h index 28574d071a3..5facd87a3b9 100644 --- a/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32s31/include/hal/regi2c_ctrl_ll.h @@ -12,6 +12,7 @@ #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { @@ -72,7 +73,9 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_i2c_sar_periph_enable(void) { - // TODO: IDF-14632, IDF-14744 + //Enter regi2c reset mode + CLEAR_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C); + esp_rom_delay_us(1); // 1us delay is recommended by digital design //Enable REGI2C for SAR_ADC and TSENS SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C); //Release regi2c reset mode, enter work mode @@ -84,7 +87,6 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_i2c_sar_periph_ */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_i2c_sar_periph_disable(void) { - // TODO: IDF-14632, IDF-14744 CLEAR_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C); }