diff --git a/components/esp_hal_security/esp32c5/include/hal/ecc_ll.h b/components/esp_hal_security/esp32c5/include/hal/ecc_ll.h
index b5a5bca2e27..aa8d0738199 100644
--- a/components/esp_hal_security/esp32c5/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32c5/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,11 +48,17 @@ static inline void ecc_ll_reset_register(void)
     PCR.ecdsa_conf.ecdsa_rst_en = 0;
 }
 
+static inline void ecc_ll_clear_force_pd(void)
+{
+    REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+}
+
 static inline void ecc_ll_power_up(void)
 {
     /* Power up the ECC peripheral (default state is power-down) */
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD) == 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32c6/include/hal/ecc_ll.h b/components/esp_hal_security/esp32c6/include/hal/ecc_ll.h
index 264e89958ab..103ac78570a 100644
--- a/components/esp_hal_security/esp32c6/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32c6/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -46,6 +47,7 @@ static inline void ecc_ll_power_up(void)
 {
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD) == 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32c61/include/hal/ecc_ll.h b/components/esp_hal_security/esp32c61/include/hal/ecc_ll.h
index 14c74e53168..717d81a7871 100644
--- a/components/esp_hal_security/esp32c61/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32c61/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -49,9 +50,10 @@ static inline void ecc_ll_reset_register(void)
 
 static inline void ecc_ll_power_up(void)
 {
-    /* Power up the ECC peripheral (default state is power-down) */
+    /* Power up the ECC peripheral (default state is power-up) */
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD) == 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32h2/include/hal/ecc_ll.h b/components/esp_hal_security/esp32h2/include/hal/ecc_ll.h
index 3ad0a815b78..c3904280287 100644
--- a/components/esp_hal_security/esp32h2/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32h2/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 
@@ -54,6 +55,7 @@ static inline void ecc_ll_power_up(void)
 {
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD) == 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32h21/include/hal/ecc_ll.h b/components/esp_hal_security/esp32h21/include/hal/ecc_ll.h
index 6ac32c21aa4..98bc34e2854 100644
--- a/components/esp_hal_security/esp32h21/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32h21/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,6 +53,7 @@ static inline void ecc_ll_power_up(void)
 {
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
     REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD) == 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32h4/include/hal/ecc_ll.h b/components/esp_hal_security/esp32h4/include/hal/ecc_ll.h
index 1c2e4b91002..5d0c1386e07 100644
--- a/components/esp_hal_security/esp32h4/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32h4/include/hal/ecc_ll.h
@@ -12,6 +12,7 @@
 #include "soc/ecc_mult_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,9 +51,11 @@ static inline void ecc_ll_reset_register(void)
 static inline void ecc_ll_power_up(void)
 {
 
-    /* Power up the ECC peripheral (default state is power-down) */
+    /* Power up the ECC peripheral (default state is power-up) */
     REG_CLR_BIT(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_LP_EN);
-    REG_CLR_BIT(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_FORCE_CTRL);
+    REG_SET_BIT(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_FORCE_CTRL);
+    ESP_FAULT_ASSERT(REG_GET_BIT(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_LP_EN) == 0 &&
+                     REG_GET_BIT(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_FORCE_CTRL) != 0);
 }
 
 static inline void ecc_ll_power_down(void)
diff --git a/components/esp_hal_security/esp32p4/include/hal/ecc_ll.h b/components/esp_hal_security/esp32p4/include/hal/ecc_ll.h
index ab4b65d187d..34a9e98db7f 100644
--- a/components/esp_hal_security/esp32p4/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32p4/include/hal/ecc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,8 +12,10 @@
 #include "hal/efuse_hal.h"
 #include "soc/ecc_mult_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/hp_system_reg.h"
 #include "soc/chip_revision.h"
 #include "hal/config.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -65,8 +67,20 @@ static inline void ecc_ll_reset_register(void)
         ecc_ll_reset_register(__VA_ARGS__); \
     } while(0)
 
-static inline void ecc_ll_power_up(void) {}
-static inline void ecc_ll_power_down(void) {}
+static inline void ecc_ll_power_up(void)
+{
+    /* Power up the ECC peripheral (default state is power-up) */
+    REG_CLR_BIT(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_PD);
+    REG_CLR_BIT(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_FORCE_PD);
+    ESP_FAULT_ASSERT(REG_GET_BIT(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_FORCE_PD) == 0);
+}
+
+static inline void ecc_ll_power_down(void)
+{
+    /* Power down the ECC peripheral */
+    REG_CLR_BIT(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_FORCE_PU);
+    REG_SET_BIT(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_PD);
+}
 
 static inline void ecc_ll_enable_interrupt(void)
 {
diff --git a/components/esp_hal_security/esp32s31/include/hal/ecc_ll.h b/components/esp_hal_security/esp32s31/include/hal/ecc_ll.h
index c23094a77bd..195886e14b4 100644
--- a/components/esp_hal_security/esp32s31/include/hal/ecc_ll.h
+++ b/components/esp_hal_security/esp32s31/include/hal/ecc_ll.h
@@ -11,6 +11,8 @@
 #include "hal/ecc_types.h"
 #include "soc/ecc_mult_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/hp_system_reg.h"
+#include "esp_fault.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -62,8 +64,21 @@ static inline void ecc_ll_reset_register(void)
         ecc_ll_reset_register(__VA_ARGS__); \
     } while(0)
 
-static inline void ecc_ll_power_up(void) {}
-static inline void ecc_ll_power_down(void) {}
+static inline void ecc_ll_power_up(void)
+{
+    /* Power up the ECC peripheral (default state is power-up) */
+    REG_CLR_BIT(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN);
+    REG_SET_BIT(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL);
+    /* Anti-FI: confirm the clears took effect. */
+    ESP_FAULT_ASSERT(REG_GET_BIT(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN) == 0 &&
+                     REG_GET_BIT(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL) != 0);
+}
+
+static inline void ecc_ll_power_down(void)
+{
+    /* Power down the ECC peripheral */
+    REG_SET_BIT(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN);
+}
 
 static inline void ecc_ll_enable_interrupt(void)
 {
diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c
index 1ab861d269c..d1a00ba93ca 100644
--- a/components/esp_system/port/soc/esp32c5/system_internal.c
+++ b/components/esp_system/port/soc/esp32c5/system_internal.c
@@ -99,6 +99,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c
index a5391a5c3f9..17ffd0df04f 100644
--- a/components/esp_system/port/soc/esp32c6/system_internal.c
+++ b/components/esp_system/port/soc/esp32c6/system_internal.c
@@ -83,6 +83,8 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
+
     CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c
index 5e703bc3927..dec09f88be9 100644
--- a/components/esp_system/port/soc/esp32c61/system_internal.c
+++ b/components/esp_system/port/soc/esp32c61/system_internal.c
@@ -100,6 +100,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
index 41140f44226..6a471aff8ff 100644
--- a/components/esp_system/port/soc/esp32h2/system_internal.c
+++ b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -82,6 +82,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c
index d39606dbeee..b519f67a75b 100644
--- a/components/esp_system/port/soc/esp32h21/system_internal.c
+++ b/components/esp_system/port/soc/esp32h21/system_internal.c
@@ -85,6 +85,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c
index 9b765e5843a..98cb5570e9c 100644
--- a/components/esp_system/port/soc/esp32h4/system_internal.c
+++ b/components/esp_system/port/soc/esp32h4/system_internal.c
@@ -85,6 +85,8 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_LP_EN);
+    SET_PERI_REG_MASK(PCR_ECC_MEM_LP_CTRL_REG, PCR_ECC_MEM_FORCE_CTRL);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c
index 5456d680631..a310fa296c7 100644
--- a/components/esp_system/port/soc/esp32p4/system_internal.c
+++ b/components/esp_system/port/soc/esp32p4/system_internal.c
@@ -131,6 +131,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
     CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_RSA);
     CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_SHA);
+    CLEAR_PERI_REG_MASK(HP_SYSTEM_ECC_PD_CTRL_REG, HP_SYSTEM_ECC_MEM_FORCE_PD);
 
 #if CONFIG_ESP32P4_REV_MIN_FULL < 101
     if (efuse_hal_chip_revision() < 101) {
diff --git a/components/esp_system/port/soc/esp32s31/system_internal.c b/components/esp_system/port/soc/esp32s31/system_internal.c
index 470bd516425..2da0d2b1275 100644
--- a/components/esp_system/port/soc/esp32s31/system_internal.c
+++ b/components/esp_system/port/soc/esp32s31/system_internal.c
@@ -48,6 +48,9 @@ void esp_system_reset_modules_on_exit(void)
             esp_rom_output_tx_wait_idle(i);
         }
     }
+
+    CLEAR_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN);
+    SET_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL);
 }
 
 static void IRAM_ATTR __attribute__((noinline, noreturn)) esp_restart_noos_inner(void)
diff --git a/components/mbedtls/port/psa_driver/esp_ecdsa/psa_crypto_driver_esp_ecdsa.c b/components/mbedtls/port/psa_driver/esp_ecdsa/psa_crypto_driver_esp_ecdsa.c
index 911e8d241c9..eed84dce00d 100644
--- a/components/mbedtls/port/psa_driver/esp_ecdsa/psa_crypto_driver_esp_ecdsa.c
+++ b/components/mbedtls/port/psa_driver/esp_ecdsa/psa_crypto_driver_esp_ecdsa.c
@@ -18,6 +18,7 @@
 #include "mbedtls/bignum.h"
 
 #include "esp_assert.h"
+#include "esp_fault.h"
 #include "esp_crypto_lock.h"
 #include "esp_crypto_periph_clk.h"
 
@@ -353,13 +354,22 @@ static psa_status_t check_ecdsa_signature_range(const uint8_t *signature, size_t
         goto cleanup;
     }
 
-    /* 1 <= scalar <= n-1: equivalently scalar > 0 and scalar < n. */
-    if (mbedtls_mpi_cmp_int(&r, 0) <= 0 ||
-        mbedtls_mpi_cmp_mpi(&r, &grp.N) >= 0 ||
-        mbedtls_mpi_cmp_int(&s, 0) <= 0 ||
-        mbedtls_mpi_cmp_mpi(&s, &grp.N) >= 0) {
+    /* 1 <= scalar <= n-1: that is, scalar > 0 and scalar < n. */
+    #define RANGE_OK   0x6A6A6A6AU
+    #define RANGE_FAIL 0x95959595U
+    volatile uint32_t verdict = RANGE_FAIL;
+    if (mbedtls_mpi_cmp_int(&r, 0) > 0 &&
+        mbedtls_mpi_cmp_mpi(&r, &grp.N) < 0 &&
+        mbedtls_mpi_cmp_int(&s, 0) > 0 &&
+        mbedtls_mpi_cmp_mpi(&s, &grp.N) < 0) {
+        verdict = RANGE_OK;
+    }
+    if (verdict != RANGE_OK) {
         goto cleanup;
     }
+    ESP_FAULT_ASSERT(verdict == RANGE_OK);
+    #undef RANGE_OK
+    #undef RANGE_FAIL
 
     status = PSA_SUCCESS;
 
@@ -562,6 +572,8 @@ psa_status_t esp_ecdsa_transparent_verify_hash_complete(esp_ecdsa_transparent_ve
         return PSA_ERROR_INVALID_SIGNATURE;
     }
 
+    ESP_FAULT_ASSERT(ret == 0);
+
     return PSA_SUCCESS;
 }
 
diff --git a/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_ecdsa.c b/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_ecdsa.c
index 08794629ba5..f7c22646dd5 100644
--- a/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_ecdsa.c
+++ b/components/mbedtls/test_apps/mbedtls_ut/main/test_psa_ecdsa.c
@@ -10,6 +10,9 @@
 #include <inttypes.h>
 #include <esp_log.h>
 
+#define MBEDTLS_DECLARE_PRIVATE_IDENTIFIERS
+#include "mbedtls/private/ecp.h"
+#include "mbedtls/private/bignum.h"
 #include "psa/crypto.h"
 #include "psa_crypto_driver_esp_ecdsa_contexts.h"
 #include "psa_crypto_driver_esp_ecdsa.h"
@@ -334,6 +337,16 @@ TEST_CASE("mbedtls ECDSA signature verification performance on SECP384R1", "[mbe
 #define ECDSA_RANGE_CHECK_REJECT_STATUS  PSA_ERROR_INVALID_SIGNATURE
 #endif
 
+/* Curve order N in big-endian, taken from mbedtls instead of a hard-coded table. */
+static void ecdsa_get_curve_order_be(mbedtls_ecp_group_id id, uint8_t *n_be, size_t len)
+{
+    mbedtls_ecp_group grp;
+    mbedtls_ecp_group_init(&grp);
+    TEST_ASSERT_EQUAL(0, mbedtls_ecp_group_load(&grp, id));
+    TEST_ASSERT_EQUAL(0, mbedtls_mpi_write_binary(&grp.N, n_be, len));
+    mbedtls_ecp_group_free(&grp);
+}
+
 TEST_CASE("mbedtls ECDSA signature verification rejects out-of-range r, s on SECP256R1", "[mbedtls]")
 {
 #if SOC_ECDSA_SUPPORTED
@@ -341,24 +354,17 @@ TEST_CASE("mbedtls ECDSA signature verification rejects out-of-range r, s on SEC
         TEST_IGNORE_MESSAGE("ECDSA is not supported");
     }
 #endif
-    /* Case A: r = 0, s = 0 -- caught by 'r > 0' / 's > 0' check. */
     static const uint8_t zero32[32] = { 0 };
-    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha,
-                      zero32, zero32,
-                      ecdsa256_pub_x, ecdsa256_pub_y,
-                      ECDSA_RANGE_CHECK_REJECT_STATUS);
+    uint8_t p256_n_be[32];
+    ecdsa_get_curve_order_be(MBEDTLS_ECP_DP_SECP256R1, p256_n_be, sizeof(p256_n_be));
 
-    /* Case B: r = N (SECP256R1 curve order), s = valid -- caught by 'r < N' check. */
-    static const uint8_t p256_n_be[32] = {
-        0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-        0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84,
-        0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51,
-    };
-    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha,
-                      p256_n_be, ecdsa256_s,
-                      ecdsa256_pub_x, ecdsa256_pub_y,
-                      ECDSA_RANGE_CHECK_REJECT_STATUS);
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, zero32, zero32,       ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=0, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, zero32, p256_n_be,    ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=0, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, p256_n_be, zero32,    ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, p256_n_be, p256_n_be, ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, ecdsa256_r, zero32,    ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=valid, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, ecdsa256_r, p256_n_be, ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=valid, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP256R1, sha, p256_n_be, ecdsa256_s, ecdsa256_pub_x, ecdsa256_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=valid */
 }
 
 #ifdef SOC_ECDSA_SUPPORT_CURVE_P384
@@ -369,26 +375,17 @@ TEST_CASE("mbedtls ECDSA signature verification rejects out-of-range r, s on SEC
         TEST_IGNORE_MESSAGE("ECDSA is not supported");
     }
 #endif
-    /* Case A: r = 0, s = 0 */
     static const uint8_t zero48[48] = { 0 };
-    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha,
-                      zero48, zero48,
-                      ecdsa384_pub_x, ecdsa384_pub_y,
-                      ECDSA_RANGE_CHECK_REJECT_STATUS);
+    uint8_t p384_n_be[48];
+    ecdsa_get_curve_order_be(MBEDTLS_ECP_DP_SECP384R1, p384_n_be, sizeof(p384_n_be));
 
-    /* Case B: r = N (SECP384R1 curve order), s = valid */
-    static const uint8_t p384_n_be[48] = {
-        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-        0xc7, 0x63, 0x4d, 0x81, 0xf4, 0x37, 0x2d, 0xdf,
-        0x58, 0x1a, 0x0d, 0xb2, 0x48, 0xb0, 0xa7, 0x7a,
-        0xec, 0xec, 0x19, 0x6a, 0xcc, 0xc5, 0x29, 0x73,
-    };
-    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha,
-                      p384_n_be, ecdsa384_s,
-                      ecdsa384_pub_x, ecdsa384_pub_y,
-                      ECDSA_RANGE_CHECK_REJECT_STATUS);
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, zero48, zero48,       ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=0, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, zero48, p384_n_be,    ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=0, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, p384_n_be, zero48,    ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, p384_n_be, p384_n_be, ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, ecdsa384_r, zero48,    ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=valid, s=0 */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, ecdsa384_r, p384_n_be, ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=valid, s=N */
+    test_ecdsa_verify(ESP_ECDSA_CURVE_SECP384R1, sha, p384_n_be, ecdsa384_s, ecdsa384_pub_x, ecdsa384_pub_y, ECDSA_RANGE_CHECK_REJECT_STATUS); /* r=N, s=valid */
 }
 #endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */