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refactor(dac): rename LL APIs and introduce sintx manager

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This commit is contained in:
Hu Rui
2026-09-17 15:35:58 +08:00
parent a8a5106421
commit 550734e7dc
12 changed files with 520 additions and 303 deletions
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components/esp_hal_ana_conv/adc_oneshot_hal.c
+6 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -181,25 +181,25 @@ static void s_disable_dac(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel)
* If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*/
if (hal->unit == ADC_UNIT_1) {
dac_ll_rtc_sync_by_adc(false);
dac_ll_sync_by_adc(false);
}
#if SOC_IS(ESP32)
if (hal->unit == ADC_UNIT_2) {
if (channel == ADC_CHANNEL_8) {
dac_ll_power_down(DAC_CHAN_0); // the same as DAC channel 0
dac_ll_pad_power_down(DAC_CHAN_0); // the same as DAC channel 0
}
if (channel == ADC_CHANNEL_9) {
dac_ll_power_down(DAC_CHAN_1);
dac_ll_pad_power_down(DAC_CHAN_1);
}
}
#elif SOC_IS(ESP32S2)
if (hal->unit == ADC_UNIT_2) {
if (channel == ADC_CHANNEL_6) {
dac_ll_power_down(DAC_CHAN_0); // the same as DAC channel 0
dac_ll_pad_power_down(DAC_CHAN_0); // the same as DAC channel 0
}
if (channel == ADC_CHANNEL_7) {
dac_ll_power_down(DAC_CHAN_1);
dac_ll_pad_power_down(DAC_CHAN_1);
}
}
#else
components/esp_hal_ana_conv/esp32/include/hal/dac_ll.h
+71 -65
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,56 +19,84 @@
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "hal/dac_types.h"
#include "hal/dac_types_private.h"
#define SOC_DAC_DC_VIA_SINTX 0
#define SOC_DAC_SINTX_HAS_TIMER_TARGET 0
#define SOC_DAC_SINTX_LUT_SIGNED 0
#ifdef __cplusplus
extern "C" {
#endif
#define DAC_LL_CW_PHASE_0 0x02
#define DAC_LL_CW_PHASE_180 0x03
/*---------------------------------------------------------------
DAC pad setting
---------------------------------------------------------------*/
/**
* Power on dac module and start output voltage.
* @brief Power on the DAC pad and start outputting voltage.
*
* @note Before powering up, make sure the DAC PAD is set to RTC PAD and floating status.
* @param channel DAC channel num.
*/
static inline void dac_ll_power_on(dac_channel_t channel)
static inline void dac_ll_pad_power_on(dac_channel_t channel)
{
RTCIO.pad_dac[channel].dac_xpd_force = 1;
RTCIO.pad_dac[channel].xpd_dac = 1;
}
/**
* Power done dac module and stop output voltage.
* @brief Power down the DAC pad and stop outputting voltage.
*
* @param channel DAC channel num.
*/
static inline void dac_ll_power_down(dac_channel_t channel)
static inline void dac_ll_pad_power_down(dac_channel_t channel)
{
RTCIO.pad_dac[channel].dac_xpd_force = 0;
RTCIO.pad_dac[channel].xpd_dac = 0;
}
/**
* Output voltage with value (8 bit).
* @brief Select the internal data source that drives a DAC channel output.
*
* @note Since dac_dig_force is shared between the two channels, either both channels must use DMA as their data source, or neither can.
* @note When selecting the DMA source, the DAC output data comes from the I2S DMA.
*
* @param channel DAC channel num.
* @param value Output value. Value range: 0 ~ 255.
* The corresponding range of voltage is 0v ~ VDD3P3_RTC.
* @param source Data source, see `dac_data_source_t`
*/
__attribute__((always_inline))
static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value)
static inline void dac_ll_pad_set_data_source(dac_channel_t channel, dac_data_source_t source)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
if (source == DAC_DATA_SOURCE_DMA) {
SENS.sar_dac_ctrl1.dac_dig_force = true;
} else {
bool cw_en = (source == DAC_DATA_SOURCE_COSINE);
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = cw_en;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = cw_en;
}
SENS.sar_dac_ctrl1.dac_dig_force = false;
}
}
/**
* @brief Set the DAC output code (8 bit).
*
* @param channel DAC channel num.
* @param code Output code. Range: 0 ~ 255.
* The corresponding voltage range is 0 V ~ VDD3P3_RTC.
*/
__attribute__((always_inline))
static inline void dac_ll_pad_set_output_code(dac_channel_t channel, uint8_t code)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, code);
}
/*---------------------------------------------------------------
DAC controller setting
---------------------------------------------------------------*/
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
@@ -76,56 +104,39 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
*
* @param enable Enable or disable adc and dac synchronization function.
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
static inline void dac_ll_sync_by_adc(bool enable)
{
SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable;
}
/************************************/
/* DAC cosine wave generator API's */
/************************************/
/*---------------------------------------------------------------
Cosine wave generator setting
---------------------------------------------------------------*/
/**
* Enable cosine wave generator output.
* @brief Enable the cosine wave generator phase accumulator.
*/
static inline void dac_ll_cw_generator_enable(void)
static inline void dac_ll_cw_enable_tone(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 1;
}
/**
* Disable cosine wave generator output.
* @brief Disable the cosine wave generator
*/
static inline void dac_ll_cw_generator_disable(void)
static inline void dac_ll_cw_disable(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 0;
}
/**
* Enable the cosine wave generator of DAC channel.
* Set the step increment of the cosine wave generator.
*
* @param channel DAC channel num.
* @param enable
* @note cosine wave frequency = (dig_clk_rtc_freq * fstep) / 2^16
*/
static inline void dac_ll_cw_enable_channel(dac_channel_t channel, bool enable)
static inline void dac_ll_cw_set_fstep(uint16_t fstep)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = enable;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = enable;
}
}
/**
* Set frequency of cosine wave generator output.
*
* @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error.
* @param freq_hz CW generator frequency. Range: >= 130Hz, no exact ceiling limitation, but will distort when reach several MHz
* @param rtc8m_freq the calibrated RTC 8M clock frequency
*/
static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
{
uint32_t sw_freq = (uint32_t)(((uint64_t)freq << 16) / rtc8m_freq);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, fstep);
}
/**
@@ -163,38 +174,33 @@ static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cosine_phase_t
}
/**
* Set the voltage value of the DC component of the cosine wave generator output.
* @brief Set the DC offset of the cosine wave generator output.
*
* @note The DC offset setting should be after phase setting.
* @note Unreasonable settings can cause the signal to be oversaturated.
* @note On ESP32, dac_inv also inverts the DC component. The caller must
* compensate (e.g. negate) the offset for 180° phase before calling this.
* @param channel DAC channel num.
* @param offset DC value. Range: -128 ~ 127.
* @param offset DC offset. Range: -128 ~ 127.
*/
static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
static inline void dac_ll_cw_set_offset(dac_channel_t channel, int8_t offset)
{
if (channel == DAC_CHAN_0) {
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset);
} else if (channel == DAC_CHAN_1) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset);
}
}
/************************************/
/* DAC DMA API's */
/************************************/
/*---------------------------------------------------------------
DAC DMA setting
---------------------------------------------------------------*/
/**
* Enable/disable DAC output data from I2S DMA.
* I2S_CLK connect to DAC_CLK, I2S_DATA_OUT connect to DAC_DATA.
* @brief Enable/disable invert the DAC DMA clock signal.
*
* @param enable true to invert, false otherwise
*/
static inline void dac_ll_digi_enable_dma(bool enable)
static inline void dac_ll_dma_clk_inv(bool enable)
{
SENS.sar_dac_ctrl1.dac_dig_force = enable;
SENS.sar_dac_ctrl1.dac_clk_inv = enable;
}
components/esp_hal_ana_conv/esp32s2/include/hal/dac_ll.h
+87 -101
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,28 +17,30 @@
#include "hal/misc.h"
#include "hal/dac_periph.h"
#include "hal/dac_types.h"
#include "hal/dac_types_private.h"
#include "soc/apb_saradc_struct.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/apb_saradc_reg.h"
#define SOC_DAC_DC_VIA_SINTX 0
#define SOC_DAC_SINTX_HAS_TIMER_TARGET 0
#define SOC_DAC_SINTX_LUT_SIGNED 0
#ifdef __cplusplus
extern "C" {
#endif
#define DAC_LL_CW_PHASE_0 0x02
#define DAC_LL_CW_PHASE_180 0x03
/*---------------------------------------------------------------
DAC common setting
DAC pad setting
---------------------------------------------------------------*/
/**
* Power on dac module and start output voltage.
* @brief Power on the DAC pad and start outputting voltage.
*
* @note Before powering up, make sure the DAC PAD is set to RTC PAD and floating status.
* @param channel DAC channel num.
*/
static inline void dac_ll_power_on(dac_channel_t channel)
static inline void dac_ll_pad_power_on(dac_channel_t channel)
{
SENS.sar_dac_ctrl1.dac_clkgate_en = 1;
RTCIO.pad_dac[channel].dac_xpd_force = 1;
@@ -46,11 +48,11 @@ static inline void dac_ll_power_on(dac_channel_t channel)
}
/**
* Power done dac module and stop output voltage.
* @brief Power down the DAC pad and stop outputting voltage.
*
* @param channel DAC channel num.
*/
static inline void dac_ll_power_down(dac_channel_t channel)
static inline void dac_ll_pad_power_down(dac_channel_t channel)
{
RTCIO.pad_dac[channel].dac_xpd_force = 0;
RTCIO.pad_dac[channel].xpd_dac = 0;
@@ -59,32 +61,51 @@ static inline void dac_ll_power_down(dac_channel_t channel)
}
}
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
/**
* Output voltage with value (8 bit).
* @brief Select the internal data source that drives a DAC channel output.
*
* @note Since dac_dig_force is shared between the two channels, either both channels must use DMA as their data source, or neither can.
*
* @param channel DAC channel num.
* @param value Output value. Value range: 0 ~ 255.
* The corresponding range of voltage is 0v ~ VDD3P3_RTC.
* @param source Data source, see `dac_data_source_t`
*/
__attribute__((always_inline))
static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value)
static inline void dac_ll_pad_set_data_source(dac_channel_t channel, dac_data_source_t source)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
if (source == DAC_DATA_SOURCE_DMA) {
SENS.sar_dac_ctrl1.dac_dig_force = true;
APB_SARADC.apb_dac_ctrl.apb_dac_trans = true;
} else {
bool cw_en = (source == DAC_DATA_SOURCE_COSINE);
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = cw_en;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = cw_en;
}
SENS.sar_dac_ctrl1.dac_dig_force = false;
APB_SARADC.apb_dac_ctrl.apb_dac_trans = false;
}
}
/**
* @brief Set the DAC output code (8 bit).
*
* @param channel DAC channel num.
* @param code Output code. Range: 0 ~ 255.
* The corresponding voltage range is 0 V ~ VDD3P3_RTC.
*/
__attribute__((always_inline))
static inline void dac_ll_pad_set_output_code(dac_channel_t channel, uint8_t code)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, code);
}
/*---------------------------------------------------------------
DAC controller setting
---------------------------------------------------------------*/
/**
* Reset dac by software.
*/
static inline void dac_ll_rtc_reset(void)
static inline void dac_ll_reset(void)
{
SENS.sar_dac_ctrl1.dac_reset = 1;
SENS.sar_dac_ctrl1.dac_reset = 0;
@@ -97,56 +118,38 @@ static inline void dac_ll_rtc_reset(void)
*
* @param enable Enable or disable adc and dac synchronization function.
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
static inline void dac_ll_sync_by_adc(bool enable)
{
SENS.sar_amp_ctrl3.sar1_dac_xpd_fsm = enable;
}
/************************************/
/* DAC cosine wave generator API's */
/************************************/
/*---------------------------------------------------------------
DAC cosine wave generator setting
---------------------------------------------------------------*/
/**
* Enable cosine wave generator output.
* @brief Enable the cosine wave generator phase accumulator.
*/
static inline void dac_ll_cw_generator_enable(void)
static inline void dac_ll_cw_enable_tone(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 1;
}
/**
* Disable cosine wave generator output.
* @brief Disable the cosine wave generator
*/
static inline void dac_ll_cw_generator_disable(void)
static inline void dac_ll_cw_disable(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 0;
}
/**
* Enable the cosine wave generator of DAC channel.
* Set the step increment of the cosine wave generator.
*
* @param channel DAC channel num.
* @param enable
* @note cosine wave frequency = (dig_clk_rtc_freq * fstep) / 2^16
*/
static inline void dac_ll_cw_enable_channel(dac_channel_t channel, bool enable)
static inline void dac_ll_cw_set_fstep(uint16_t fstep)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = enable;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_cw_en2 = enable;
}
}
/**
* Set frequency of cosine wave generator output.
*
* @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error.
* @param freq_hz CW generator frequency. Range: >= 130Hz, no exact ceiling limitation, but will distort when reach several MHz
* @param rtc8m_freq the calibrated RTC 8M clock frequency
*/
static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
{
uint32_t sw_freq = (uint32_t)(((uint64_t)freq << 16) / rtc8m_freq);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, fstep);
}
/**
@@ -184,101 +187,84 @@ static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cosine_phase_t
}
/**
* Set the voltage value of the DC component of the cosine wave generator output.
* @brief Set the DC offset of the cosine wave generator output.
*
* @note The DC offset setting should be after phase setting.
* @note Unreasonable settings can cause the signal to be oversaturated.
* @note On ESP32-S2, dac_inv also inverts the DC component. The caller must
* compensate (e.g. negate) the offset for 180° phase before calling this.
* @param channel DAC channel num.
* @param offset DC value. Range: -128 ~ 127.
* @param offset DC offset. Range: -128 ~ 127.
*/
static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
static inline void dac_ll_cw_set_offset(dac_channel_t channel, int8_t offset)
{
if (channel == DAC_CHAN_0) {
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset);
} else if (channel == DAC_CHAN_1) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_LL_CW_PHASE_180) {
offset = -offset;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset);
}
}
/*---------------------------------------------------------------
Digital controller setting
DAC DMA setting
---------------------------------------------------------------*/
/************************************/
/* DAC DMA API's */
/************************************/
/**
* Enable/disable invert the DAC digital controller clock signal.
* @brief Enable/disable invert the DAC DMA clock signal.
*
* @param enable true or false.
* @param enable true to invert, false otherwise
*
* @note On ESP32-S2, when the DAC is driven through DMA, enabling inv_clk is necessary to avoid glitches in the output waveform.
*/
static inline void dac_ll_digi_clk_inv(bool enable)
static inline void dac_ll_dma_clk_inv(bool enable)
{
SENS.sar_dac_ctrl1.dac_clk_inv = enable;
}
/**
* Enable/disable DAC-DMA mode for dac digital controller.
* @brief Set the DMA path timer target.
*
* @note The clocks of the DAC digital controller use the ADC digital controller clock divider.
* @note DMA output frequency = controller_clk / timer_target.
*
* @param timer_target Number of divided-clock cycles between DAC outputs.
*/
static inline void dac_ll_digi_enable_dma(bool enable)
static inline void dac_ll_dma_set_timer_target(uint32_t timer_target)
{
SENS.sar_dac_ctrl1.dac_dig_force = enable;
APB_SARADC.apb_dac_ctrl.apb_dac_trans = enable;
APB_SARADC.apb_dac_ctrl.dac_timer_target = timer_target;
}
/**
* Sets the number of interval clock cycles for the digital controller to trigger the DAC output.
* Expression: `dac_output_freq` = `controller_clk` / interval.
* @brief Enable/disable the DAC DMA output timer.
*
* @note The clocks of the DAC digital controller use the ADC digital controller clock divider.
*
* @param cycle The number of clock cycles for the trigger output interval. The unit is the divided clock.
* @param enable true to enable, false to disable
*/
static inline void dac_ll_digi_set_trigger_interval(uint32_t cycle)
{
APB_SARADC.apb_dac_ctrl.dac_timer_target = cycle;
}
/**
* Enable/disable DAC digital controller to trigger the DAC output.
*
* @param enable true or false.
*/
static inline void dac_ll_digi_trigger_output(bool enable)
static inline void dac_ll_dma_enable_timer(bool enable)
{
APB_SARADC.apb_dac_ctrl.dac_timer_en = enable;
}
/**
* Set DAC conversion mode for digital controller.
* @brief Enable/disable the alternate (ping-pong) output mode of the DMA path.
*
* @param mode Conversion mode select. See ``dac_digi_convert_mode_t``.
* @param enable true to route consecutive samples alternately to the two channels
*/
static inline void dac_ll_digi_set_convert_mode(bool is_alternate)
static inline void dac_ll_dma_enable_alternate_mode(bool enable)
{
APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = is_alternate;
APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = enable;
}
/**
* Reset FIFO of DAC digital controller.
* @brief Reset the DAC DMA FIFO.
*/
static inline void dac_ll_digi_fifo_reset(void)
static inline void dac_ll_dma_reset_fifo(void)
{
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 1;
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 0;
}
/**
* Reset DAC digital controller.
* @brief Reset the DAC DMA FSM, i.e. the DAC-side consumer of DMA samples (timer, alter-mode demux).
*/
static inline void dac_ll_digi_reset(void)
static inline void dac_ll_dma_reset_fsm(void)
{
APB_SARADC.apb_dac_ctrl.apb_dac_rst = 1;
APB_SARADC.apb_dac_ctrl.apb_dac_rst = 0;
components/esp_hal_ana_conv/include/hal/dac_types.h
-9
View File
@@ -15,15 +15,6 @@ extern "C" {
#if SOC_DAC_SUPPORTED
/**
* ESP32:
* - DAC channel 0: GPIO25
* - DAC channel 1: GPIO26
* ESP32S2:
* - DAC channel 0: GPIO17
* - DAC channel 1: GPIO18
*/
typedef enum {
DAC_CHAN_0 = 0,
DAC_CHAN_1 = 1,
components/esp_hal_ana_conv/include/hal/dac_types_private.h
+33
View File
@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_DAC_SUPPORTED
/**
* @brief The internal data source that drives a DAC channel output
*
* @note The number of distinct sources differs per chip:
* - ESP32/ESP32-S2: cosine generator, DMA, and direct register output are three separate states.
* - ESP32-S31: the Sintx path serves both the cosine generator and the direct software output.
*/
typedef enum {
DAC_DATA_SOURCE_COSINE = 0, /*!< Channel output driven by the on-chip cosine wave generator (Sintx) */
DAC_DATA_SOURCE_DMA = 1, /*!< Channel output driven by the digital DMA path */
DAC_DATA_SOURCE_DIRECT = 2, /*!< Channel output driven by the direct register value */
} dac_data_source_t;
#endif // SOC_DAC_SUPPORTED
#ifdef __cplusplus
}
#endif