diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index 2e8df43e161..c197eea497e 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -35,9 +35,6 @@ ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31"); static inline void bootloader_hardware_init(void) { - /* Disable RF pll by default */ - REG_SET_FIELD(PMU_RF_PWC_REG, PMU_XPD_RF_CIRCUIT, 0xFFFF); - modem_lpcon_ll_enable_bus_clock(true); #if !CONFIG_IDF_ENV_FPGA diff --git a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h index e631b3bbfff..15192392543 100644 --- a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h +++ b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h @@ -514,6 +514,25 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu hw->power.mem_cntl.force_hp_mem_pu = fpu; } +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_on_mask(pmu_dev_t *hw, uint32_t mem_mask) +{ + hw->power.mem_mask.mem0_mask = (mem_mask & BIT(0)) ? 0x1F : 0; + hw->power.mem_mask.mem1_mask = (mem_mask & BIT(1)) ? 0x1F : 0; + hw->power.mem_mask.mem2_mask = (mem_mask & BIT(2)) ? 0x1F : 0; + if (mem_mask & BIT(3)) { + hw->power.mem_cntl.force_hp_mem_pu |= (mem_mask & BIT(3)); + } else { + hw->power.mem_cntl.force_hp_mem_pu &= ~(mem_mask & BIT(3)); + } +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_off_mask(pmu_dev_t *hw, uint32_t mem0_pd_mask, uint32_t mem1_pd_mask, uint32_t mem2_pd_mask) +{ + hw->power.mem_mask.mem0_pd_mask = mem0_pd_mask; + hw->power.mem_mask.mem1_pd_mask = mem1_pd_mask; + hw->power.mem_mask.mem2_pd_mask = mem2_pd_mask; +} + FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw) { hw->wakeup.cntl0.sleep_req = 1; @@ -755,12 +774,17 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw) return hw->clk_state0.sysclk_slp_sel; } +FORCE_INLINE_ATTR void pmu_ll_set_rf_power_control(pmu_dev_t *hw, uint16_t val) +{ + hw->hp_ext.rf_pwc.xpd_rf_circuit = val; +} + /** * @brief Get ext1 wakeup source status * @return The lower 8 bits of the returned value are the bitmap of * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 */ -static inline uint32_t pmu_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t pmu_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(PMU_EXT_WAKEUP_ST_REG, PMU_EXT_WAKEUP_STATUS); } @@ -768,7 +792,7 @@ static inline uint32_t pmu_ll_ext1_get_wakeup_status(void) /** * @brief Clear the ext1 wakeup source status */ -static inline void pmu_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void pmu_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR); } @@ -779,7 +803,7 @@ static inline void pmu_ll_ext1_clear_wakeup_status(void) * @param level_mask 0: Wake the chip when all selected GPIOs go low * 1: Wake the chip when any of the selected GPIOs go high */ -static inline void pmu_ll_ext1_set_wakeup_pins(uint32_t io_mask, int level_mask) +FORCE_INLINE_ATTR void pmu_ll_ext1_set_wakeup_pins(uint32_t io_mask, int level_mask) { REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, io_mask); REG_SET_FIELD(PMU_EXT_WAKEUP_LV_REG, PMU_EXT_WAKEUP_LV, level_mask); @@ -788,7 +812,7 @@ static inline void pmu_ll_ext1_set_wakeup_pins(uint32_t io_mask, int level_mask /** * @brief Clear all ext1 wakup-source setting */ -static inline void pmu_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void pmu_ll_ext1_clear_wakeup_pins(void) { REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, 0); } @@ -798,7 +822,7 @@ static inline void pmu_ll_ext1_clear_wakeup_pins(void) * @return The lower 8 bits of the returned value are the bitmap of * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 */ -static inline uint32_t pmu_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t pmu_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL); } diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 543b9c34c5a..af7cc9042cb 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -123,8 +123,8 @@ typedef enum { #define RTC_USB_TRIG_EN PMU_USB_WAKEUP_EN #if SOC_LP_CORE_SUPPORTED -#define RTC_LP_CORE_TRIG_EN PMU_LP_CORE_WAKEUP_EN //!< LP core wakeup -#define RTC_LP_CORE_TRAP_TRIG_EN PMU_LP_CORE_TRAP_WAKEUP_EN //!< LP core trap (exception) wakeup +#define RTC_LP_CORE_TRIG_EN PMU_LP_CORE_WAKEUP_HP_EN //!< LP core wakeup +#define RTC_LP_CORE_TRAP_TRIG_EN PMU_LP_CORE_TRAP_WAKEUP_EN //!< LP core trap (exception) wakeup #else #define RTC_LP_CORE_TRIG_EN 0 #define RTC_LP_CORE_TRAP_TRIG_EN 0 diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 4b51f5b2078..6c091ac5f5e 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -46,7 +46,7 @@ entries: if SOC_PM_SLEEP_CLK_ICG_USE_REGDMA = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP != y: pmu_sleep_clock_icg:pmu_sleep_clock_icg_config (noflash) sleep_mspi (noflash) - if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y: + if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32S31 != y: pmu_param:get_act_lp_dbias (noflash) if IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H21 = y: pmu_param:get_act_hp_drvb (noflash) diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h index b7876d6ffe2..7f6556bddea 100644 --- a/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h @@ -19,9 +19,10 @@ extern "C" { #define PMU_UART0_WAKEUP_EN BIT(6) #define PMU_UART1_WAKEUP_EN BIT(7) #define PMU_BLE_SOC_WAKEUP_EN BIT(10) -#define PMU_LP_CORE_WAKEUP_EN BIT(11) +#define PMU_LP_CORE_WAKEUP_HP_EN BIT(11) #define PMU_LP_CORE_TRAP_WAKEUP_EN BIT(12) #define PMU_USB_WAKEUP_EN BIT(14) +#define PMU_MODEM_WAKEUP_PROTECT BIT(16) #ifdef __cplusplus } diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_bit_defs.h index fe9b958e7c2..2b8078d7ef9 100644 --- a/components/esp_hw_support/port/esp32c6/private_include/pmu_bit_defs.h +++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_bit_defs.h @@ -20,10 +20,10 @@ extern "C" { #define PMU_UART1_WAKEUP_EN BIT(7) #define PMU_SDIO_WAKEUP_EN BIT(8) #define PMU_BLE_SOC_WAKEUP_EN BIT(10) -#define PMU_LP_CORE_WAKEUP_EN BIT(11) +#define PMU_LP_CORE_WAKEUP_HP_EN BIT(11) #define PMU_LP_CORE_TRAP_WAKEUP_EN BIT(12) #define PMU_USB_WAKEUP_EN BIT(14) - +#define PMU_MODEM_WAKEUP_PROTECT BIT(16) #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h index f3550538bf9..e29050c6b41 100644 --- a/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h +++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h @@ -20,8 +20,9 @@ extern "C" { #define PMU_UART1_WAKEUP_EN BIT(7) #define PMU_UART2_WAKEUP_EN BIT(9) #define PMU_BLE_SOC_WAKEUP_EN BIT(10) -// #define PMU_LP_CORE_WAKEUP_EN BIT(11) +#define PMU_LP_CORE_WAKEUP_HP_EN BIT(11) #define PMU_USB_WAKEUP_EN BIT(14) +#define PMU_MODEM_WAKEUP_PROTECT BIT(16) #ifdef __cplusplus } diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_bit_defs.h index 72931274a7a..6d25676c483 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_bit_defs.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_bit_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,7 @@ extern "C" { #endif #define PMU_SDIO_WAKEUP_EN BIT(0) -#define PMU_LP_CORE_WAKEUP_EN BIT(1) +#define PMU_LP_CORE_WAKEUP_HP_EN BIT(1) #define PMU_GPIO_WAKEUP_EN BIT(2) #define PMU_USB_WAKEUP_EN BIT(3) #define PMU_UART4_WAKEUP_EN BIT(4) @@ -31,6 +31,8 @@ extern "C" { #define PMU_LP_TIMER1_WAKEUP_EN BIT(18) #define PMU_LP_I2S_WAKEUP_EN BIT(19) +#define PMU_INTERRUPT_WAKEUP BIT(23) + // BIT order in PLL control registers in PMU #define PMU_CPLL_CTRL BIT(0) #define PMU_SPLL_CTRL BIT(1) diff --git a/components/esp_hw_support/port/esp32s31/pmu_init.c b/components/esp_hw_support/port/esp32s31/pmu_init.c index a540ba0ec98..508c01e666f 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_init.c +++ b/components/esp_hw_support/port/esp32s31/pmu_init.c @@ -90,14 +90,14 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa pmu_ll_hp_set_regulator_dbias_select (ctx->hal->dev, mode, anlg->regulator0.dbias_sel); pmu_ll_hp_set_regulator_dbias_init (ctx->hal->dev, mode, anlg->regulator0.dig_dbias_init); } - pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd); - pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias); - pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd); - pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias); - pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias); - pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd); + pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd); + pmu_ll_hp_set_regulator_sleep_memory_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias); + pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd); + pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias); + pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd); pmu_ll_hp_set_regulator_sleep_connect_enable(ctx->hal->dev, mode, anlg->regulator0.slp_connect_en); - pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b); + pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b); /* Default configuration of hp-system retention sub-system in active, modem * and sleep modes */ @@ -158,6 +158,8 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx) } /* Isolate all memory banks while sleeping, avoid memory leakage current */ pmu_ll_hp_set_memory_no_isolate (ctx->hal->dev, 0); + /* Disable memory force pu for memory pd during deep sleep */ + pmu_ll_hp_set_memory_power_up (ctx->hal->dev, 0); pmu_ll_lp_set_power_force_power_up (ctx->hal->dev, false); pmu_ll_lp_set_power_force_no_reset (ctx->hal->dev, false); @@ -210,6 +212,4 @@ void pmu_init(void) pmu_hp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); - - WRITE_PERI_REG(PMU_POWER_PD_MEM_CNTL_REG, 0); } diff --git a/components/esp_hw_support/port/esp32s31/pmu_param.c b/components/esp_hw_support/port/esp32s31/pmu_param.c index b284bd20819..2fc17e5e225 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_param.c +++ b/components/esp_hw_support/port/esp32s31/pmu_param.c @@ -38,9 +38,15 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .clk_power = { \ .i2c_iso_en = 0, \ .i2c_retention = 0, \ - .xpd_bb_i2c = 0, \ - .xpd_pll_i2c = 0x3, \ - .xpd_pll = 0x3 \ + .xpd_bb_i2c = 1, \ + .xpd_cpll_i2c = 1, \ + .xpd_bbpll_i2c = 1, \ + .xpd_apll_i2c = 0, \ + .xpd_mpll_i2c = 0, \ + .xpd_cpll = 1, \ + .xpd_bbpll = 1, \ + .xpd_apll = 0, \ + .xpd_mpll = 0, \ }, \ .xtal = { \ .xpd_xtal = 1 \ @@ -62,9 +68,15 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .clk_power = { \ .i2c_iso_en = 1, \ .i2c_retention = 1, \ - .xpd_bb_i2c = 0, \ - .xpd_pll_i2c = 0x3, \ - .xpd_pll = 0x3 \ + .xpd_bb_i2c = 1, \ + .xpd_cpll_i2c = 1, \ + .xpd_bbpll_i2c = 1, \ + .xpd_apll_i2c = 0, \ + .xpd_mpll_i2c = 0, \ + .xpd_cpll = 1, \ + .xpd_bbpll = 1, \ + .xpd_apll = 0, \ + .xpd_mpll = 0, \ }, \ .xtal = { \ .xpd_xtal = 1 \ @@ -87,8 +99,14 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .i2c_iso_en = 1, \ .i2c_retention = 1, \ .xpd_bb_i2c = 0, \ - .xpd_pll_i2c = 0, \ - .xpd_pll = 0 \ + .xpd_cpll_i2c = 0, \ + .xpd_bbpll_i2c = 0, \ + .xpd_apll_i2c = 0, \ + .xpd_mpll_i2c = 0, \ + .xpd_cpll = 0, \ + .xpd_bbpll = 0, \ + .xpd_apll = 0, \ + .xpd_mpll = 0, \ }, \ .xtal = { \ .xpd_xtal = 0 \ @@ -178,27 +196,21 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod .syscntl = { \ .c_channel = 1, \ .uart_wakeup_en = 0, \ - .lp_pad_hold_all = 0, \ - .hp_pad_hold_all = 0, \ - .dig_pad_slp_sel = 1, \ + .lp_pad_hold_all = 1, \ + .hp_pad_hold_all = 1, \ + .dig_pad_slp_sel = 0, \ .dig_pause_wdt = 1, \ .dig_cpu_stall = 1 \ } \ } -/** - * - hp_pad_hold_all: - * - when top off: must set to 1; - * - when top on: 0 if use pad; 1 if not use pad - * - dig_pad_slp_sel: must set to 1 when sleep - */ #define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \ .syscntl = { \ .c_channel = 0, \ .uart_wakeup_en = 1, \ - .lp_pad_hold_all = 0, \ + .lp_pad_hold_all = 1, \ .hp_pad_hold_all = 1, \ - .dig_pad_slp_sel = 1, \ + .dig_pad_slp_sel = 0, \ .dig_pause_wdt = 1, \ .dig_cpu_stall = 1 \ } \ diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 8449304dcd7..29e61e36958 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -238,6 +238,13 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val); pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal); + if (dslp) { + pmu_ll_hp_set_memory_power_on_mask(ctx->hal->dev, 0); + } else { + pmu_ll_hp_set_memory_power_on_mask(ctx->hal->dev, 0xf); + } + + pmu_ll_set_rf_power_control(ctx->hal->dev, 0); pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val); pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val); @@ -249,26 +256,24 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig) { pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel); + pmu_ll_hp_set_hold_all_hp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.hp_pad_hold_all); pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all); + pmu_ll_hp_set_pause_watchdog (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pause_wdt); pmu_ll_hp_set_c_channel_enable (ctx->hal->dev, HP(SLEEP), dig->syscntl.c_channel); } static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp) { assert(ctx->hal); - pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); - pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); - pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd); - pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd); - pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); - pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias); - pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten); - pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); - pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); - - pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias); - pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.dbias); - pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.drv_b); + pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); + pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); + pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd); + pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd); + pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); + pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias); + pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); + pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); @@ -278,9 +283,6 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten); pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); - - pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_xpd); - pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.xpd); } static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp) diff --git a/components/esp_hw_support/port/esp32s31/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32s31/private_include/pmu_bit_defs.h index 470ec8872cd..6ea92b8e80a 100644 --- a/components/esp_hw_support/port/esp32s31/private_include/pmu_bit_defs.h +++ b/components/esp_hw_support/port/esp32s31/private_include/pmu_bit_defs.h @@ -10,11 +10,11 @@ extern "C" { #endif -#define PMU_SDIO_WAKEUP_EN BIT(0) -#define PMU_LP_CORE_WAKEUP_EN BIT(1) +#define PMU_LP_CORE_WAKEUP_HP_EN BIT(0) +#define PMU_HP_CORE_WAKEUP_LP_EN BIT(1) #define PMU_GPIO_WAKEUP_EN BIT(2) #define PMU_USB_WAKEUP_EN BIT(3) -#define PMU_UART4_WAKEUP_EN BIT(4) +#define PMU_INTERRUPT_WAKEUP BIT(4) #define PMU_UART3_WAKEUP_EN BIT(5) #define PMU_UART2_WAKEUP_EN BIT(6) #define PMU_UART1_WAKEUP_EN BIT(7) @@ -25,14 +25,13 @@ extern "C" { #define PMU_EXT1_WAKEUP_EN BIT(12) #define PMU_RTC_TIMER_WAKEUP_EN BIT(13) #define PMU_BOD_WAKEUP_EN BIT(14) -#define PMU_VBAT_UNDERVOLT_WAKEUP_EN BIT(15) #define PMU_LP_CORE_TRAP_WAKEUP_EN BIT(16) #define PMU_ETM_WAKEUP_EN BIT(17) #define PMU_LP_TIMER1_WAKEUP_EN BIT(18) -#define PMU_LP_I2S_WAKEUP_EN BIT(19) #define PMU_WIFI_SOC_WAKEUP_EN BIT(22) #define PMU_WIFI_BEACON_WAKEUP_EN BIT(23) -#define PMU_BLE_SOC_WAKEUP_EN BIT(24) +#define PMU_MODEM_WAKEUP_PROTECT BIT(24) +#define PMU_BLE_SOC_WAKEUP_EN BIT(25) // BIT order in PLL control registers in PMU diff --git a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h index 652d9d82601..48b4555cd97 100644 --- a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h @@ -278,7 +278,7 @@ typedef struct { .pd_modem_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0, \ .pd_hp_cnnt_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CNNT) ? 1 : 0, \ .pd_hp_cpu_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0, \ - .pd_modem_pwr_pd_en = 0, \ + .pd_modem_pwr_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MEM) ? 1 : 0, \ .pd_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \ .pd_hp_mem_pd_en = 0, \ .mem_dslp = 0, \ @@ -330,15 +330,19 @@ typedef struct { #define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \ .syscntl = { \ .dig_pad_slp_sel = 0, \ - .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ + .lp_pad_hold_all = 1, \ + .hp_pad_hold_all = 1, \ + .dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \ .c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \ } \ } #define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \ .syscntl = { \ - .dig_pad_slp_sel = 0, \ - .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ + .dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \ + .lp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \ + .hp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \ + .dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \ .c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \ } \ } @@ -363,15 +367,6 @@ typedef struct { .dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6 \ } \ }, \ - .lp_sys[PMU_MODE_LP_ACTIVE] = { \ - .analog = { \ - .slp_xpd = 0, \ - .slp_dbias = 0, \ - .xpd = 1, \ - .dbias = 29, \ - .drv_b = 0x0 \ - } \ - }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ .drv_b = PMU_LP_DRVB_LIGHTSLEEP, \ @@ -395,15 +390,6 @@ typedef struct { .dbg_atten = PMU_DBG_HP_DEEPSLEEP \ } \ }, \ - .lp_sys[PMU_MODE_LP_ACTIVE] = { \ - .analog = { \ - .xpd = 1, \ - .dbias = 0x1a, \ - .slp_xpd = 0, \ - .slp_dbias = 0, \ - .drv_b = 0x7 \ - } \ - }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ @@ -501,7 +487,7 @@ typedef struct pmu_sleep_machine_constant { }, \ .hp = { \ .min_slp_time_us = 450, \ - .clock_domain_sync_time_us = 150, \ + .clock_domain_sync_time_us = 2, \ .system_dfs_up_work_time_us = 124, \ .analog_wait_time_us = 154, \ .isolate_wait_time_us = 1, \ @@ -509,9 +495,9 @@ typedef struct pmu_sleep_machine_constant { .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ .regdma_s2m_work_time_us = 172, \ - .regdma_s2a_work_time_us = 685, \ + .regdma_s2a_work_time_us = 750, \ .regdma_m2a_work_time_us = 278, \ - .regdma_a2s_work_time_us = 382, \ + .regdma_a2s_work_time_us = 400, \ .regdma_rf_on_work_time_us = 70, \ .regdma_rf_off_work_time_us = 23, \ .xtal_wait_stable_time_us = 250, \ diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c59964aa86c..3731b1e4097 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -288,7 +288,7 @@ typedef struct { #endif portMUX_TYPE lock; uint64_t sleep_duration; - uint32_t wakeup_triggers : 20; + uint32_t wakeup_triggers; #if SOC_PM_SUPPORT_EXT1_WAKEUP uint32_t ext1_trigger_mode : 22; // 22 is the maximum RTCIO number in all chips uint32_t ext1_rtc_gpio_mask : 22; diff --git a/components/soc/esp32s31/register/soc/pmu_reg.h b/components/soc/esp32s31/register/soc/pmu_reg.h index b90162301a7..b143653cc9f 100644 --- a/components/soc/esp32s31/register/soc/pmu_reg.h +++ b/components/soc/esp32s31/register/soc/pmu_reg.h @@ -227,56 +227,56 @@ extern "C" { /** PMU_HP_ACTIVE_XPD_CPLL_I2C : R/W; bitpos: [23]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_CPLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL_I2C (BIT(23)) #define PMU_HP_ACTIVE_XPD_CPLL_I2C_M (PMU_HP_ACTIVE_XPD_CPLL_I2C_V << PMU_HP_ACTIVE_XPD_CPLL_I2C_S) #define PMU_HP_ACTIVE_XPD_CPLL_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_CPLL_I2C_S 23 /** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [24]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_BBPLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(24)) #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 24 /** PMU_HP_ACTIVE_XPD_APLL_I2C : R/W; bitpos: [25]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_APLL_I2C 0x00000001U -#define PMU_HP_ACTIVE_XPD_APLL_I2C_M (PMU_HP_ACTIVE_XPD_APLL_I2C_V << PMU_HP_ACTIVE_XPD_ACPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_APLL_I2C (BIT(25)) +#define PMU_HP_ACTIVE_XPD_APLL_I2C_M (PMU_HP_ACTIVE_XPD_APLL_I2C_V << PMU_HP_ACTIVE_XPD_APLL_I2C_S) #define PMU_HP_ACTIVE_XPD_APLL_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_APLL_I2C_S 25 /** PMU_HP_ACTIVE_XPD_MPLL_I2C : R/W; bitpos: [26]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_MLL_I2C 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL_I2C (BIT(26)) #define PMU_HP_ACTIVE_XPD_MPLL_I2C_M (PMU_HP_ACTIVE_XPD_MPLL_I2C_V << PMU_HP_ACTIVE_XPD_MPLL_I2C_S) #define PMU_HP_ACTIVE_XPD_MPLL_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_MPLL_I2C_S 26 /** PMU_HP_ACTIVE_XPD_CPLL : R/W; bitpos: [27]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_CPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_CPLL (BIT(27)) #define PMU_HP_ACTIVE_XPD_CPLL_M (PMU_HP_ACTIVE_XPD_CPLL_V << PMU_HP_ACTIVE_XPD_CPLL_S) #define PMU_HP_ACTIVE_XPD_CPLL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_CPLL_S 27 /** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [28]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_BBPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(28)) #define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) #define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BBPLL_S 28 /** PMU_HP_ACTIVE_XPD_APLL : R/W; bitpos: [29]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_APLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_APLL (BIT(29)) #define PMU_HP_ACTIVE_XPD_APLL_M (PMU_HP_ACTIVE_XPD_APLL_V << PMU_HP_ACTIVE_XPD_APLL_S) #define PMU_HP_ACTIVE_XPD_APLL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_APLL_S 29 /** PMU_HP_ACTIVE_XPD_MPLL : R/W; bitpos: [30]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_XPD_MPLL 0x00000001U +#define PMU_HP_ACTIVE_XPD_MPLL (BIT(30)) #define PMU_HP_ACTIVE_XPD_MPLL_M (PMU_HP_ACTIVE_XPD_MPLL_V << PMU_HP_ACTIVE_XPD_MPLL_S) #define PMU_HP_ACTIVE_XPD_MPLL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_MPLL_S 30 @@ -780,20 +780,62 @@ extern "C" { #define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) #define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U #define PMU_HP_MODEM_XPD_BB_I2C_S 22 -/** PMU_HP_MODEM_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; +/** PMU_HP_MODEM_XPD_CPLL_I2C : R/W; bitpos: [23]; default: 0; * need_des */ -#define PMU_HP_MODEM_XPD_PLL_I2C 0x0000000FU -#define PMU_HP_MODEM_XPD_PLL_I2C_M (PMU_HP_MODEM_XPD_PLL_I2C_V << PMU_HP_MODEM_XPD_PLL_I2C_S) -#define PMU_HP_MODEM_XPD_PLL_I2C_V 0x0000000FU -#define PMU_HP_MODEM_XPD_PLL_I2C_S 23 -/** PMU_HP_MODEM_XPD_PLL : R/W; bitpos: [30:27]; default: 0; +#define PMU_HP_MODEM_XPD_CPLL_I2C (BIT(23)) +#define PMU_HP_MODEM_XPD_CPLL_I2C_M (PMU_HP_MODEM_XPD_CPLL_I2C_V << PMU_HP_MODEM_XPD_CPLL_I2C_S) +#define PMU_HP_MODEM_XPD_CPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_CPLL_I2C_S 23 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [24]; default: 0; * need_des */ -#define PMU_HP_MODEM_XPD_PLL 0x0000000FU -#define PMU_HP_MODEM_XPD_PLL_M (PMU_HP_MODEM_XPD_PLL_V << PMU_HP_MODEM_XPD_PLL_S) -#define PMU_HP_MODEM_XPD_PLL_V 0x0000000FU -#define PMU_HP_MODEM_XPD_PLL_S 27 +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(24)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 24 +/** PMU_HP_MODEM_XPD_APLL_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_APLL_I2C (BIT(25)) +#define PMU_HP_MODEM_XPD_APLL_I2C_M (PMU_HP_MODEM_XPD_APLL_I2C_V << PMU_HP_MODEM_XPD_APLL_I2C_S) +#define PMU_HP_MODEM_XPD_APLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_APLL_I2C_S 25 +/** PMU_HP_MODEM_XPD_MPLL_I2C : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_MPLL_I2C (BIT(26)) +#define PMU_HP_MODEM_XPD_MPLL_I2C_M (PMU_HP_MODEM_XPD_MPLL_I2C_V << PMU_HP_MODEM_XPD_MPLL_I2C_S) +#define PMU_HP_MODEM_XPD_MPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_MPLL_I2C_S 26 +/** PMU_HP_MODEM_XPD_CPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_CPLL (BIT(27)) +#define PMU_HP_MODEM_XPD_CPLL_M (PMU_HP_MODEM_XPD_CPLL_V << PMU_HP_MODEM_XPD_CPLL_S) +#define PMU_HP_MODEM_XPD_CPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_CPLL_S 27 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(28)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 28 +/** PMU_HP_MODEM_XPD_APLL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_APLL (BIT(29)) +#define PMU_HP_MODEM_XPD_APLL_M (PMU_HP_MODEM_XPD_APLL_V << PMU_HP_MODEM_XPD_APLL_S) +#define PMU_HP_MODEM_XPD_APLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_APLL_S 29 +/** PMU_HP_MODEM_XPD_MPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_MPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_MPLL_M (PMU_HP_MODEM_XPD_MPLL_V << PMU_HP_MODEM_XPD_MPLL_S) +#define PMU_HP_MODEM_XPD_MPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_MPLL_S 30 /** PMU_HP_MODEM_BIAS_REG register * need_des @@ -1231,20 +1273,62 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) #define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U #define PMU_HP_SLEEP_XPD_BB_I2C_S 22 -/** PMU_HP_SLEEP_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; +/** PMU_HP_SLEEP_XPD_CPLL_I2C : R/W; bitpos: [23]; default: 0; * need_des */ -#define PMU_HP_SLEEP_XPD_PLL_I2C 0x0000000FU -#define PMU_HP_SLEEP_XPD_PLL_I2C_M (PMU_HP_SLEEP_XPD_PLL_I2C_V << PMU_HP_SLEEP_XPD_PLL_I2C_S) -#define PMU_HP_SLEEP_XPD_PLL_I2C_V 0x0000000FU -#define PMU_HP_SLEEP_XPD_PLL_I2C_S 23 -/** PMU_HP_SLEEP_XPD_PLL : R/W; bitpos: [30:27]; default: 0; +#define PMU_HP_SLEEP_XPD_CPLL_I2C (BIT(23)) +#define PMU_HP_SLEEP_XPD_CPLL_I2C_M (PMU_HP_SLEEP_XPD_CPLL_I2C_V << PMU_HP_SLEEP_XPD_CPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_CPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_CPLL_I2C_S 23 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [24]; default: 0; * need_des */ -#define PMU_HP_SLEEP_XPD_PLL 0x0000000FU -#define PMU_HP_SLEEP_XPD_PLL_M (PMU_HP_SLEEP_XPD_PLL_V << PMU_HP_SLEEP_XPD_PLL_S) -#define PMU_HP_SLEEP_XPD_PLL_V 0x0000000FU -#define PMU_HP_SLEEP_XPD_PLL_S 27 +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(24)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 24 +/** PMU_HP_SLEEP_XPD_APLL_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_APLL_I2C (BIT(25)) +#define PMU_HP_SLEEP_XPD_APLL_I2C_M (PMU_HP_SLEEP_XPD_APLL_I2C_V << PMU_HP_SLEEP_XPD_APLL_I2C_S) +#define PMU_HP_SLEEP_XPD_APLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_APLL_I2C_S 25 +/** PMU_HP_SLEEP_XPD_MPLL_I2C : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_MPLL_I2C (BIT(26)) +#define PMU_HP_SLEEP_XPD_MPLL_I2C_M (PMU_HP_SLEEP_XPD_MPLL_I2C_V << PMU_HP_SLEEP_XPD_MPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_MPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_MPLL_I2C_S 26 +/** PMU_HP_SLEEP_XPD_CPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_CPLL (BIT(27)) +#define PMU_HP_SLEEP_XPD_CPLL_M (PMU_HP_SLEEP_XPD_CPLL_V << PMU_HP_SLEEP_XPD_CPLL_S) +#define PMU_HP_SLEEP_XPD_CPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_CPLL_S 27 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(28)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 28 +/** PMU_HP_SLEEP_XPD_APLL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_APLL (BIT(29)) +#define PMU_HP_SLEEP_XPD_APLL_M (PMU_HP_SLEEP_XPD_APLL_V << PMU_HP_SLEEP_XPD_APLL_S) +#define PMU_HP_SLEEP_XPD_APLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_APLL_S 29 +/** PMU_HP_SLEEP_XPD_MPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_MPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_MPLL_M (PMU_HP_SLEEP_XPD_MPLL_V << PMU_HP_SLEEP_XPD_MPLL_S) +#define PMU_HP_SLEEP_XPD_MPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_MPLL_S 30 /** PMU_HP_SLEEP_BIAS_REG register * need_des diff --git a/components/soc/esp32s31/register/soc/pmu_struct.h b/components/soc/esp32s31/register/soc/pmu_struct.h index 2d635a5aa6e..956811d5087 100644 --- a/components/soc/esp32s31/register/soc/pmu_struct.h +++ b/components/soc/esp32s31/register/soc/pmu_struct.h @@ -55,14 +55,20 @@ typedef union { typedef union { struct { - uint32_t reserved0 : 19; - uint32_t xpd_xtalx2 : 1; - uint32_t i2c_iso_en : 1; - uint32_t i2c_retention: 1; - uint32_t xpd_bb_i2c : 1; - uint32_t xpd_pll_i2c : 4; - uint32_t xpd_pll : 4; - uint32_t reserved1 : 1; + uint32_t reserved0 : 19; + uint32_t xpd_xtalx2 : 1; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention : 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_cpll_i2c : 1; + uint32_t xpd_bbpll_i2c : 1; + uint32_t xpd_apll_i2c : 1; + uint32_t xpd_mpll_i2c : 1; + uint32_t xpd_cpll : 1; + uint32_t xpd_bbpll : 1; + uint32_t xpd_apll : 1; + uint32_t xpd_mpll : 1; + uint32_t reserved1 : 1; }; uint32_t val; } pmu_hp_clk_power_reg_t;