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fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL
Align C6/H2 rtc_clk_cpu_freq_set_xtal behavior to other chips
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -16,8 +16,8 @@ extern "C" {
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* @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency.
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*
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* This function does not disable BBPLL. If BBPLL requires to be disabled to save power, please call
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* `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check to see whether can disable the BBPLL after switching the
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* CPU clock source to XTAL.
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* `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock
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* source to XTAL (except for S2).
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*
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* Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
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* clock source back to XTAL (by default) before reset.
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@@ -30,12 +30,6 @@ void rtc_clk_cpu_set_to_default_config(void);
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* Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock
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*
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* Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`.
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* For light and deep sleep, whether to disable the BBPLL in the interal call to `rtc_clk_cpu_freq_set_xtal`
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* varies for targets.
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* On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore.
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* `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer.
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* On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so
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* `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use.
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*/
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void rtc_clk_bbpll_add_consumer(void);
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