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feat(spi_flash): Add exclusive support for ESP32H4

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Add 32bit addr support for esp32s31 as well
This commit is contained in:
Song Ruo Jing
2026-06-08 17:56:09 +08:00
parent c9eced7205
commit 545b31e6b9
35 changed files with 647 additions and 356 deletions
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components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+8
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@@ -215,6 +215,10 @@ config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED
bool
default y
config SOC_ECDSA_SUPPORTED
bool
default y
@@ -871,6 +875,10 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+2
View File
@@ -89,6 +89,7 @@
#define SOC_WDT_SUPPORTED 1
#define SOC_RTC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1
#define SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED 1
#define SOC_ECDSA_SUPPORTED 1
#define SOC_SPIRAM_SUPPORTED 1
#define SOC_LIGHT_SLEEP_SUPPORTED 1
@@ -376,6 +377,7 @@
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
components/soc/esp32h4/register/soc/spi1_mem_reg.h
+25 -1
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -417,6 +417,30 @@ extern "C" {
#define SPI_MEM_STATUS_M (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
#define SPI_MEM_STATUS_V 0x0000FFFFU
#define SPI_MEM_STATUS_S 0
/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE 0x000000FFU
#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
#define SPI_MEM_WB_MODE_V 0x000000FFU
#define SPI_MEM_WB_MODE_S 16
/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_BITLEN 0x00000007U
#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S)
#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U
#define SPI_MEM_WB_MODE_BITLEN_S 24
/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_EN (BIT(27))
#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S)
#define SPI_MEM_WB_MODE_EN_V 0x00000001U
#define SPI_MEM_WB_MODE_EN_S 27
/** SPI_MEM_MISC_REG register
* SPI1 misc register