From 542756888b5e4da9fd3021228ac48469e9898066 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 15 Jan 2026 14:53:14 +0800 Subject: [PATCH] fix(soc): fix LP_UART clock source definitions to FOSC instead of LP_FAST --- components/hal/esp32p4/include/hal/uart_ll.h | 4 ++-- components/soc/esp32p4/include/soc/clk_tree_defs.h | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 4fb522939a9..bc76a4cd79b 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -97,7 +97,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou switch (LPPERI.core_clk_sel.lp_uart_clk_sel) { default: case 0: - *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST; + *source_clk = (soc_module_clk_t)LP_UART_SCLK_RC_FAST; break; case 1: *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2; @@ -118,7 +118,7 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_ { (void)hw; switch (src_clk) { - case LP_UART_SCLK_LP_FAST: + case LP_UART_SCLK_RC_FAST: LPPERI.core_clk_sel.lp_uart_clk_sel = 0; break; case LP_UART_SCLK_XTAL_D2: diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index a5550cbe7c3..209e02c4b6d 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -273,16 +273,16 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of LP_UART */ -#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} +#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2} /** * @brief Type of LP_UART clock source */ typedef enum { - LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ + LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is FOSC */ LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ - // LP_UART_SCLK_LP_PLL = SOC_MOD_CLK_LP_PLL, /*!< LP_UART source clock is LP_PLL (8M PLL) */ TODO: LP_PLL clock requires extra support - LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ + // LP_UART_SCLK_LP_PLL = SOC_MOD_CLK_LP_PLL, /*!< LP_UART source clock is LP_PLL (8M PLL) */ TODO: LP_PLL clock requires extra support + LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock default choice is FOSC */ } soc_periph_lp_uart_clk_src_t; //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////