fix(build_system): cleaned up esp_psram dependencies

Also moved mspi_mb functionality to esp_hw_support together with
other mspi functionality

components/esp_hw_support/CMakeLists.txt

@@ -17,6 +17,7 @@ set(public_include_dirs "include" "include/soc"
                         "mspi/mspi_timing_tuning/include" "mspi/mspi_timing_tuning/tuning_scheme_impl/include"
                         "mspi/mspi_intr/include"
                         "mspi/esp_mspi_align/include"
+                        "mspi/mspi_mem_barrier/include"
                         "power_supply/include" "modem/include")
 
 if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/include/soc/${target}")
@@ -73,7 +74,8 @@ if(NOT non_os_build)
                      "port/${target}/esp_clk_tree.c"
                      "spi_bus_lock.c"
                      "heap_align_hw.c"
-                     "clk_utils.c")
+                     "clk_utils.c"
+                     "mspi/mspi_mem_barrier/mspi_mem_barrier.c")
     if(CONFIG_SOC_USB_OTG_SUPPORTED)
         list(APPEND srcs "usb_phy/usb_phy.c")
     endif()

components/esp_hw_support/mspi/mspi_mem_barrier/include/esp_private/mspi_mem_barrier.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize the MSPI memory barrier workaround
+ *
+ * On targets affected by the MSPI memory barrier hardware issue, this allocates the
+ * dummy cacheline used by @ref esp_psram_mspi_mb to force a cache writeback/fence. On
+ * other targets this is a no-op.
+ *
+ * @return ESP_OK on success, otherwise an error code
+ */
+esp_err_t esp_psram_mspi_mb_init(void);
+
+/**
+ * @brief MSPI memory barrier
+ *
+ * Some targets need this workaround after a DMA transfer into PSRAM to make sure the
+ * data is visible to the CPU. This is a no-op on targets that don't need the workaround.
+ */
+void esp_psram_mspi_mb(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/mspi/mspi_mem_barrier/mspi_mem_barrier.c

@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_cache.h"
+#include "esp_heap_caps.h"
+#include "esp_private/mspi_mem_barrier.h"
+
+#define MSPI_MEM_BARRIER_WORKAROUND    ((CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101))
+
+__attribute__((unused)) ESP_LOG_ATTR_TAG_DRAM(TAG, "mspi_mem_barrier");
+
+#if MSPI_MEM_BARRIER_WORKAROUND
+static void *s_psram_mb_dummy_cacheline;  //dummy cacheline for cache memory barrier
+#endif
+
+esp_err_t esp_psram_mspi_mb_init(void)
+{
+#if MSPI_MEM_BARRIER_WORKAROUND
+    s_psram_mb_dummy_cacheline = heap_caps_calloc(1, CONFIG_CACHE_L1_CACHE_LINE_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_CACHE_ALIGNED);
+    if (!s_psram_mb_dummy_cacheline) {
+        ESP_EARLY_LOGE(TAG, "Failed to allocate dummy cacheline for PSRAM memory barrier!");
+    }
+#endif
+
+    return ESP_OK;
+}
+
+void IRAM_ATTR esp_psram_mspi_mb(void)
+{
+#if MSPI_MEM_BARRIER_WORKAROUND
+    if (s_psram_mb_dummy_cacheline) {
+        uint32_t *p = (uint32_t *)s_psram_mb_dummy_cacheline;
+        *p = (*p + 1) % UINT32_MAX;
+        __attribute__((unused)) esp_err_t ret = ESP_FAIL;
+        ret = esp_cache_msync(s_psram_mb_dummy_cacheline, sizeof(uint32_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); //malloc is aligned, no need to writeback all
+        assert(ret == ESP_OK);
+        asm volatile("fence");
+    }
+#endif
+}