feat(hal): Add LL-API to check whether RNG is enabled

- Also add RNG LL-APIs for ESP32-C61
- Add SOC_RNG_CLOCK_IS_INDEPENDENT for ESP32-C61: now that
  rng_ll_disable() actually clears the RNG clock gate, the application
  needs the esp_hw_support startup hook to re-enable the RNG after
  bootloader_random_disable()

components/hal/esp32c5/include/hal/rng_ll.h

@@ -15,6 +15,8 @@
 
 //For ESP32C5, RNG needs to be reset and enabled again when wakeup from sleep
 #define RNG_LL_NEEDS_RESET_WHEN_WAKEUP 1
+//Default value for the RNG timer clock divider
+#define RNG_LL_CFG_PSCALE              255
 
 #ifdef __cplusplus
 extern "C" {
@@ -40,6 +42,16 @@ static inline void rng_ll_enable_sample(bool enable)
     LPPERI.rng_cfg.rng_sample_enable = enable;
 }
 
+/**
+ * @brief Set RNG timer prescaler
+ *
+ * @param prescaler Timer prescaler value (0-255)
+ */
+static inline void rng_ll_set_timer_prescaler(uint8_t prescaler)
+{
+    LPPERI.rng_cfg.rng_timer_pscale = prescaler;
+}
+
 /**
  * @brief Enable or disable rng xor rtc timer.
  *
@@ -77,6 +89,7 @@ static inline void rng_ll_reset(void)
 static inline void rng_ll_enable(void)
 {
     _lp_clkrst_ll_enable_rng_clock(true);
+    rng_ll_set_timer_prescaler(RNG_LL_CFG_PSCALE);
     rng_ll_enable_sample(true);
     rng_ll_enable_rtc_timer(true);
     rng_ll_enable_rng_timer(true);
@@ -95,6 +108,16 @@ static inline void rng_ll_disable(void)
     _lp_clkrst_ll_enable_rng_clock(false);
 }
 
+/**
+ * @brief Check that the RNG is live: clocked and out of reset.
+ *
+ * @return True if the RNG is enabled and operational, false otherwise.
+ */
+static inline bool rng_ll_is_enabled(void)
+{
+    return LPPERI.clk_en.rng_ck_en && !LPPERI.reset_en.lp_rng_reset_en;
+}
+
 #ifdef __cplusplus
 }
 #endif