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Merge branch 'fix/enable_pvt_esp32c5_v5.5' into 'release/v5.5'

Browse Source 
Revert "disable PVT feature for esp32c5"

See merge request espressif/esp-idf!50422
This commit is contained in:
Jiang Jiang Jian
2026-07-09 17:04:01 +08:00
parent 416d47ecdf aab94d3658
commit 5215699d57
11 changed files with 98 additions and 33 deletions
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components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+4 -4
View File
@@ -105,20 +105,20 @@ set pvt default param
*/
#define PVT_CHANNEL0_SEL 33
#define PVT_CHANNEL1_SEL 37
#define PVT_CHANNEL0_CFG 0x13e80
#define PVT_CHANNEL1_CFG 0x13e80
#define PVT_CHANNEL0_CFG 0x11fff
#define PVT_CHANNEL1_CFG 0x17fff
#define PVT_CHANNEL2_CFG 0x10000
#define PVT_CMD0 0x24
#define PVT_CMD1 0x5
#define PVT_CMD2 0x427
#define PVT_TARGET 0xffff
#define PVT_CLK_DIV 1
#define PVT_DELAY_NUM_HIGH 154
#define PVT_DELAY_NUM_HIGH 157
#define PVT_DELAY_NUM_LOW 147
#define PVT_PUMP_CHANNEL_CODE 1
#define PVT_PUMP_BITMAP 22
#define PVT_PUMP_DRV 0
#define PVT_DELAY_NUM_PUMP 143
#define PVT_DELAY_NUM_PUMP 139
/**
* @brief Initialize PVT related parameters
components/esp_hw_support/port/esp32c5/pmu_pvt.c
+24
View File
@@ -26,6 +26,8 @@
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
#if CONFIG_ESP_ENABLE_PVT
@@ -83,6 +85,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (pvt_enable_flag == true) {
return;
}
REG_SET_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN); // Must reset after pd_cpu
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -119,6 +124,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -129,7 +137,11 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
esp_rom_delay_us(50);
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -138,6 +150,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -147,6 +160,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -158,9 +174,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c5/rtc_clk.c
+4 -8
View File
@@ -180,10 +180,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_8m(void)
@@ -193,10 +189,6 @@ static void rtc_clk_cpu_freq_to_8m(void)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -477,6 +469,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
#ifndef BOOTLOADER_BUILD
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+2 -2
View File
@@ -102,8 +102,8 @@ set pvt default param
*/
#define PVT_CHANNEL0_SEL 34
#define PVT_CHANNEL1_SEL 38
#define PVT_CHANNEL0_CFG 0x1033e
#define PVT_CHANNEL1_CFG 0x1033e
#define PVT_CHANNEL0_CFG 0x11fff
#define PVT_CHANNEL1_CFG 0x17fff
#define PVT_CHANNEL2_CFG 0x10000
#define PVT_CMD0 0x24
#define PVT_CMD1 0x5
components/esp_hw_support/port/esp32c6/pmu_pvt.c
+24
View File
@@ -28,6 +28,8 @@
static __attribute__((unused)) const char *TAG = "pmu_pvt";
#if CONFIG_ESP_ENABLE_PVT
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
static uint8_t get_lp_hp_gap(void)
{
@@ -83,6 +85,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (pvt_enable_flag == true) {
return;
}
REG_SET_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN); // Must reset after pd_cpu
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -120,6 +125,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAUL
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -129,7 +137,11 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -138,6 +150,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -147,6 +160,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -158,9 +174,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c6/rtc_clk.c
+4 -8
View File
@@ -191,10 +191,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_ls_divider(div);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_8m(void)
@@ -203,10 +199,6 @@ static void rtc_clk_cpu_freq_to_8m(void)
clk_ll_cpu_set_ls_divider(1);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -371,6 +363,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
components/esp_hw_support/port/esp32c61/include/soc/rtc.h
+3 -3
View File
@@ -105,15 +105,15 @@ set pvt default param
*/
#define PVT_CHANNEL0_SEL 33
#define PVT_CHANNEL1_SEL 37
#define PVT_CHANNEL0_CFG 0x13e80
#define PVT_CHANNEL1_CFG 0x13e80
#define PVT_CHANNEL0_CFG 0x11fff
#define PVT_CHANNEL1_CFG 0x17fff
#define PVT_CHANNEL2_CFG 0x10000
#define PVT_CMD0 0x24
#define PVT_CMD1 0x5
#define PVT_CMD2 0x427
#define PVT_TARGET 0xffff
#define PVT_CLK_DIV 1
#define PVT_DELAY_NUM_HIGH 142
#define PVT_DELAY_NUM_HIGH 145
#define PVT_DELAY_NUM_LOW 135
#define PVT_PUMP_CHANNEL_CODE 1
#define PVT_PUMP_BITMAP 22
components/esp_hw_support/port/esp32c61/pmu_pvt.c
+24
View File
@@ -25,6 +25,8 @@
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
#if CONFIG_ESP_ENABLE_PVT
@@ -82,6 +84,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (pvt_enable_flag == true) {
return;
}
REG_SET_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN); // Must reset after pd_cpu
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_RST_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -118,6 +123,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -127,7 +135,11 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -136,6 +148,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -145,6 +158,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -156,9 +172,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c61/rtc_clk.c
+4 -8
View File
@@ -178,10 +178,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_8m(void)
@@ -191,10 +187,6 @@ static void rtc_clk_cpu_freq_to_8m(void)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -356,6 +348,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -187,6 +187,10 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_PMU_PVT_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
View File
@@ -63,6 +63,7 @@
#define SOC_BOD_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1