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Fix output bit range in bitscrambler documentation

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Destination bit range incorrect in `Sub-instructions` example
This commit is contained in:
Xorlent
2026-04-17 17:20:28 +08:00
committed by C.S.M
parent dfc5bbb58c
commit 51d059232b
20 changed files with 188 additions and 61 deletions
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components/spi_flash/test_apps/esp_flash/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
+1 -1
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@@ -77,7 +77,7 @@
#define SPI2_PIN_NUM_WP 2
#define SPI2_PIN_NUM_CS 1
#elif CONFIG_IDF_TARGET_ESP32P4
#elif CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32S31
// Just use the same pins for HSPI
#define SPI2_PIN_NUM_MOSI 8
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
+2
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@@ -1113,6 +1113,7 @@ void test_flash_counter(const esp_partition_t* part)
// check for resset_counter after used
TEST_ASSERT_EACH_EQUAL_HEX8(0, &flash_counter, sizeof(esp_flash_counters_t));
#if SOC_FLASH_ENC_SUPPORTED
TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write_encrypted(chip, offs, write_buf, TEST_CNT_RW_LEN) );
TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read_encrypted(chip, offs, read_buf, TEST_CNT_RW_LEN) );
@@ -1127,6 +1128,7 @@ void test_flash_counter(const esp_partition_t* part)
TEST_ASSERT_EQUAL_UINT32(1 * TEST_CNT_RW_LEN, flash_counter.read.bytes);
TEST_ASSERT_EQUAL_UINT32(1 * TEST_CNT_RW_LEN, flash_counter.write.bytes);
TEST_ASSERT_EQUAL_UINT32(0, flash_counter.erase.bytes);
#endif //SOC_FLASH_ENC_SUPPORTED
}
TEST_CASE_FLASH("SPI flash counter test", test_flash_counter);
components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
+1 -1
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@@ -122,7 +122,7 @@ TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_fla
}
// TODO: This test is disabled on S3 with legacy impl - IDF-3505
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4, ESP32S31)
#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
typedef struct {
components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
-1
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@@ -17,7 +17,6 @@ from pytest_embedded_idf.utils import idf_parametrize
indirect=True,
)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
def test_esp_flash(dut: Dut) -> None:
dut.run_all_single_board_cases(group='esp_flash')