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Fix output bit range in bitscrambler documentation

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Destination bit range incorrect in `Sub-instructions` example
This commit is contained in:
Xorlent
2026-04-17 17:20:28 +08:00
committed by C.S.M
parent dfc5bbb58c
commit 51d059232b
20 changed files with 188 additions and 61 deletions
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components/esp_hal_mspi/esp32s31/include/hal/gpspi_flash_ll.h
+99 -28
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,6 +15,8 @@
#include <stdlib.h>
#include "soc/spi_reg.h"
#include "soc/spi_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include <sys/param.h> // For MIN/MAX
@@ -26,31 +28,41 @@
extern "C" {
#endif
// TODO: ["ESP32S31"] IDF-14778
#define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \
: ((host_id)==SPI3_HOST ? &GPSPI3 \
: ({abort();(spi_dev_t*)0;}))))
#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : (\
((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\
-1 \
((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\
-1 \
)) )
typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ 80
#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80)
#define GPSPI_FLASH_LL_SUPPORT_CLK_SRC_PRE_DIV (1)
#define GPSPI_FLASH_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
/*------------------------------------------------------------------------------
* Control
*----------------------------------------------------------------------------*/
/**
* Reset peripheral registers before configuration and starting control.
*
* @param dev Beginning address of the peripheral registers.
*/
* Reset peripheral registers before configuration and starting control
*
* @param dev Beginning address of the peripheral registers.
*/
static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
{
// TODO: [ESP32S31] IDF-14778
dev->user.val = 0;
dev->ctrl.val = 0;
dev->clk_gate.clk_en = 1;
dev->clk_gate.mst_clk_active = 1;
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -71,10 +83,23 @@ static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
*/
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
// TODO: ["ESP32S31"] IDF-14778
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
// If everything is word-aligned, do a faster memcpy
memcpy(buffer, (void *)dev->data_buf, read_len);
} else {
// Otherwise, slow(er) path copies word by word
int copy_len = read_len;
for (int i = 0; i < (read_len + 3) / 4; i++) {
int word_len = MIN(sizeof(uint32_t), copy_len);
uint32_t word = dev->data_buf[i].buf;
memcpy(buffer, &word, word_len);
buffer = (void *)((intptr_t)buffer + word_len);
copy_len -= word_len;
}
}
}
/**
@@ -85,7 +110,7 @@ static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer,
*/
static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
{
// TODO: ["ESP32S31"] IDF-14778
dev->data_buf[0].buf = word;
}
/**
@@ -97,7 +122,16 @@ static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
*/
static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
{
// TODO: ["ESP32S31"] IDF-14778
// Load data registers, word at a time
int num_words = (length + 3) / 4;
for (int i = 0; i < num_words; i++) {
uint32_t word = 0;
uint32_t word_len = MIN(length, sizeof(word));
memcpy(&word, buffer, word_len);
dev->data_buf[i].buf = word;
length -= word_len;
buffer = (void *)((intptr_t)buffer + word_len);
}
}
/**
@@ -165,11 +199,11 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
* Configs
*----------------------------------------------------------------------------*/
/**
* Select which pin to use for the flash
*
* @param dev Beginning address of the peripheral registers.
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
*/
* Select which pin to use for the flash
*
* @param dev Beginning address of the peripheral registers.
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
*/
static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
{
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
@@ -311,7 +345,9 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// TODO: ["ESP32S31"] IDF-14778
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -322,7 +358,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
// dev->addr = addr;
dev->addr.val = addr;
}
/**
@@ -335,7 +371,7 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
if (dummy_n > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1)
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
}
@@ -408,13 +444,42 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
{
uint32_t clk_id = 0;
switch (clk_source) {
case SPI_CLK_SRC_BBPLL:
clk_id = 2;
break;
case SPI_CLK_SRC_RC_FAST:
clk_id = 1;
break;
case SPI_CLK_SRC_XTAL:
hw->clk_gate.mst_clk_sel = 0;
clk_id = 0;
break;
default:
hw->clk_gate.mst_clk_sel = 1;
break;
HAL_ASSERT(false);
}
if (hw == &GPSPI2) {
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_clk_src_sel = clk_id;
} else if (hw == &GPSPI3) {
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_clk_src_sel = clk_id;
}
}
/**
* Enable/disable SPI flash module clock
*
* @param host_id SPI host ID
* @param enable true to enable, false to disable
*/
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
{
if (hw == &GPSPI2) {
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_hs_clk_en = enable;
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_mst_clk_en = enable;
} else if (hw == &GPSPI3) {
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_hs_clk_en = enable;
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_mst_clk_en = enable;
}
}
@@ -424,9 +489,15 @@ static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source
* @param hw Beginning address of the peripheral registers.
* @param enable true to enable, false to disable
*/
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
static inline void gpspi_flash_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div)
{
hw->clk_gate.clk_en = enable;
if (hw == &GPSPI2) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_hs_clk_div_num, hs_div - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_mst_clk_div_num, mst_div - 1);
} else if (hw == &GPSPI3) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_hs_clk_div_num, hs_div - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_mst_clk_div_num, mst_div - 1);
}
}
#ifdef __cplusplus
components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h
+21
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@@ -39,6 +39,7 @@
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_c_reg.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@@ -47,6 +48,7 @@ extern "C" {
#define MSPI_LL_PERIPH_NUM 4
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 6
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
@@ -216,6 +218,25 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel = clk_val;
}
/**
* Set MSPI Flash core clock
*
* @param spi_num SPI0 / SPI1
* @param core_clk_mhz core clock mhz
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_core_clock(int spi_num, uint32_t core_clk_mhz)
{
HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0);
if (core_clk_mhz == 80) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.flash_ctrl0, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV - 1));
HP_SYS_CLKRST.flash_ctrl0.reg_flash_core_clk_en = 1;
} else {
//ESP32S31 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz / 80MHz. We add assertion here to ensure this
HAL_ASSERT(false);
}
}
/*---------------------------------------------------------------
Misc
---------------------------------------------------------------*/
components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h
+5 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -240,7 +240,7 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
// SPIMEM0ctrl2.cs_hold_delay = cs_hold_delay;
SPIMEM0.mem_ctrl2.mem_cs_hold_delay = cs_hold_delay;
}
/**
@@ -296,7 +296,7 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
// SPIMEM0fsm.lock_delay_time = lock_time;
SPIMEM0.mem_fsm.mem_lock_delay_time = lock_time;
}
/**
@@ -677,7 +677,6 @@ static inline void spimem_flash_ll_set_fdummy_rin(spi_mem_dev_t *dev, uint32_t f
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
return 80;
int source_clk_mhz = 0;
switch (HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel) {
@@ -685,7 +684,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
source_clk_mhz = clk_ll_xtal_get_freq_mhz();
break;
case 1:
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // BBPLL
break;
case 2:
source_clk_mhz = CLK_LL_PLL_320M_FREQ_MHZ; // CPLL
@@ -812,7 +811,7 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
}
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI1_MEM_C_PES_END_INT_ENA_M
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_FLASH_INTR_SOURCE
/**
* @brief Get the address of the interrupt status register.