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Fix output bit range in bitscrambler documentation

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Destination bit range incorrect in `Sub-instructions` example
This commit is contained in:
Xorlent
2026-04-17 17:20:28 +08:00
committed by C.S.M
parent dfc5bbb58c
commit 51d059232b
20 changed files with 188 additions and 61 deletions
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components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h
-1
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@@ -30,7 +30,6 @@
#define CLK_LL_PLL_80M_FREQ_MHZ (80)
#define CLK_LL_PLL_160M_FREQ_MHZ (160)
#define CLK_LL_PLL_240M_FREQ_MHZ (240)
#define CLK_LL_PLL_320M_FREQ_MHZ (320)
#define CLK_LL_PLL_480M_FREQ_MHZ (480)