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Merge branch 'fix/uart_is_enable_check_error_on_s3_v5.4' into 'release/v5.4'

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Fix ESP32-S3 uart2 is_enabled check error (v5.4)

See merge request espressif/esp-idf!49350
This commit is contained in:
morris
2026-07-20 10:02:22 +08:00
parent 591ea73bfb e0f2141301
commit 515a532893
1 changed files with 13 additions and 8 deletions
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components/hal/esp32s3/include/hal/uart_ll.h
+13 -8
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@@ -68,14 +68,19 @@ typedef enum {
*/ */
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{ {
uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST : switch (uart_num) {
(uart_num == 1) ? SYSTEM_UART1_RST : case 0:
(uart_num == 2) ? SYSTEM_UART2_RST : 0); return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST) == 0 &&
uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN : DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN) != 0;
(uart_num == 1) ? SYSTEM_UART1_CLK_EN : case 1:
(uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0); return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST) == 0 &&
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 && DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN) != 0;
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0; case 2:
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_UART2_RST) == 0 &&
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_UART2_CLK_EN) != 0;
default:
abort();
}
} }
/** /**