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feat(clk): support for esp32s31 clock tree

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This commit is contained in:
Song Ruo Jing
2026-04-02 20:39:59 +08:00
parent 25cb4d0196
commit 50051b74a5
54 changed files with 1241 additions and 658 deletions
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components/esp_rom/CMakeLists.txt
+7
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@@ -306,6 +306,13 @@ else() # Regular app build
if(CONFIG_ESP32C61_REV_MIN_FULL GREATER_EQUAL 101)
rom_linker_script("eco4")
endif()
elseif(target STREQUAL "esp32s31")
# esp32s31.rom.api.ld has been split to several lds by components.
# esp32s31.rom.api.ld is still reserved to map the APIs
rom_linker_script("phy")
rom_linker_script("coexist")
rom_linker_script("net80211")
rom_linker_script("pp")
endif()
components/esp_rom/esp32s31/include/esp32s31/rom/rtc.h
+1 -2
View File
@@ -42,7 +42,7 @@ extern "C" {
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE4_REG Status of whether to disable LOG from ROM at bit[0]
* RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
@@ -52,7 +52,6 @@ extern "C" {
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_ENTRY_LENGTH_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG