Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-01 18:50:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

refactor(isp): avoid isp ll functions using hal.hw before initialization

Browse Source
This commit is contained in:
gaoxu
2026-04-24 11:20:00 +08:00
parent 334732144d
commit 4fd3d38d6c
2 changed files with 9 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32p4/include/hal/isp_ll.h
+4 -9
View File
@@ -252,10 +252,9 @@ typedef enum {
/**
* @brief Enable the bus clock for ISP module
*
* @param hw Hardware instance address
* @param en enable / disable
*/
static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
static inline void isp_ll_enable_module_clock(bool en)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_isp_clk_en = en;
}
@@ -266,10 +265,8 @@ static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
/**
* @brief Reset the ISP module
*
* @param hw Hardware instance address
*/
static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
static inline void isp_ll_reset_module_clock(void)
{
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 1;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 0;
@@ -282,10 +279,9 @@ static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
/**
* @brief Select ISP clock source
*
* @param hw Hardware instance address
* @param clk_src clock source, see valid sources in type `soc_periph_isp_clk_src_t`
*/
static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_src_t clk_src)
static inline void isp_ll_select_clk_source(soc_periph_isp_clk_src_t clk_src)
{
uint32_t clk_val = 0;
switch (clk_src) {
@@ -313,10 +309,9 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr
/**
* @brief Set ISP clock div
*
* @param hw Hardware instance address
* @param div Clock division with integral and decimal part
*/
static inline void isp_ll_set_clock_div(isp_dev_t *hw, const hal_utils_clk_div_t *clk_div)
static inline void isp_ll_set_clock_div(const hal_utils_clk_div_t *clk_div)
{
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= ISP_LL_TX_MAX_CLK_INT_DIV);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl26, reg_isp_clk_div_num, clk_div->integer - 1);