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feat(uart): add LP-UART GPIO support

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This commit is contained in:
gaoxu
2023-10-08 10:10:02 +08:00
parent 3e3e928209
commit 4f24f805cc
22 changed files with 353 additions and 397 deletions
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components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+5 -1
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@@ -1037,12 +1037,16 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
config SOC_UART_NUM
int
default 5
default 6
config SOC_UART_HP_NUM
int
default 5
config SOC_UART_LP_NUM
int
default 1
config SOC_UART_FIFO_LEN
int
default 128
components/soc/esp32p4/include/soc/clk_tree_defs.h
+1 -1
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@@ -153,8 +153,8 @@ typedef enum {
SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_LP_PLL, /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
SOC_MOD_CLK_LP_PLL,
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
components/soc/esp32p4/include/soc/soc_caps.h
+3 -5
View File
@@ -72,6 +72,7 @@
// #define SOC_PMU_SUPPORTED 1 //TODO: IDF-7531
// #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: IDF-7532
// #define SOC_ULP_LP_UART_SUPPORTED 1 //TODO: IDF-7533
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_SPIRAM_SUPPORTED 1
@@ -208,7 +209,6 @@
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// #define SOC_LP_GPIO_MATRIX_SUPPORTED (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
@@ -472,11 +472,9 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-P4 has 6 UARTs (5 HP UART, and 1 LP UART)
#define SOC_UART_NUM (5)
#define SOC_UART_NUM (6)
#define SOC_UART_HP_NUM (5)
// TODO: 7815
// The RTC GPIO and sigmap is not supported yet, so make SOC_UART_NUM->5 to avoid lp-uart build errors
// #define SOC_UART_LP_NUM (1U)
#define SOC_UART_LP_NUM (1U)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
components/soc/esp32p4/uart_periph.c
+30 -31
View File
@@ -180,38 +180,37 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
.irq = ETS_UART4_INTR_SOURCE,
.module = PERIPH_UART4_MODULE,
},
//TODO:IDF-7815
// { // LP UART0
// .pins = {
// [SOC_UART_TX_PIN_IDX] = {
// .default_gpio = LP_U0TXD_GPIO_NUM,
// .iomux_func = LP_U0TXD_MUX_FUNC,
// .input = 0,
// .signal = LP_UART_TXD_PAD_OUT_IDX,
// },
{ // LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = LP_UART_TXD_PAD_OUT_IDX,
},
// [SOC_UART_RX_PIN_IDX] = {
// .default_gpio = LP_U0RXD_GPIO_NUM,
// .iomux_func = LP_U0RXD_MUX_FUNC,
// .input = 1,
// .signal = LP_UART_RXD_PAD_IN_IDX,
// },
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = LP_UART_RXD_PAD_IN_IDX,
},
// [SOC_UART_RTS_PIN_IDX] = {
// .default_gpio = LP_U0RTS_GPIO_NUM,
// .iomux_func = LP_U0RTS_MUX_FUNC,
// .input = 0,
// .signal = LP_UART_RTSN_PAD_OUT_IDX,
// },
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = LP_UART_RTSN_PAD_OUT_IDX,
},
// [SOC_UART_CTS_PIN_IDX] = {
// .default_gpio = LP_U0CTS_GPIO_NUM,
// .iomux_func = LP_U0CTS_MUX_FUNC,
// .input = 1,
// .signal = LP_UART_CTSN_PAD_IN_IDX,
// },
// },
// .irq = ETS_LP_UART_INTR_SOURCE,
// .module = PERIPH_LP_UART0_MODULE,
// },
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = LP_UART_CTSN_PAD_IN_IDX,
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
.module = PERIPH_LP_UART0_MODULE,
},
};