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Merge branch 'feature/add_int_task_wdt_esp32c2' into 'master'

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WDT: implement interrupt wdt and task wdt for ESP32-C2

Closes IDF-4035, IDF-4205, and IDF-5055

See merge request espressif/esp-idf!18918
This commit is contained in:
Omar Chebib
2022-09-16 10:43:34 +08:00
parent 1146b83bf1 79598b1db7
commit 4f1a9e436e
45 changed files with 1046 additions and 206 deletions
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components/soc/esp32/include/soc/soc.h
+3
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@@ -403,3 +403,6 @@
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
components/soc/esp32c2/include/soc/soc.h
+4 -1
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@@ -211,7 +211,7 @@
//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
#define ETS_T1_WDT_INUM 24 // Remove TODO: IDF-4246
#define ETS_T0_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM 26
#define ETS_DPORT_INUM 28
@@ -234,3 +234,6 @@
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T0_WDT_INUM)
components/soc/esp32c2/include/soc/timer_group_struct.h
+2 -6
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@@ -173,11 +173,7 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
uint32_t reserved_0:13;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
@@ -239,7 +235,7 @@ typedef union {
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* MWDT clock prescaler value. MWDT clock period = 25 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
components/soc/esp32c3/include/soc/soc.h
+3
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@@ -235,3 +235,6 @@
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
components/soc/esp32h2/include/soc/soc.h
+3
View File
@@ -235,3 +235,6 @@
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
components/soc/esp32s2/include/soc/soc.h
+3
View File
@@ -265,3 +265,6 @@
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
components/soc/esp32s3/include/soc/soc.h
+3
View File
@@ -287,3 +287,6 @@
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)