Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-01 18:50:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(gdbstub): add f- and q-registers support

Browse Source
This commit is contained in:
Alexey Lapshin
2026-03-27 17:04:24 +08:00
committed by BOT
parent 1fc39de502
commit 4e2cb08534
14 changed files with 987 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_gdbstub/CMakeLists.txt
+2 -1
View File
@@ -18,7 +18,8 @@ if(CONFIG_IDF_TARGET_ARCH_XTENSA)
list(APPEND priv_includes "src/port/xtensa/include")
elseif(CONFIG_IDF_TARGET_ARCH_RISCV)
list(APPEND srcs "src/port/riscv/gdbstub_riscv.c"
"src/port/riscv/rv_decode.c")
"src/port/riscv/rv_decode.c"
"src/port/riscv/target_xml.c")
list(APPEND priv_includes "src/port/riscv/include")
endif()
components/esp_gdbstub/private_include/esp_gdbstub_common.h
+5 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -133,6 +133,9 @@ void esp_gdbstub_send_char(char c);
/** Send a string as part of the packet */
void esp_gdbstub_send_str(const char *s);
/** Send a string of limited length as part of a packet */
void esp_gdbstub_send_str_n(const char *c, size_t len);
/** Send a hex value as part of the packet */
void esp_gdbstub_send_hex(int val, int bits);
@@ -165,4 +168,4 @@ void esp_gdbstub_trigger_cpu(void);
* @param reg_index register index, depends on architecture
* @param value 32 bit data value
*/
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value);
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t *value_ptr);
components/esp_gdbstub/src/gdbstub.c
+69 -21
View File
@@ -24,6 +24,12 @@
#include "freertos/task.h"
#include "sdkconfig.h"
#if GDBSTUB_QXFER_FEATURES_ENABLED
#define GDBSTUB_QXFER_SUPPORTED_STR ";qXfer:features:read+"
#else
#define GDBSTUB_QXFER_SUPPORTED_STR ""
#endif
#ifdef CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
static inline int gdb_tid_to_task_index(int tid);
static inline int task_index_to_gdb_tid(int tid);
@@ -672,29 +678,35 @@ static void handle_C_command(const unsigned char *cmd, int len)
/* Set Register ... */
static void handle_P_command(const unsigned char *cmd, int len)
{
uint32_t reg_index = 0;
if (cmd[1] == '=') {
reg_index = esp_gdbstub_gethex(&cmd, 4);
cmd++;
} else if (cmd[2] == '=') {
reg_index = esp_gdbstub_gethex(&cmd, 8);
cmd++;
cmd++;
} else {
esp_gdbstub_send_str_packet("E02");
uint32_t reg_index = esp_gdbstub_gethex(&cmd, -1);
if (*cmd != '=') {
esp_gdbstub_send_str_packet("E.unexpected P packet format");
return;
}
uint32_t addr = esp_gdbstub_gethex(&cmd, -1);
/* The address comes with inverted byte order.*/
uint8_t *addr_ptr = (uint8_t *)&addr;
uint32_t p_address = 0;
uint8_t *p_addr_ptr = (uint8_t *)&p_address;
p_addr_ptr[3] = addr_ptr[0];
p_addr_ptr[2] = addr_ptr[1];
p_addr_ptr[1] = addr_ptr[2];
p_addr_ptr[0] = addr_ptr[3];
cmd++; /* skip '=' */
esp_gdbstub_set_register((esp_gdbstub_frame_t *)selected_task_frame, reg_index, p_address);
/* In general, we operate with 32-bit sized values here.
* However, some registers may be larger. For example, q registers are 128-bit sized. */
#if GDBSTUB_MAX_REGISTER_SIZE > 4
uint8_t value[GDBSTUB_MAX_REGISTER_SIZE * sizeof(uint32_t)] = {0};
uint32_t *value_ptr = (uint32_t *)value;
for(int i = 0; i < sizeof(value); i++) {
value[i] = (uint8_t) esp_gdbstub_gethex(&cmd, 8);
if (*cmd == 0)
break;
}
#else
uint32_t value;
uint32_t *value_ptr = &value;
value = gdbstub_hton(esp_gdbstub_gethex(&cmd, -1));
#endif
if (*cmd != 0) {
esp_gdbstub_send_str_packet("E.unexpected register size");
return;
}
esp_gdbstub_set_register((esp_gdbstub_frame_t *)selected_task_frame, reg_index, value_ptr);
/* Convert current register file to GDB*/
esp_gdbstub_frame_to_regfile((esp_gdbstub_frame_t *)selected_task_frame, gdb_local_regfile);
/* Sen OK response*/
@@ -706,10 +718,42 @@ static void handle_P_command(const unsigned char *cmd, int len)
static void handle_qSupported_command(const unsigned char *cmd, int len)
{
esp_gdbstub_send_start();
esp_gdbstub_send_str("qSupported:multiprocess+;swbreak-;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;no-resumed+");
esp_gdbstub_send_str("qSupported:multiprocess+;swbreak-;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;no-resumed+" GDBSTUB_QXFER_SUPPORTED_STR);
esp_gdbstub_send_end();
}
#if GDBSTUB_QXFER_FEATURES_ENABLED
static void qXfer_data(const char *ptr, uint32_t size, uint32_t offset, uint32_t length)
{
if (offset >= size) {
/* No data to send. */
esp_gdbstub_send_str_packet("l");
} else {
size_t len = MIN(length, size - offset);
esp_gdbstub_send_start();
esp_gdbstub_send_char('m');
esp_gdbstub_send_str_n(ptr + offset, len);
esp_gdbstub_send_end();
}
}
static void handle_qXfer_command(const unsigned char *cmd, int len)
{
uint32_t offset;
uint32_t length;
const char *target_feature_str = "qXfer:features:read:target.xml:";
const int target_feature_str_len = strlen(target_feature_str);
if (!command_name_matches(target_feature_str, cmd, target_feature_str_len)) {
/* Send empty packet for not supported requests. */
esp_gdbstub_send_str_packet(NULL);
}
cmd += target_feature_str_len;
offset = esp_gdbstub_gethex(&cmd, -1);
cmd++; /* skip ',' */
length = esp_gdbstub_gethex(&cmd, -1);
qXfer_data(target_xml, strlen(target_xml), offset, length);
}
#endif // GDBSTUB_QXFER_FEATURES_ENABLED
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
/** Handle a command received from gdb */
@@ -787,6 +831,10 @@ int esp_gdbstub_handle_command(unsigned char *cmd, int len)
return GDBSTUB_ST_CONT;
} else if (command_name_matches("qSupported", cmd, 10)) {
handle_qSupported_command(cmd, len);
#if GDBSTUB_QXFER_FEATURES_ENABLED
} else if (command_name_matches("qXfer", cmd, 5)) {
handle_qXfer_command(cmd, len);
#endif // GDBSTUB_QXFER_FEATURES_ENABLED
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
} else if (s_scratch.state != GDBSTUB_TASK_SUPPORT_DISABLED) {
components/esp_gdbstub/src/packet.c
+12 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -33,6 +33,16 @@ void esp_gdbstub_send_char(char c)
}
}
// Send a string of limited length as part of a packet
void esp_gdbstub_send_str_n(const char *c, size_t len)
{
while (*c != 0 && len != 0) {
esp_gdbstub_send_char(*c);
c++;
len--;
}
}
// Send a string as part of a packet
void esp_gdbstub_send_str(const char *c)
{
@@ -84,7 +94,7 @@ uint32_t esp_gdbstub_gethex(const unsigned char **ptr, int bits)
char c;
no = bits / 4;
if (bits == -1) {
no = 64;
no = 32 / 4;
}
for (i = 0; i < no; i++) {
c = **ptr;
components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c
+355 -16
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,12 +7,18 @@
#include <string.h>
#include "esp_gdbstub.h"
#include "esp_gdbstub_common.h"
#include "soc/soc_caps.h"
#include "esp_cpu.h"
#include "esp_ipc_isr.h"
#include "rv_decode.h"
#include "sdkconfig.h"
#include "esp_private/crosscore_int.h"
#include "esp_private/freertos_debug.h"
#include "freertos/portmacro.h"
#include "freertos/FreeRTOS.h"
#include "freertos/FreeRTOSConfig.h"
#define GDBSTUB_CSA_NOT_INITIALIZED ((void *) 0xFFFFFFFF)
extern volatile esp_gdbstub_frame_t *temp_regs_frame;
@@ -21,6 +27,183 @@ static inline void init_regfile(esp_gdbstub_gdb_regfile_t *dst)
memset(dst, 0, sizeof(*dst));
}
#if SOC_CPU_HAS_FPU
static void esp_gdbstub_fpu_regs_to_regfile (esp_gdbstub_gdb_regfile_t *dst)
{
/*
* NOTE: The GDB stub logic executes within an ISR, where coprocessors are disabled.
* Therefore, we must enable the coprocessor before reading or writing its registers.
*/
rv_utils_enable_fpu();
__asm__ volatile ("fsw ft0, %0" : "=m" (dst->f.ft0));
__asm__ volatile ("fsw ft1, %0" : "=m" (dst->f.ft1));
__asm__ volatile ("fsw ft2, %0" : "=m" (dst->f.ft2));
__asm__ volatile ("fsw ft3, %0" : "=m" (dst->f.ft3));
__asm__ volatile ("fsw ft4, %0" : "=m" (dst->f.ft4));
__asm__ volatile ("fsw ft5, %0" : "=m" (dst->f.ft5));
__asm__ volatile ("fsw ft6, %0" : "=m" (dst->f.ft6));
__asm__ volatile ("fsw ft7, %0" : "=m" (dst->f.ft7));
__asm__ volatile ("fsw fs0, %0" : "=m" (dst->f.fs0));
__asm__ volatile ("fsw fs1, %0" : "=m" (dst->f.fs1));
__asm__ volatile ("fsw fa0, %0" : "=m" (dst->f.fa0));
__asm__ volatile ("fsw fa1, %0" : "=m" (dst->f.fa1));
__asm__ volatile ("fsw fa2, %0" : "=m" (dst->f.fa2));
__asm__ volatile ("fsw fa3, %0" : "=m" (dst->f.fa3));
__asm__ volatile ("fsw fa4, %0" : "=m" (dst->f.fa4));
__asm__ volatile ("fsw fa5, %0" : "=m" (dst->f.fa5));
__asm__ volatile ("fsw fa6, %0" : "=m" (dst->f.fa6));
__asm__ volatile ("fsw fa7, %0" : "=m" (dst->f.fa7));
__asm__ volatile ("fsw fs2, %0" : "=m" (dst->f.fs2));
__asm__ volatile ("fsw fs3, %0" : "=m" (dst->f.fs3));
__asm__ volatile ("fsw fs4, %0" : "=m" (dst->f.fs4));
__asm__ volatile ("fsw fs5, %0" : "=m" (dst->f.fs5));
__asm__ volatile ("fsw fs6, %0" : "=m" (dst->f.fs6));
__asm__ volatile ("fsw fs7, %0" : "=m" (dst->f.fs7));
__asm__ volatile ("fsw fs8, %0" : "=m" (dst->f.fs8));
__asm__ volatile ("fsw fs9, %0" : "=m" (dst->f.fs9));
__asm__ volatile ("fsw fs10, %0" : "=m" (dst->f.fs10));
__asm__ volatile ("fsw fs11, %0" : "=m" (dst->f.fs11));
__asm__ volatile ("fsw ft8, %0" : "=m" (dst->f.ft8));
__asm__ volatile ("fsw ft9, %0" : "=m" (dst->f.ft9));
__asm__ volatile ("fsw ft10, %0" : "=m" (dst->f.ft10));
__asm__ volatile ("fsw ft11, %0" : "=m" (dst->f.ft11));
__asm__ volatile ("csrr %0, fcsr" : "=r" (dst->f.fcsr));
rv_utils_disable_fpu();
}
#endif
#if SOC_CPU_HAS_PIE
static void esp_gdbstub_pie_regs_to_regfile (esp_gdbstub_gdb_regfile_t *dst)
{
/*
* NOTE: The GDB stub logic executes within an ISR, where coprocessors are disabled.
* Therefore, we must enable the coprocessor before reading or writing its registers.
*/
rv_utils_enable_pie();
register void* ptr asm("a5") = &dst->pie;
__asm__ volatile ("esp.vst.128.ip q0, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q1, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q2, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q3, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q4, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q5, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q6, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.vst.128.ip q7, %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.qacc.l.l.128.ip %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.qacc.l.h.128.ip %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.qacc.h.l.128.ip %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.qacc.h.h.128.ip %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.ua.state.ip %0, 16" :: "r" (ptr));
__asm__ volatile ("esp.st.s.xacc.ip %0, 0" :: "r" (ptr));
rv_utils_disable_pie();
}
#endif
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
const StaticTask_t *esp_gdbstub_find_tcb_by_frame(const esp_gdbstub_frame_t *frame)
{
/*
* Determine which task owns the current frame.
* Perform a search across all tasks, as GDBstub may not include task information
* if configured with ESP_GDBSTUB_SUPPORT_TASKS disabled.
*/
TaskIterator_t xTaskIter = {0}; /* Point to the first task list */
while(xTaskGetNext(&xTaskIter) != -1)
{
StaticTask_t *tcb = (StaticTask_t *)xTaskIter.pxTaskHandle;
if (tcb->pxDummy1 /* pxTopOfStack */ == frame) {
return tcb;
}
}
return NULL; /* Task not found. */
}
static void *esp_gdbstub_coproc_saved_area(const StaticTask_t *tcb, int coproc, bool is_read) {
/*
* Coprocessors have lazy register saving mechanism:
* 1. Defer saving coprocessor registers until a task actually uses a coprocessor instruction.
* This triggers an exception when the instruction is executed.
* 2. In the exception handler:
* - Enable the coprocessor and designate the task as the new coprocessor owner.
* - If another task previously owned the coprocessor, save its registers.
* - Restore the coprocessor registers for the new owner before execution resumes.
*
*
* To determine whether to read/write coprocessor registers directly or use stack memory:
* - Check if the current task is the coprocessor owner:
* - Yes: Perform direct read/write operations.
* - No: Read/write from the stack.
*/
RvCoprocSaveArea* pxPortGetCoprocArea(StaticTask_t* task, bool allocate, int coproc);
RvCoprocSaveArea* csa;
extern StaticTask_t* port_uxCoprocOwner[portNUM_PROCESSORS][SOC_CPU_COPROC_NUM];
uint32_t core = rv_utils_get_core_id();
uint32_t coproc_bit;
if (port_uxCoprocOwner[core][coproc] == tcb) {
return NULL;
}
csa = pxPortGetCoprocArea((StaticTask_t*)tcb, false, coproc);
if (csa->sa_coprocs[coproc]) {
return csa->sa_coprocs[coproc];
}
if (is_read) {
/* Don't allocate csa for coprocessor for read. (Just return zeroed registers) */
return GDBSTUB_CSA_NOT_INITIALIZED;
}
/*
* Ignore 'csa->sa_enable' flag to read/write from the frame if the coprocessor has not been used by this task yet.
* This ensures that the registers are correctly restored when the task's coprocessor context is switched.
* That's why true is passed to the allocate parameter of pxPortGetCoprocArea.
*/
/* TODO: IDF-12550. Provide correct read/write access for coprocessor owned by another CPU.
* Accessing registers in stack-frame is not correct in this case.
*/
csa = pxPortGetCoprocArea((StaticTask_t*)tcb, true, coproc);
coproc_bit = 1 << coproc;
if (!(csa->sa_enable & coproc_bit)) {
uint32_t sa_coproc_size = coproc == 0 ? RV_COPROC0_SIZE : (coproc == 1 ? RV_COPROC1_SIZE : RV_COPROC2_SIZE);
/* coproc registers were not saved for this task yet. Initialize with zeroes. */
memset(csa->sa_coprocs[coproc], 0, sa_coproc_size);
csa->sa_enable |= coproc_bit;
}
return csa->sa_coprocs[coproc];
}
static void esp_gdbstub_coproc_regs_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst)
{
const StaticTask_t *tcb = esp_gdbstub_find_tcb_by_frame(frame);
void *csa;
#if SOC_CPU_HAS_FPU
csa = esp_gdbstub_coproc_saved_area(tcb, FPU_COPROC_IDX, true);
if (csa == NULL) {
esp_gdbstub_fpu_regs_to_regfile(dst);
} else if (csa == GDBSTUB_CSA_NOT_INITIALIZED) {
memset(&dst->f, 0, sizeof(dst->f));
} else {
memcpy(&dst->f, csa, sizeof(dst->f));
}
#endif
#if SOC_CPU_HAS_PIE
csa = esp_gdbstub_coproc_saved_area(tcb, PIE_COPROC_IDX, true);
if (csa == NULL) {
esp_gdbstub_pie_regs_to_regfile(dst);
} else if (csa == GDBSTUB_CSA_NOT_INITIALIZED) {
memset(&dst->pie, 0, sizeof(dst->pie));
} else {
memcpy(&dst->pie, csa, sizeof(dst->pie));
}
#endif
}
#endif /* SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE */
void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst)
{
init_regfile(dst);
@@ -29,28 +212,21 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_
// We omit register x0 here since it's the zero register and always hard-wired to 0.
// See The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213 for more details.
memcpy(&(dst->x[1]), &frame->ra, sizeof(uint32_t) * 31);
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
esp_gdbstub_coproc_regs_to_regfile(frame, dst);
#endif
}
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS || CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
/* Represents FreeRTOS TCB structure */
typedef struct {
uint8_t *top_of_stack;
/* Other members aren't needed */
} dummy_tcb_t;
#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
void esp_gdbstub_tcb_to_regfile(TaskHandle_t tcb, esp_gdbstub_gdb_regfile_t *dst)
{
const dummy_tcb_t *dummy_tcb = (const dummy_tcb_t *) tcb;
const RvExcFrame *frame = (RvExcFrame *) dummy_tcb->top_of_stack;
const RvExcFrame *frame = (RvExcFrame *) ((StaticTask_t *) tcb)->pxDummy1 /* top_of_stack */;
esp_gdbstub_frame_to_regfile(frame, dst);
}
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS || CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
int esp_gdbstub_get_signal(const esp_gdbstub_frame_t *frame)
{
@@ -87,8 +263,8 @@ void esp_gdbstub_int(__attribute__((unused)) void *frame)
/* Pointer to saved frame is in pxCurrentTCB
* See rtos_int_enter function
*/
dummy_tcb_t *tcb = (dummy_tcb_t *)pvTaskGetCurrentTCBForCore(esp_cpu_get_core_id());
gdbstub_handle_uart_int((esp_gdbstub_frame_t *)tcb->top_of_stack);
StaticTask_t *tcb = (StaticTask_t *)pvTaskGetCurrentTCBForCore(esp_cpu_get_core_id());
gdbstub_handle_uart_int((esp_gdbstub_frame_t *)tcb->pxDummy1 /* top_of_stack */);
}
void esp_gdbstub_init_dports(void)
@@ -152,8 +328,168 @@ void esp_gdbstub_trigger_cpu(void)
#endif
}
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value)
#if SOC_CPU_HAS_FPU
void esp_gdbstub_set_fpu_register(uint32_t reg_index, uint32_t value)
{
/*
* NOTE: The GDB stub logic executes within an ISR, where coprocessors are disabled.
* Therefore, we must enable the coprocessor before reading or writing its registers.
*/
rv_utils_enable_fpu();
if (reg_index == 0) {
__asm__ volatile ("flw ft0, %0" : "=m" (value));
} else if (reg_index == 1) {
__asm__ volatile ("flw ft1, %0" : "=m" (value));
} else if (reg_index == 2) {
__asm__ volatile ("flw ft2, %0" : "=m" (value));
} else if (reg_index == 3) {
__asm__ volatile ("flw ft3, %0" : "=m" (value));
} else if (reg_index == 4) {
__asm__ volatile ("flw ft4, %0" : "=m" (value));
} else if (reg_index == 5) {
__asm__ volatile ("flw ft5, %0" : "=m" (value));
} else if (reg_index == 6) {
__asm__ volatile ("flw ft6, %0" : "=m" (value));
} else if (reg_index == 7) {
__asm__ volatile ("flw ft7, %0" : "=m" (value));
} else if (reg_index == 8) {
__asm__ volatile ("flw fs0, %0" : "=m" (value));
} else if (reg_index == 9) {
__asm__ volatile ("flw fs1, %0" : "=m" (value));
} else if (reg_index == 10) {
__asm__ volatile ("flw fa0, %0" : "=m" (value));
} else if (reg_index == 11) {
__asm__ volatile ("flw fa1, %0" : "=m" (value));
} else if (reg_index == 12) {
__asm__ volatile ("flw fa2, %0" : "=m" (value));
} else if (reg_index == 13) {
__asm__ volatile ("flw fa3, %0" : "=m" (value));
} else if (reg_index == 14) {
__asm__ volatile ("flw fa4, %0" : "=m" (value));
} else if (reg_index == 15) {
__asm__ volatile ("flw fa5, %0" : "=m" (value));
} else if (reg_index == 16) {
__asm__ volatile ("flw fa6, %0" : "=m" (value));
} else if (reg_index == 17) {
__asm__ volatile ("flw fa7, %0" : "=m" (value));
} else if (reg_index == 18) {
__asm__ volatile ("flw fs2, %0" : "=m" (value));
} else if (reg_index == 19) {
__asm__ volatile ("flw fs3, %0" : "=m" (value));
} else if (reg_index == 20) {
__asm__ volatile ("flw fs4, %0" : "=m" (value));
} else if (reg_index == 21) {
__asm__ volatile ("flw fs5, %0" : "=m" (value));
} else if (reg_index == 22) {
__asm__ volatile ("flw fs6, %0" : "=m" (value));
} else if (reg_index == 23) {
__asm__ volatile ("flw fs7, %0" : "=m" (value));
} else if (reg_index == 24) {
__asm__ volatile ("flw fs8, %0" : "=m" (value));
} else if (reg_index == 25) {
__asm__ volatile ("flw fs9, %0" : "=m" (value));
} else if (reg_index == 26) {
__asm__ volatile ("flw fs10, %0" : "=m" (value));
} else if (reg_index == 27) {
__asm__ volatile ("flw fs11, %0" : "=m" (value));
} else if (reg_index == 28) {
__asm__ volatile ("flw ft8, %0" : "=m" (value));
} else if (reg_index == 29) {
__asm__ volatile ("flw ft9, %0" : "=m" (value));
} else if (reg_index == 30) {
__asm__ volatile ("flw ft10, %0" : "=m" (value));
} else if (reg_index == 31) {
__asm__ volatile ("flw ft11, %0" : "=m" (value));
} else if (reg_index == 32) {
__asm__ volatile ("csrw fcsr, %0" : : "r" (value));
}
rv_utils_disable_fpu();
}
#endif /* SOC_CPU_HAS_FPU */
#if SOC_CPU_HAS_PIE
void esp_gdbstub_set_pie_register(uint32_t reg_index, uint32_t *value_ptr)
{
/*
* NOTE: The GDB stub logic executes within an ISR, where coprocessors are disabled.
* Therefore, we must enable the coprocessor before reading or writing its registers.
*/
register void *ptr asm("a5") = value_ptr;
rv_utils_enable_pie();
if (reg_index == 0) {
__asm__ volatile ("esp.vld.128.ip q0, %0, 0" :: "r" (ptr));
} else if (reg_index == 1) {
__asm__ volatile ("esp.vld.128.ip q1, %0, 0" :: "r" (ptr));
} else if (reg_index == 2) {
__asm__ volatile ("esp.vld.128.ip q2, %0, 0" :: "r" (ptr));
} else if (reg_index == 3) {
__asm__ volatile ("esp.vld.128.ip q3, %0, 0" :: "r" (ptr));
} else if (reg_index == 4) {
__asm__ volatile ("esp.vld.128.ip q4, %0, 0" :: "r" (ptr));
} else if (reg_index == 5) {
__asm__ volatile ("esp.vld.128.ip q5, %0, 0" :: "r" (ptr));
} else if (reg_index == 6) {
__asm__ volatile ("esp.vld.128.ip q6, %0, 0" :: "r" (ptr));
} else if (reg_index == 7) {
__asm__ volatile ("esp.vld.128.ip q7, %0, 0" :: "r" (ptr));
} else if (reg_index == 8) {
__asm__ volatile ("esp.ld.qacc.l.l.128.ip %0, 0" :: "r" (ptr));
} else if (reg_index == 9) {
__asm__ volatile ("esp.ld.qacc.l.h.128.ip %0, 0" :: "r" (ptr));
} else if (reg_index == 10) {
__asm__ volatile ("esp.ld.qacc.h.l.128.ip %0, 0" :: "r" (ptr));
} else if (reg_index == 11) {
__asm__ volatile ("esp.ld.qacc.h.h.128.ip %0, 0" :: "r" (ptr));
} else if (reg_index == 12) {
__asm__ volatile ("esp.ld.ua.state.ip %0, 0" :: "r" (ptr));
} else if (reg_index == 13) {
__asm__ volatile ("esp.ld.xacc.ip %0, 0" :: "r" (ptr));
}
rv_utils_disable_pie();
}
#endif /* SOC_CPU_HAS_PIE */
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
void esp_gdbstub_set_coproc_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t *value_ptr) {
const StaticTask_t *tcb = esp_gdbstub_find_tcb_by_frame(frame);
uint32_t *csa; /* points to coprocessor registers data. */
#if SOC_CPU_HAS_FPU
if (reg_index >= 33 && reg_index <= 68) {
reg_index -= 33;
if (reg_index > 32 /* fcsr */) {
reg_index = 32;
}
csa = esp_gdbstub_coproc_saved_area(tcb, FPU_COPROC_IDX, false);
if (csa == NULL) {
esp_gdbstub_set_fpu_register(reg_index, *value_ptr);
} else {
csa[reg_index] = *value_ptr;
}
return;
}
#endif
#if SOC_CPU_HAS_PIE
if (reg_index >= 4211 && reg_index <= 4224) {
reg_index -= 4211;
csa = esp_gdbstub_coproc_saved_area(tcb, PIE_COPROC_IDX, false);
if (csa == NULL) {
esp_gdbstub_set_pie_register(reg_index, value_ptr);
} else {
if (reg_index < 13) { /* 128-bit registers: q, qacc, ua_state */
memcpy(&csa[reg_index * 4], value_ptr, sizeof(uint32_t) * 4);
} else { /* 40-bit regiseter: xacc */
memcpy(&csa[4 * 13], value_ptr, sizeof(uint8_t) * 5);
}
}
}
#endif
}
#endif /* SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE */
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t *value_ptr)
{
uint32_t value = *value_ptr;
/* RISC-V base ISA has registers x0-x31 */
if (reg_index == 0) { /* skip zero-wired register */
return;
@@ -162,4 +498,7 @@ void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, ui
} else if (reg_index == 32) { /* register 32 is PC */
frame->mepc = value;
}
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
esp_gdbstub_set_coproc_register(frame, reg_index, value_ptr);
#endif
}
components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_arch.h
+30 -1
View File
@@ -1,12 +1,22 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <assert.h>
#include <stdint.h>
#include "soc/soc_caps.h"
#include "riscv/rvruntime-frames.h"
#include "sdkconfig.h"
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
#define GDBSTUB_QXFER_FEATURES_ENABLED 1
#if SOC_CPU_HAS_PIE
#define GDBSTUB_MAX_REGISTER_SIZE 16
#endif
#endif
#ifdef __cplusplus
extern "C" {
@@ -14,12 +24,31 @@ extern "C" {
typedef RvExcFrame esp_gdbstub_frame_t;
#if SOC_CPU_HAS_FPU
static_assert(sizeof(RvFPUSaveArea) == (32 + 1) * sizeof(uint32_t),
"Expected 32 float registers + fcsr. Please update gdbstub internals.");
#endif
#if SOC_CPU_HAS_PIE
static_assert(sizeof(RvPIESaveArea) == ((8 + 4 + 1) * (4 * sizeof(uint32_t))) + (2 * sizeof(uint32_t)),
"Expected 8 Q regs, QACC, UA_STATE, XACC. Please update gdbstub internals.");
#endif
/* GDB regfile structure, configuration dependent */
typedef struct {
uint32_t x[32];
uint32_t pc;
#if SOC_CPU_HAS_FPU
RvFPUSaveArea f;
#endif
#if SOC_CPU_HAS_PIE
RvPIESaveArea pie;
#endif
} esp_gdbstub_gdb_regfile_t;
#if GDBSTUB_QXFER_FEATURES_ENABLED
extern const char target_xml[];
#endif
#ifdef __cplusplus
}
#endif
components/esp_gdbstub/src/port/riscv/rv_decode.c
+1
View File
@@ -5,6 +5,7 @@
*/
#include "rv_decode.h"
#include "riscv/csr.h"
#include "riscv/csr_hwlp.h"
#include "soc/soc_caps.h"
components/esp_gdbstub/src/port/riscv/target_xml.c
+116
View File
@@ -0,0 +1,116 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#if SOC_CPU_HAS_FPU || SOC_CPU_HAS_PIE
const char target_xml[] =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target>"
"<architecture>riscv</architecture>"
"<feature name=\"org.gnu.gdb.riscv.cpu\">"
"<reg name=\"zero\" bitsize=\"32\"/>"
"<reg name=\"ra\" bitsize=\"32\" type=\"code_ptr\"/>"
"<reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\"gp\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\"tp\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\"t0\" bitsize=\"32\"/>"
"<reg name=\"t1\" bitsize=\"32\"/>"
"<reg name=\"t2\" bitsize=\"32\"/>"
"<reg name=\"fp\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\"s1\" bitsize=\"32\"/>"
"<reg name=\"a0\" bitsize=\"32\"/>"
"<reg name=\"a1\" bitsize=\"32\"/>"
"<reg name=\"a2\" bitsize=\"32\"/>"
"<reg name=\"a3\" bitsize=\"32\"/>"
"<reg name=\"a4\" bitsize=\"32\"/>"
"<reg name=\"a5\" bitsize=\"32\"/>"
"<reg name=\"a6\" bitsize=\"32\"/>"
"<reg name=\"a7\" bitsize=\"32\"/>"
"<reg name=\"s2\" bitsize=\"32\"/>"
"<reg name=\"s3\" bitsize=\"32\"/>"
"<reg name=\"s4\" bitsize=\"32\"/>"
"<reg name=\"s5\" bitsize=\"32\"/>"
"<reg name=\"s6\" bitsize=\"32\"/>"
"<reg name=\"s7\" bitsize=\"32\"/>"
"<reg name=\"s8\" bitsize=\"32\"/>"
"<reg name=\"s9\" bitsize=\"32\"/>"
"<reg name=\"s10\" bitsize=\"32\"/>"
"<reg name=\"s11\" bitsize=\"32\"/>"
"<reg name=\"t3\" bitsize=\"32\"/>"
"<reg name=\"t4\" bitsize=\"32\"/>"
"<reg name=\"t5\" bitsize=\"32\"/>"
"<reg name=\"t6\" bitsize=\"32\"/>"
"<reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
"</feature>"
#if SOC_CPU_HAS_FPU
"<feature name=\"org.gnu.gdb.riscv.fpu\">"
"<reg name=\"ft0\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft1\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft2\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft3\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft4\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft5\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft6\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft7\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs0\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs1\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa0\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa1\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa2\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa3\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa4\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa5\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa6\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fa7\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs2\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs3\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs4\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs5\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs6\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs7\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs8\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs9\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs10\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fs11\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft8\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft9\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft10\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"ft11\" bitsize=\"32\" type=\"float\"/>"
"<reg name=\"fcsr\" bitsize=\"32\" regnum=\"68\"/>"
"</feature>"
#endif /* SOC_CPU_HAS_FPU */
#if SOC_CPU_HAS_PIE
"<feature name=\"org.gnu.gdb.riscv.xesppie\">"
"<vector id=\"v5i8\" type=\"int8\" count=\"5\"/>"
"<vector id=\"v3i8\" type=\"int8\" count=\"3\"/>"
"<vector id=\"v4i32\" type=\"int32\" count=\"4\"/>"
"<vector id=\"v2i64\" type=\"int64\" count=\"2\"/>"
"<union id=\"vec128\">"
"<field name=\"v4_int32\" type=\"v4i32\"/>"
"<field name=\"v2_int64\" type=\"v2i64\"/>"
"<field name=\"uint128\" type=\"uint128\"/>"
"</union>"
"<reg name=\"q0\" bitsize=\"128\" type=\"vec128\" group=\"vector\" regnum=\"4211\"/>"
"<reg name=\"q1\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q2\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q3\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q4\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q5\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q6\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"q7\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"qacc_l_l\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"qacc_l_h\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"qacc_h_l\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"qacc_h_h\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"ua_state\" bitsize=\"128\" type=\"vec128\" group=\"vector\"/>"
"<reg name=\"xacc\" bitsize=\"40\" type=\"v5i8\" group=\"vector\"/>"
"<reg name=\"misc\" bitsize=\"24\" type=\"v3i8\" group=\"vector\"/>" /* make GDB happy about "Truncated register 4207 in remote 'g' packet" */
"</feature>"
#endif /* SOC_CPU_HAS_PIE */
"</target>";
#endif
components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c
+22 -27
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -349,78 +349,73 @@ void esp_gdbstub_trigger_cpu(void)
*
* */
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value)
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t *value_ptr)
{
uint32_t temp_fpu_value = value;
float *ptr0;
asm volatile ("mov %0, %1" : "=a" (ptr0) : "a" (&temp_fpu_value));
uint32_t value = *value_ptr;
if (reg_index == 0) {
frame->pc = value;
} else if (reg_index > 0 && (reg_index <= 27)) {
(&frame->a0)[reg_index - 1] = value;
}
#if XCHAL_HAVE_FP
void *ptr1;
uint32_t cp_enabled;
RSR(CPENABLE, cp_enabled);
if (cp_enabled != 0) {
if (reg_index == 87) {
asm volatile ("lsi f0, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f0, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 88) {
asm volatile ("lsi f1, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f1, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 89) {
asm volatile ("lsi f2, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f2, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 90) {
asm volatile ("lsi f3, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f3, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 91) {
asm volatile ("lsi f4, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f4, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 92) {
asm volatile ("lsi f5, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f5, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 93) {
asm volatile ("lsi f6, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f6, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 94) {
asm volatile ("lsi f7, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f7, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 95) {
asm volatile ("lsi f8, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f8, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 96) {
asm volatile ("lsi f9, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f9, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 97) {
asm volatile ("lsi f10, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f10, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 98) {
asm volatile ("lsi f11, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f11, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 99) {
asm volatile ("lsi f12, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f12, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 100) {
asm volatile ("lsi f13, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f13, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 101) {
asm volatile ("lsi f14, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f14, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 102) {
asm volatile ("lsi f15, %0, 0" :: "a" (ptr0));
asm volatile ("lsi f15, %0, 0" :: "a" (value_ptr));
}
if (reg_index == 103) {
asm volatile ("l32i %0, %1, 0" : "=a" (ptr1) : "a" (ptr0));
asm volatile ("wur.FCR %0" : "=a" (ptr1));
asm volatile ("wur.FCR %0" : "=a" (value));
}
if (reg_index == 104) {
asm volatile ("l32i %0, %1, 0" : "=a" (ptr1) : "a" (ptr0));
asm volatile ("wur.FSR %0" : "=a" (ptr1));
asm volatile ("wur.FSR %0" : "=a" (value));
}
}
#endif // XCHAL_HAVE_FP
components/esp_gdbstub/test_gdbstub_host/rv_decode/include/sdkconfig.h
+1 -1
View File
@@ -5,4 +5,4 @@
*/
#pragma once
#define CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
#define CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME 1