diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h
index 2a378006a25..d8da5869512 100644
--- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h
+++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +14,7 @@ extern "C" {
 #include <stdbool.h>
 #include "hal/i2c_types.h"
 #include "esp_err.h"
+#include "hal/i2c_ll.h"
 
 /**
  * @brief Read from I2C device
@@ -99,6 +100,34 @@ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t d
  */
 void lp_core_i2c_master_set_ack_check_en(i2c_port_t lp_i2c_num, bool ack_check_en);
 
+#if SOC_LP_I2C_SUPPORTED
+/**
+ * @brief Enable LP I2C master-related interrupts at the peripheral
+ *
+ * Enables the same interrupt sources used by the LP I2C master driver (see I2C_LL_MASTER_EVENT_INTR).
+ *
+ * @param lp_i2c_num    Must be the LP I2C port (e.g. LP_I2C_NUM_0), not an HP I2C port.
+ * @param mask          Interrupt mask needs to be enabled
+ */
+static inline void ulp_lp_core_lp_i2c_intr_enable(i2c_port_t lp_i2c_num, uint32_t mask)
+{
+    HAL_ASSERT(lp_i2c_num == LP_I2C_NUM_0);
+    i2c_ll_enable_intr_mask(I2C_LL_GET_HW(lp_i2c_num), mask);
+}
+
+/**
+ * @brief Disable LP I2C master-related interrupts at the peripheral
+ *
+ * @param lp_i2c_num    Must be the LP I2C port (e.g. LP_I2C_NUM_0), not an HP I2C port.
+ * @param mask          Interrupt mask needs to be disabled
+ */
+static inline void ulp_lp_core_lp_i2c_intr_disable(i2c_port_t lp_i2c_num, uint32_t mask)
+{
+    HAL_ASSERT(lp_i2c_num == LP_I2C_NUM_0);
+    i2c_ll_disable_intr_mask(I2C_LL_GET_HW(lp_i2c_num), mask);
+}
+#endif /* SOC_LP_I2C_SUPPORTED */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h
index 5b125e5c0f4..f8f06e5040d 100644
--- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h
+++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,31 @@ extern "C" {
 #include <stdint.h>
 #include "esp_err.h"
 #include "hal/uart_types.h"
+#include "hal/uart_ll.h"
+
+#if SOC_LP_UART_SUPPORTED
+/**
+ * @brief LP UART peripheral interrupt enable
+ * @param uart_num UART port number
+ * @param mask Interrupt mask needs to be enabled
+ */
+static inline void ulp_lp_core_lp_uart_intr_enable(uart_port_t uart_num, uint32_t mask)
+{
+    HAL_ASSERT(uart_num == LP_UART_NUM_0);
+    uart_ll_ena_intr_mask(UART_LL_GET_HW(uart_num), mask);
+}
+
+/**
+ * @brief LP UART peripheral interrupt disable
+ * @param uart_num UART port number
+ * @param mask Interrupt mask needs to be disabled
+ */
+static inline void ulp_lp_core_lp_uart_intr_disable(uart_port_t uart_num, uint32_t mask)
+{
+    HAL_ASSERT(uart_num == LP_UART_NUM_0);
+    uart_ll_disable_intr_mask(UART_LL_GET_HW(uart_num), mask);
+}
+#endif /* SOC_LP_UART_SUPPORTED */
 
 /**
  * @brief Send data to the LP UART port if there is space available in the Tx FIFO
diff --git a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_adc_shared.h b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_adc_shared.h
index 310caa0b1a9..4899eb50ed9 100644
--- a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_adc_shared.h
+++ b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_adc_shared.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
 #include <stdint.h>
+#include <stdbool.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -14,6 +15,9 @@ extern "C" {
 #include "esp_err.h"
 #include "hal/adc_types.h"
 #include "esp_adc/adc_oneshot.h"
+#if SOC_LP_ADC_SUPPORTED
+#include "soc/lp_adc_struct.h"
+#endif
 
 /**
  * @brief LP ADC channel configurations
@@ -108,6 +112,23 @@ esp_err_t lp_core_lp_adc_read_channel_raw(adc_unit_t unit_id, adc_channel_t chan
  */
 esp_err_t lp_core_lp_adc_read_channel_converted(adc_unit_t unit_id, adc_channel_t channel, int *voltage_mv);
 
+#if SOC_LP_ADC_SUPPORTED
+/**
+ * @brief Enable or disable the LP ADC conversion-done interrupt to the LP CPU (LP_ADC int_ena cocpu_saradc1/2_int_ena).
+ *
+ * @param unit_id  ADC unit (ADC_UNIT_1 / ADC_UNIT_2)
+ * @param enable   true to enable, false to disable
+ */
+static inline void ulp_lp_core_lp_adc_intr_enable(adc_unit_t unit_id, bool enable)
+{
+    if (unit_id == ADC_UNIT_1) {
+        LP_ADC.int_ena.cocpu_saradc1_int_ena = enable;
+    } else if (unit_id == ADC_UNIT_2) {
+        LP_ADC.int_ena.cocpu_saradc2_int_ena = enable;
+    }
+}
+#endif /* SOC_LP_ADC_SUPPORTED */
+
 #ifdef __cplusplus
 }
 #endif