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refactor(esp_hal_security): Updated esp_hal_security build and includes
This commit is contained in:
Aditya Patwardhan
@@ -0,0 +1,188 @@
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/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <string.h>
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#include "hal/assert.h"
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#include "hal/ecc_types.h"
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#include "soc/ecc_mult_reg.h"
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#include "soc/system_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ECC_PARAM_PX = 0x0,
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ECC_PARAM_PY,
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ECC_PARAM_K,
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} ecc_ll_param_t;
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/**
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* @brief Enable the bus clock for ECC peripheral module
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*
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* @param true to enable the module, false to disable the module
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*/
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static inline void ecc_ll_enable_bus_clock(bool enable)
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{
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SYSTEM.perip_clk_en1.crypto_ecc_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ecc_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ecc_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the ECC peripheral module
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*/
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static inline void ecc_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en1.crypto_ecc_rst = 1;
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SYSTEM.perip_rst_en1.crypto_ecc_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ecc_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ecc_ll_reset_register(__VA_ARGS__); \
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} while(0)
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static inline void ecc_ll_power_up(void) {}
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static inline void ecc_ll_power_down(void) {}
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static inline void ecc_ll_enable_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
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}
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static inline void ecc_ll_disable_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
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}
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static inline void ecc_ll_clear_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
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}
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static inline void ecc_ll_set_mode(ecc_mode_t mode)
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{
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switch (mode) {
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case ECC_MODE_POINT_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
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break;
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case ECC_MODE_VERIFY:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
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break;
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case ECC_MODE_VERIFY_THEN_POINT_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
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break;
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default:
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HAL_ASSERT(false && "Unsupported mode");
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break;
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}
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}
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static inline void ecc_ll_set_curve(ecc_curve_t curve)
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{
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switch (curve) {
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case ECC_CURVE_SECP256R1:
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
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break;
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case ECC_CURVE_SECP192R1:
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REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
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break;
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default:
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HAL_ASSERT(false && "Unsupported curve");
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return;
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}
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}
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static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
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{
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uint32_t reg;
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uint32_t word;
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switch (param) {
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case ECC_PARAM_PX:
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reg = ECC_MULT_PX_1_REG;
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break;
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case ECC_PARAM_PY:
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reg = ECC_MULT_PY_1_REG;
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break;
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case ECC_PARAM_K:
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reg = ECC_MULT_K_1_REG;
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break;
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default:
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HAL_ASSERT(false && "Invalid parameter");
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return;
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}
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for (int i = 0; i < len; i += 4) {
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memcpy(&word, buf + i, 4);
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REG_WRITE(reg + i, word);
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}
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}
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static inline void ecc_ll_start_calc(void)
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{
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
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}
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static inline int ecc_ll_is_calc_finished(void)
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{
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return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
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}
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static inline ecc_mode_t ecc_ll_get_mode(void)
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{
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return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
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}
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static inline int ecc_ll_get_verification_result(void)
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{
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return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
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}
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static inline ecc_curve_t ecc_ll_get_curve(void)
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{
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return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
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}
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static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
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{
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uint32_t reg;
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switch (param) {
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case ECC_PARAM_PX:
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reg = ECC_MULT_PX_1_REG;
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break;
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case ECC_PARAM_PY:
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reg = ECC_MULT_PY_1_REG;
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break;
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case ECC_PARAM_K:
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reg = ECC_MULT_K_1_REG;
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break;
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default:
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HAL_ASSERT(false && "Invalid parameter");
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return;
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}
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memcpy(buf, (void *)reg, len);
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}
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static inline void ecc_ll_enable_constant_time_point_mul(bool enable)
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{
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// Not supported for ESP32-C2
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(void) enable; //unused
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,185 @@
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/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "soc/hwcrypto_reg.h"
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#include "soc/system_struct.h"
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#include "hal/sha_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for SHA peripheral module
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*
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* @param enable true to enable the module, false to disable the module
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*/
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static inline void sha_ll_enable_bus_clock(bool enable)
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{
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SYSTEM.perip_clk_en1.crypto_sha_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sha_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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sha_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the SHA peripheral module
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*/
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static inline void sha_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en1.crypto_sha_rst = 1;
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SYSTEM.perip_rst_en1.crypto_sha_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sha_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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sha_ll_reset_register(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Load the mode for the SHA engine
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_set_mode(esp_sha_type sha_type)
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{
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REG_WRITE(SHA_MODE_REG, sha_type);
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}
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/**
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* @brief Start a new SHA block conversions (no initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_start_block(esp_sha_type sha_type)
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{
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(void) sha_type;
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REG_WRITE(SHA_START_REG, 1);
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}
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/**
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* @brief Continue a SHA block conversion (initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_continue_block(esp_sha_type sha_type)
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{
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(void) sha_type;
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REG_WRITE(SHA_CONTINUE_REG, 1);
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}
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/**
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* @brief Start a new SHA message conversion using DMA (no initial hash in HW)
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*/
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static inline void sha_ll_start_dma(void)
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{
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REG_WRITE(SHA_DMA_START_REG, 1);
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}
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/**
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* @brief Continue a SHA message conversion using DMA (initial hash in HW)
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*/
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static inline void sha_ll_continue_dma(void)
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{
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REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
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}
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/**
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* @brief Load the current hash digest to digest register
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*
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* @note Happens automatically on ESP32S3
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_load(esp_sha_type sha_type)
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{
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}
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/**
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* @brief Sets the number of message blocks to be hashed
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*
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* @note DMA operation only
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*
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* @param num_blocks Number of message blocks to process
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*/
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static inline void sha_ll_set_block_num(size_t num_blocks)
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{
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REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks);
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}
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/**
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* @brief Checks if the SHA engine is currently busy hashing a block
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*
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* @return true SHA engine busy
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* @return false SHA engine idle
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*/
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static inline bool sha_ll_busy(void)
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{
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return REG_READ(SHA_BUSY_REG);
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}
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/**
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* @brief Write a text (message) block to the SHA engine
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*
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* @param input_text Input buffer to be written to the SHA engine
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* @param block_word_len Number of words in block
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*/
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static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
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{
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uint32_t *data_words = (uint32_t *)input_text;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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for (int i = 0; i < block_word_len; i++) {
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REG_WRITE(®_addr_buf[i], data_words[i]);
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}
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}
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/**
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* @brief Read the message digest from the SHA engine
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*
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* @param sha_type The SHA algorithm type
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* @param digest_state Buffer that message digest will be written to
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* @param digest_word_len Length of the message digest
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*/
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static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < digest_word_len; i++) {
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digest_state_words[i] = REG_READ(SHA_H_BASE + (i * REG_WIDTH));
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}
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}
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/**
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* @brief Write the message digest to the SHA engine
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*
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* @param sha_type The SHA algorithm type
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* @param digest_state Message digest to be written to SHA engine
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* @param digest_word_len Length of the message digest
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*/
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static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE);
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for (int i = 0; i < digest_word_len; i++) {
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REG_WRITE(®_addr_buf[i], digest_state_words[i]);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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