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refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio
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@@ -555,10 +555,6 @@ config SOC_GPIO_SUPPORT_ETM
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bool
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default y
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config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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bool
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default y
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config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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bool
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default y
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@@ -623,10 +619,6 @@ config SOC_RTCIO_WAKE_SUPPORTED
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bool
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default y
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config SOC_RTCIO_EDGE_WAKE_SUPPORTED
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bool
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default y
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config SOC_SDM_SUPPORT_SLEEP_RETENTION
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bool
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default y
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@@ -219,8 +219,6 @@
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#define SOC_GPIO_SUPPORT_ETM 1
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// Target has the full LP IO subsystem
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// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
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#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
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// LP IO peripherals have independent clock gating to manage
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@@ -256,7 +254,6 @@
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*/
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
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/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
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#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
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@@ -9,14 +9,6 @@
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#include "soc/soc_caps.h"
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#include "soc/soc_caps_eval.h"
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/*------------------------------- Dedicated GPIO ------------------------------*/
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#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
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#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
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/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
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#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
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#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
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/*------------------------------- I2S ---------------------------------------*/
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// helper macros to access module attributes
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#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
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