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Merge branch 'bugfix/chip764_clk_tree_ll_pll_update' into 'master'

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fix(pmu): update cpll_bbpll_apll_mpll enable config

See merge request espressif/esp-idf!47901
This commit is contained in:
Chai Ji’e
2026-04-29 19:54:08 +08:00
parent f27907591d 12491d21cf
commit 4ce06f5ea1
4 changed files with 206 additions and 14 deletions
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components/soc/esp32s31/register/soc/pmu_reg.h
+170
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@@ -1877,6 +1877,176 @@ extern "C" {
#define PMU_TIE_HIGH_XPD_PLL_M (PMU_TIE_HIGH_XPD_PLL_V << PMU_TIE_HIGH_XPD_PLL_S)
#define PMU_TIE_HIGH_XPD_PLL_V 0x0000000FU
#define PMU_TIE_HIGH_XPD_PLL_S 27
/** PMU_TIE_LOW_XPD_CPLL_I2C : WT; bitpos: [0]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_CPLL_I2C (BIT(0))
#define PMU_TIE_LOW_XPD_CPLL_I2C_M (PMU_TIE_LOW_XPD_CPLL_I2C_V << PMU_TIE_LOW_XPD_CPLL_I2C_S)
#define PMU_TIE_LOW_XPD_CPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_CPLL_I2C_S 0
/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [1]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(1))
#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S)
#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 1
/** PMU_TIE_LOW_XPD_APLL_I2C : WT; bitpos: [2]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_APLL_I2C (BIT(2))
#define PMU_TIE_LOW_XPD_APLL_I2C_M (PMU_TIE_LOW_XPD_APLL_I2C_V << PMU_TIE_LOW_XPD_APLL_I2C_S)
#define PMU_TIE_LOW_XPD_APLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_APLL_I2C_S 2
/** PMU_TIE_LOW_XPD_MPLL_I2C : WT; bitpos: [3]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_MPLL_I2C (BIT(3))
#define PMU_TIE_LOW_XPD_MPLL_I2C_M (PMU_TIE_LOW_XPD_MPLL_I2C_V << PMU_TIE_LOW_XPD_MPLL_I2C_S)
#define PMU_TIE_LOW_XPD_MPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_MPLL_I2C_S 3
/** PMU_TIE_LOW_XPD_CPLL : WT; bitpos: [4]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_CPLL (BIT(4))
#define PMU_TIE_LOW_XPD_CPLL_M (PMU_TIE_LOW_XPD_CPLL_V << PMU_TIE_LOW_XPD_CPLL_S)
#define PMU_TIE_LOW_XPD_CPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_CPLL_S 4
/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_BBPLL (BIT(5))
#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S)
#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_BBPLL_S 5
/** PMU_TIE_LOW_XPD_APLL : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_APLL (BIT(6))
#define PMU_TIE_LOW_XPD_APLL_M (PMU_TIE_LOW_XPD_APLL_V << PMU_TIE_LOW_XPD_APLL_S)
#define PMU_TIE_LOW_XPD_APLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_APLL_S 6
/** PMU_TIE_LOW_XPD_MPLL : WT; bitpos: [7]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_MPLL (BIT(7))
#define PMU_TIE_LOW_XPD_MPLL_M (PMU_TIE_LOW_XPD_MPLL_V << PMU_TIE_LOW_XPD_MPLL_S)
#define PMU_TIE_LOW_XPD_MPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_MPLL_S 7
/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [8]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG (BIT(8))
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_M (PMU_TIE_LOW_GLOBAL_CPLL_ICG_V << PMU_TIE_LOW_GLOBAL_CPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_S 8
/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [9]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(9))
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 9
/** PMU_TIE_LOW_GLOBAL_APLL_ICG : WT; bitpos: [10]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_APLL_ICG (BIT(10))
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_M (PMU_TIE_LOW_GLOBAL_APLL_ICG_V << PMU_TIE_LOW_GLOBAL_APLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_S 10
/** PMU_TIE_LOW_GLOBAL_MPLL_ICG : WT; bitpos: [11]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG (BIT(11))
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_M (PMU_TIE_LOW_GLOBAL_MPLL_ICG_V << PMU_TIE_LOW_GLOBAL_MPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_S 11
/** PMU_TIE_HIGH_GLOBAL_CPLL_ICG : R/W; bitpos: [19]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG (BIT(19))
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S 19
/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : R/W; bitpos: [20]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(20))
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 20
/** PMU_TIE_HIGH_GLOBAL_APLL_ICG : R/W; bitpos: [21]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG (BIT(21))
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_M (PMU_TIE_HIGH_GLOBAL_APLL_ICG_V << PMU_TIE_HIGH_GLOBAL_APLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_S 21
/** PMU_TIE_HIGH_GLOBAL_MPLL_ICG : R/W; bitpos: [22]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG (BIT(22))
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_MPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_MPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_S 22
/** PMU_TIE_HIGH_XPD_CPLL_I2C : WT; bitpos: [23]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_CPLL_I2C (BIT(23))
#define PMU_TIE_HIGH_XPD_CPLL_I2C_M (PMU_TIE_HIGH_XPD_CPLL_I2C_V << PMU_TIE_HIGH_XPD_CPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_CPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_CPLL_I2C_S 23
/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [24]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(24))
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 24
/** PMU_TIE_HIGH_XPD_APLL_I2C : WT; bitpos: [25]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_APLL_I2C (BIT(25))
#define PMU_TIE_HIGH_XPD_APLL_I2C_M (PMU_TIE_HIGH_XPD_APLL_I2C_V << PMU_TIE_HIGH_XPD_APLL_I2C_S)
#define PMU_TIE_HIGH_XPD_APLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_APLL_I2C_S 25
/** PMU_TIE_HIGH_XPD_MPLL_I2C : WT; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_MPLL_I2C (BIT(26))
#define PMU_TIE_HIGH_XPD_MPLL_I2C_M (PMU_TIE_HIGH_XPD_MPLL_I2C_V << PMU_TIE_HIGH_XPD_MPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_MPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_MPLL_I2C_S 26
/** PMU_TIE_HIGH_XPD_CPLL : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_CPLL (BIT(27))
#define PMU_TIE_HIGH_XPD_CPLL_M (PMU_HP_ACTIVE_XPD_CPLL_V << PMU_HP_ACTIVE_XPD_CPLL_S)
#define PMU_TIE_HIGH_XPD_CPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_CPLL_S 27
/** PMU_TIE_HIGH_XPD_BBPLL : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_BBPLL (BIT(28))
#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S)
#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_BBPLL_S 28
/** PMU_TIE_HIGH_XPD_APLL : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_APLL (BIT(29))
#define PMU_TIE_HIGH_XPD_APLL_M (PMU_HP_ACTIVE_XPD_APLL_V << PMU_HP_ACTIVE_XPD_APLL_S)
#define PMU_TIE_HIGH_XPD_APLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_APLL_S 29
/** PMU_TIE_HIGH_XPD_MPLL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_MPLL (BIT(30))
#define PMU_TIE_HIGH_XPD_MPLL_M (PMU_HP_ACTIVE_XPD_MPLL_V << PMU_HP_ACTIVE_XPD_MPLL_S)
#define PMU_TIE_HIGH_XPD_MPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_MPLL_S 30
/** PMU_IMM_SLEEP_SYSCLK_REG register
* need_des