fix(cache): fixed cache sys clk not on issue

This commit is contained in:
armando
2026-03-31 15:58:27 +08:00
parent ebbd9cdb59
commit 4bea0ccb22
17 changed files with 130 additions and 39 deletions
@@ -245,9 +245,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con
}
}
ESP_DRAM_LOGW(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
ESP_DRAM_LOGD(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
for (config_idx = 0; config_idx < timing_config->available_config_num; config_idx++) {
ESP_DRAM_LOGW(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
ESP_DRAM_LOGD(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
}
}
@@ -481,6 +481,18 @@ void mspi_timing_psram_tuning(void)
/*------------------------------------------------------------------------------
* APIs to make SPI0 (and SPI1) FLASH work for high/low freq
*----------------------------------------------------------------------------*/
void __attribute__((weak)) mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
{
(void)control_both_mspi;
//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
}
void __attribute__((weak)) mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
{
(void)control_both_mspi;
//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
}
uint32_t mspi_timing_get_psram_low_speed_freq_mhz(void)
{
return 20;
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -157,24 +157,6 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi);
*/
void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi);
/**
* @brief Set Flash timing tuning settings
*
* This is used when the system is going to high speed mode / MSPI needs to be run in high speed
*
* @param[in] control_both_mspi Control MSPI1 as well
*/
void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi);
/**
* @brief Clear Flash timing tuning settings
*
* This is used when the system is going into low speed mode / MSPI doesn't need to be run in high speed
*
* @param[in] control_both_mspi Control MSPI1 as well
*/
void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi);
#endif //#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
#ifdef __cplusplus
@@ -240,13 +240,3 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi)
}
}
}
void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
{
//for compatibility
}
void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
{
//for compatibility
}