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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
fix(cache): fixed cache sys clk not on issue
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@@ -245,9 +245,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con
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}
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}
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ESP_DRAM_LOGW(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
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ESP_DRAM_LOGD(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
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for (config_idx = 0; config_idx < timing_config->available_config_num; config_idx++) {
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ESP_DRAM_LOGW(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
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ESP_DRAM_LOGD(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
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}
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}
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@@ -481,6 +481,18 @@ void mspi_timing_psram_tuning(void)
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/*------------------------------------------------------------------------------
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* APIs to make SPI0 (and SPI1) FLASH work for high/low freq
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*----------------------------------------------------------------------------*/
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void __attribute__((weak)) mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
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{
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(void)control_both_mspi;
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//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
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}
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void __attribute__((weak)) mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
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{
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(void)control_both_mspi;
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//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
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}
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uint32_t mspi_timing_get_psram_low_speed_freq_mhz(void)
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{
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return 20;
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+1
-19
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -157,24 +157,6 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi);
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*/
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void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi);
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/**
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* @brief Set Flash timing tuning settings
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*
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* This is used when the system is going to high speed mode / MSPI needs to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI1 as well
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*/
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void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi);
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/**
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* @brief Clear Flash timing tuning settings
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*
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* This is used when the system is going into low speed mode / MSPI doesn't need to be run in high speed
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*
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* @param[in] control_both_mspi Control MSPI1 as well
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*/
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void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi);
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#endif //#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
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#ifdef __cplusplus
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-10
@@ -240,13 +240,3 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi)
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}
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}
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}
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void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
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{
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//for compatibility
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}
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void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
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{
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//for compatibility
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}
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