feat(ledc): support ledc sleep mode selection

Support LEDC sleep retention on C6/H2/P4

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -483,6 +483,10 @@ config SOC_LEDC_SUPPORT_HS_MODE
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8

components/soc/esp32/include/soc/soc_caps.h

@@ -241,6 +241,7 @@
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_REF_TICK        (1)
 #define SOC_LEDC_SUPPORT_HS_MODE         (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (20)
 

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -383,6 +383,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6

components/soc/esp32c2/include/soc/soc_caps.h

@@ -170,6 +170,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK  (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK     (1)
+#define SOC_LEDC_TIMER_NUM              (4)
 #define SOC_LEDC_CHANNEL_NUM            (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH        (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP      (1)

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -527,6 +527,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6

components/soc/esp32c3/include/soc/soc_caps.h

@@ -223,6 +223,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -695,6 +695,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6

components/soc/esp32c5/include/soc/retention_periph_defs.h

@@ -40,6 +40,8 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_ETM0         = 17,
     SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 18,
     SLEEP_RETENTION_MODULE_PARLIO0      = 19,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 20,
+    SLEEP_RETENTION_MODULE_LEDC         = 21,
 
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -82,6 +84,8 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
     SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR  = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR),
     SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
 
     SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
     SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
@@ -106,6 +110,8 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_ETM0        \
                                   | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \
                                   | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
                                   )
 #ifdef __cplusplus
 }

components/soc/esp32c5/include/soc/soc_caps.h

@@ -294,6 +294,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)

components/soc/esp32c5/ledc_periph.c

@@ -15,3 +15,7 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
     }
 };
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -687,6 +687,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -711,6 +715,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PAGE_SIZE_CONFIGURABLE
     bool
     default y

components/soc/esp32c6/include/soc/retention_periph_defs.h

@@ -42,6 +42,8 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_TWAI0        = 19,
     SLEEP_RETENTION_MODULE_TWAI1        = 20,
     SLEEP_RETENTION_MODULE_PARLIO0      = 21,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 22,
+    SLEEP_RETENTION_MODULE_LEDC         = 23,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -80,6 +82,8 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_TWAI0        = BIT(SLEEP_RETENTION_MODULE_TWAI0),
     SLEEP_RETENTION_MODULE_BM_TWAI1        = BIT(SLEEP_RETENTION_MODULE_TWAI1),
     SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
     SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
@@ -108,6 +112,8 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_TWAI0       \
                                   | SLEEP_RETENTION_MODULE_BM_TWAI1       \
                                   | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
                                   )
 
 #ifdef __cplusplus

components/soc/esp32c6/include/soc/soc_caps.h

@@ -279,12 +279,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)

components/soc/esp32c6/ledc_periph.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,139 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
 	}
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore.
+ * 		   We won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a constant duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+	// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -451,6 +451,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6

components/soc/esp32c61/include/soc/retention_periph_defs.h

@@ -34,6 +34,8 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_UART0        = 14,
     SLEEP_RETENTION_MODULE_UART1        = 15,
     SLEEP_RETENTION_MODULE_ETM0         = 16,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 17,
+    SLEEP_RETENTION_MODULE_LEDC         = 18,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -64,6 +66,8 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
     SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
     SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
     SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
@@ -84,6 +88,8 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_UART0       \
                                   | SLEEP_RETENTION_MODULE_BM_UART1       \
                                   | SLEEP_RETENTION_MODULE_BM_ETM0        \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
                                   )
 
 #ifdef __cplusplus

components/soc/esp32c61/include/soc/soc_caps.h

@@ -245,6 +245,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)

components/soc/esp32c61/ledc_periph.c

@@ -15,3 +15,7 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
     }
 };
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -691,6 +691,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -715,6 +719,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
     bool
     default n

components/soc/esp32h2/include/soc/retention_periph_defs.h

@@ -42,6 +42,8 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 19,
     SLEEP_RETENTION_MODULE_TWAI0        = 20,
     SLEEP_RETENTION_MODULE_PARLIO0      = 21,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 22,
+    SLEEP_RETENTION_MODULE_LEDC         = 23,
 
     /* Modem module, which includes BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
@@ -78,6 +80,8 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR  = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR),
     SLEEP_RETENTION_MODULE_BM_TWAI0        = BIT(SLEEP_RETENTION_MODULE_TWAI0),
     SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
     /* modem module, which includes BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
     SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
@@ -104,6 +108,8 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \
                                   | SLEEP_RETENTION_MODULE_BM_TWAI0       \
                                   | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
                                   )
 
 #ifdef __cplusplus

components/soc/esp32h2/include/soc/soc_caps.h

@@ -280,12 +280,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MPU CAPS ----------------------------------------*/
 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0

components/soc/esp32h2/ledc_periph.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,139 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
 	}
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore.
+ * 		   We won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a constant duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+	// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1023,6 +1023,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8
@@ -1047,6 +1051,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PERIPH_NUM
     int
     default 2

components/soc/esp32p4/include/soc/pmu_icg_mapping.h

@@ -6,8 +6,6 @@
 
 #pragma once
 
-// TODO: IDF-5731
-
 #define PMU_ICG_APB_ENA_CORE0_CPU          0
 #define PMU_ICG_APB_ENA_CORE1_CPU          1
 #define PMU_ICG_APB_ENA_CORE0_CLIC         2

components/soc/esp32p4/include/soc/retention_periph_defs.h

@@ -50,6 +50,9 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_TWAI1        = 26,
     SLEEP_RETENTION_MODULE_TWAI2        = 27,
     SLEEP_RETENTION_MODULE_PARLIO0      = 28,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 29,
+    SLEEP_RETENTION_MODULE_GPSPI3       = 30,
+    SLEEP_RETENTION_MODULE_LEDC         = 31,
 
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
@@ -90,6 +93,9 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_TWAI1        = BIT(SLEEP_RETENTION_MODULE_TWAI1),
     SLEEP_RETENTION_MODULE_BM_TWAI2        = BIT(SLEEP_RETENTION_MODULE_TWAI2),
     SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_GPSPI3       = BIT(SLEEP_RETENTION_MODULE_GPSPI3),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
 
     SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
 } periph_retention_module_bitmap_t;
@@ -121,6 +127,9 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_TWAI1      \
                                   | SLEEP_RETENTION_MODULE_BM_TWAI2      \
                                   | SLEEP_RETENTION_MODULE_BM_PARLIO0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI3     \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC       \
                                   )
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/soc_caps.h

@@ -379,12 +379,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PERIPH_NUM                    (2U)

components/soc/esp32p4/ledc_periph.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,160 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT_PAD_OUT0_IDX,
     }
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ * LEDC_CHx_GAMMA_CONF_REG, LEDC_CHx_GAMMA_RANGEi_REG
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a constant duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+    // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
+                                                 LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
+                                               LEDC_CH##chan##_GAMMA_RANGE0_REG, LEDC_CH##chan##_GAMMA_RANGE0_REG, \
+                                               SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, 0, 0, \
+                                               ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
+                                               ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+static const regdma_entries_config_t ledc_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(6);
+static const regdma_entries_config_t ledc_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(7);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+    .channel[6] = {
+		.regdma_entry_array = ledc_channel6_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel6_regdma_entries),
+	},
+    .channel[7] = {
+		.regdma_entry_array = ledc_channel7_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel7_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -535,6 +535,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8

components/soc/esp32s2/include/soc/soc_caps.h

@@ -233,6 +233,7 @@
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_REF_TICK        (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -603,6 +603,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8

components/soc/esp32s3/include/soc/soc_caps.h

@@ -236,6 +236,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)

components/soc/include/soc/ledc_periph.h

@@ -1,21 +1,18 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
+
 #include "soc/soc_caps.h"
 #include "soc/ledc_reg.h"
 #include "soc/ledc_struct.h"
+#if SOC_PAU_SUPPORTED
+#include "soc/regdma.h"
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -34,6 +31,33 @@ extern const ledc_signal_conn_t ledc_periph_signal[2];
 extern const ledc_signal_conn_t ledc_periph_signal[1];
 #endif
 
+#if SOC_PAU_SUPPORTED
+
+#if SOC_LIGHT_SLEEP_SUPPORTED
+#if SOC_PHY_SUPPORTED
+#define LEDC_RETENTION_ENTRY        (ENTRY(0) | ENTRY(2))
+#else
+#define LEDC_RETENTION_ENTRY        (ENTRY(0))
+#endif
+#else // !SOC_LIGHT_SLEEP_SUPPORTED
+#define LEDC_RETENTION_ENTRY        REGDMA_SW_TRIGGER_ENTRY
+#endif
+
+typedef struct {
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} ledc_sub_reg_retention_info_t;
+
+typedef struct {
+    ledc_sub_reg_retention_info_t common;
+    ledc_sub_reg_retention_info_t timer[SOC_LEDC_TIMER_NUM];
+    ledc_sub_reg_retention_info_t channel[SOC_LEDC_CHANNEL_NUM];
+    const periph_retention_module_t module_id;
+} ledc_reg_retention_info_t;
+
+extern const ledc_reg_retention_info_t ledc_reg_retention_info;
+#endif
+
 #ifdef __cplusplus
 }
 #endif

components/soc/include/soc/regdma.h

@@ -58,6 +58,8 @@ extern "C" {
 #define REGDMA_TSENS_LINK(_pri)             ((0x20 << 8) | _pri)
 #define REGDMA_TWAI_LINK(_pri)              ((0x21 << 8) | _pri)
 #define REGDMA_PARLIO_LINK(_pri)            ((0x22 << 8) | _pri)
+#define REGDMA_GPSPI_LINK(_pri)             ((0x23 << 8) | _pri)
+#define REGDMA_LEDC_LINK(_pri)              ((0x24 << 8) | _pri)
 #define REGDMA_MODEM_FE_LINK(_pri)          ((0xFF << 8) | _pri)
 
 #define REGDMA_LINK_PRI_SYS_CLK                 REGDMA_LINK_PRI_0
@@ -80,6 +82,8 @@ extern "C" {
 #define REGDMA_LINK_PRI_UART                    REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_TEMPERATURE_SENSOR      REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_TWAI                    REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_GPSPI                   REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_LEDC                    REGDMA_LINK_PRI_GENERAL_PERIPH
 
 typedef enum {
     REGDMA_LINK_PRI_0 = 0,