From 4a70fc80c3b4df079099e4fc7e9abb0f139269b7 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 11 Sep 2026 19:49:26 +0800 Subject: [PATCH] fix(esp_hw_support): disable BBPLL after sleep if clk_tree ref is zero PLL_SOURCE retention may leave BBPLL on; sync HW in pmu_sleep_finish and keep is_power_on in IRAM. Co-authored-by: Cursor --- components/esp_hw_support/linker.lf | 4 ++-- components/esp_hw_support/port/esp32s31/pmu_sleep.c | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index c318e068bdc..2f164f45fe4 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -14,10 +14,10 @@ entries: esp_memory_utils (noflash) clk_utils (noflash) esp_clk_tree: esp_clk_tree_enable_src (noflash) + esp_clk_tree:esp_clk_tree_port_is_power_on (noflash) + esp_clk_tree_common:esp_clk_tree_is_power_on (noflash) if RTC_CLK_FUNC_IN_IRAM = y: esp_clk_tree:esp_clk_tree_enable_power (noflash) - esp_clk_tree:esp_clk_tree_port_is_power_on (noflash) - esp_clk_tree_common:esp_clk_tree_is_power_on (noflash) if SOC_CLK_MPLL_SUPPORTED = y: esp_clk_tree_common:esp_clk_tree_mpll_release (noflash) if SOC_CLK_APLL_SUPPORTED = y: diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 42c0398c089..a11070fe1c5 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -14,9 +14,12 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/pmu_struct.h" +#include "soc/hp_sys_clkrst_struct.h" #include "esp_private/esp_pmu.h" +#include "esp_private/esp_clk_tree_common.h" #include "pmu_param.h" #include "hal/clk_tree_hal.h" +#include "hal/clk_tree_ll.h" #include "hal/lp_aon_hal.h" #include "hal/efuse_ll.h" #include "hal/efuse_hal.h" @@ -403,6 +406,10 @@ bool pmu_sleep_finish(bool dslp) esp_psram_impl_exit_halfsleep_mode(); #endif #endif + /* PLL_SOURCE retention may leave BBPLL powered on; align HW to clk_tree ref. */ + if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL) && !HP_SYS_CLKRST.modem_conf.modem_pll_clk_en) { + clk_ll_bbpll_disable(); + } } #if !SOC_APM_SUPPORTED