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fix(ulp): record wakeup causes before lp core request sleep

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This commit is contained in:
hebinglin
2026-06-01 21:11:48 +08:00
parent 8c59da477b
commit 4a42a8847b
18 changed files with 148 additions and 18 deletions
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components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
+3 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -52,6 +52,7 @@ extern "C" {
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
* LP_AON_STORE9_REG LP core store wakeup cause
*************************************************************************************
*/
@@ -64,6 +65,7 @@ extern "C" {
#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG
#define RTC_LP_CORE_STORE_WAKEUP_REG LP_AON_STORE9_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
components/esp_rom/esp32c6/include/esp32c6/rom/rtc.h
+2
View File
@@ -53,6 +53,7 @@ extern "C" {
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
* LP_AON_STORE10_REG LP core store wakeup cause at bit[31:2]
*************************************************************************************
*/
@@ -66,6 +67,7 @@ extern "C" {
#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define RTC_SLEEP_MODE_REG LP_AON_STORE9_REG
#define RTC_LP_CORE_STORE_WAKEUP_REG LP_AON_STORE9_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
components/esp_rom/esp32p4/include/esp32p4/rom/rtc.h
+11 -9
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,17 +53,19 @@ extern "C" {
* LP_SYS_LP_STORE8_REG sleep mode and wake stub address
* LP_SYS_LP_STORE9_REG LP_UART_INIT_CTRL
* LP_SYS_LP_STORE10_REG LP_ROM_LOG_CTRL
* LP_SYS_LP_STORE11_REG LP core store wakeup cause
*************************************************************************************
*/
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_APB_FREQ_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_SYSTEM_REG_LP_STORE7_REG
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_APB_FREQ_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_SYSTEM_REG_LP_STORE7_REG
#define RTC_LP_CORE_STORE_WAKEUP_REG LP_SYSTEM_REG_LP_STORE11_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.